Numonyx Wireless Flash Memory Datasheet

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Numonyx™ Wireless Flash Memory (W18/W30 SCSP)

32WQ and 64WQ Family with Asynchronous RAM

Product Features

Datasheet

 Device Architecture

— Flash Density: 32-Mbit, 64-Mbit — Async PSRAM Density: 16-Mbit, 32-Mbit — Top, Bottom or Dual flash parameter

configuration

 Device Voltage

— Flash VCC = 1.8 V; Flash VCCQ = 1.8 V or 3.0 V — RAM VCC = 1.8 V or 3.0 V

 Device Packaging

— 88 balls (8 x 10 active ball matrix) — Area: 8x10 mm — Height: 1.2 mm to 1.4 mm

 PSRAM Performance

— 70 ns initial access, 25 ns async page reads at

1.8 V I/O

— 70 ns initial access async PSRAM at 1.8 V

I/O

— 70 ns initial access, 25 ns async page

reads at 3.0 V I/O

 SRAM Performance

— 70 ns initial access at 1.8 V or 3.0 V I/O

 Quality and Reliability

— Extended Temperature: –25 °C to +85 °C — Minimum 100K flash block erase cycle — 90 nm ETOX™ IX flash technology — 130 nm ETOX™ VIII flash technology

 Flash Performance

— 65 ns initial access at 1.8 V I/O — 70 ns initial access at 3.0 V I/O — 25 ns async page at 1.8 V or 3.0 V I/O — 14 ns sync reads (t — 20 ns sync reads (t — Enhanced Factory Programming:

3.10 µs/Word (Typ)

 Flash Architecture

— Read-While-Write/Erase — Asymmetrical blocking structure — 4-KWord parameter blocks (Top or

Bottom) — 32-KWord main blocks — 4-Mbit partition size — 128-bit One-Time Programmable

(OTP) Protection Register — Zero-latency block locking — Absolute write protection with block

lock using F-VPP and F-WP#

 Flash Software

— Numonyx™ Flash Data Integrator

(FDI) and Common Flash Interface

(CFI)

) at 1.8 V I/O

CHQV

) at 3.0 V I/O

CHQV

Order Number: 251407-13

November 2007

LLegal Lines and Disclaimers

INF OR MAT ION IN TH IS D OC UM ENT IS PR OVIDE D I N CON NEC TI ON WIT H N UM ONY X™ PR OD UCT S. NO L IC EN SE , EX PR ESS OR IM PLI ED, BY ES TOP PE L OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING L IABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPO SE, MERCHANTABIL ITY, OR INFRIN GEMENT OF AN Y PATENT, COPYRIGHT OR OTHE R INTEL LECTUAL PROPERTY RIGHT. Numonyx products are not intende d for use in medical, life saving, life sustaining, cr itical control or safety sy stems, or in nuclear facility applications.

Numonyx B.V. may make changes to specifications and product descriptions at any time, without notice.

Numonyx B.V. may have patents or pending patent applica tions, tradema rks, copyrights, or other in tellectual property rights that relat e to th e presen ted subject mat ter. The furnis hing of docu ments and other ma terials and information does not provide any license, expres s or implied, by estopp el or otherwise , to any such pate nts, trade marks, co pyrights, or other intellect ual prope rty rights.

Designer s must not rely on the absence or charact eristics o f any featu res or instruction s marked “reserve d” or “unde fined.” Numonyx r eserve s these f or future definit ion and shall have no responsibility whatsoever f or conflicts or incompat ibilities arisin g from future changes to them.

Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com.

Numonyx, the Numonyx logo, and StrataFlash are trademarks or registered trademarks of Numonyx B.V. or its subsidiaries in other countries.

*Other n ames and brands may be claim ed as the propert y of oth ers.

Datasheet November 2007 2 Order Number: 251407-13

32WQ and 64WQ Family with Asynchronous RAM

Contents

1.0 Introduction .............................................................................................................. 6

1.1 Nomenclature ..................................................................................................... 6

1.2 Conventions ....................................................................................................... 7

2.0 Functional Overview.................................................................................................. 8

2.1 Block Diagram .................................................................................................... 8

2.2 Flash Memory Map and Partitioning ........................................................................ 9

3.0 Package Information ............................................................................................... 10

4.0 Ballout and Signal Description ................................................................................. 13

4.1 Signal Ballout ................................................................................................... 13

4.2 Signal Descriptions ............................................................................................ 14

5.0 Maximum Ratings and Operating Conditions............................................................ 16

5.1 Absolute Maximum Ratings ................................................................................. 16

5.2 Operating Conditions ......................................................................................... 16

5.3 Capacitance...................................................................................................... 17

6.0 Electrical Specifications ........................................................................................... 18

6.1 DC Characteristics ............................................................................................. 18

7.0 AC Characteristics ................................................................................................... 20

7.1 Flash AC Characteristics ..................................................................................... 20

7.2 SRAM AC Characteristics .................................................................................... 20

7.3 PSRAM AC Characteristics................................................................................... 22

7.4 Device AC Test Conditions .................................................................................. 27

8.0 Flash Power Consumption ....................................................................................... 28

9.0 Device Operation ..................................................................................................... 29

9.1 Bus Operations ................................................................................................. 29

10.0 Flash Command Definitions ..................................................................................... 33

11.0 Flash Read Operations............................................................................................. 33

12.0 Flash Program Operations ....................................................................................... 33

13.0 Flash Erase Operations ............................................................................................ 33

14.0 Flash Security Modes ............................................................................................... 33

15.0 Flash Read Configuration Register........................................................................... 33

16.0 SRAM Operations ..................................................................................................... 34

16.1 Power-up Sequence and Initialization ................................................................... 34

16.2 Data Retention Mode ......................................................................................... 34

17.0 PSRAM Operations................................................................................................... 36

17.1 Power-Up Sequence and Initialization................................................................... 36

17.1.1 16Mbit PSRAM Power-Up Sequence (Non-Page Mode).................................. 36

17.2 Standby Mode/ Deep Power-Down Mode............................................................... 37

17.3 PSRAM Special Read and Write Constraints ........................................................... 37

A Write State Machine ................................................................................................ 38

B Common Flash Interface.......................................................................................... 38

C Flash Flowcharts ..................................................................................................... 38

D Additional Information ............................................................................................ 38

November 2007 Datasheet Order Number: 251407-13 3

32WQ and 64WQ Family with Asynchronous RAM

E Ordering Information (Active Line Items)................................................................39

F Ordering Information (Retired Line Items) ..............................................................40

Datasheet November 2007 4 Order Number: 251407-13

32WQ and 64WQ Family with Asynchronous RAM

Revision History

Date Revision Description

June 2003 -001 Initial release

September

2003

May 2004 -006 Reformatted the datasheet and moved sections around according to the new layout.

August 2004 -007

January 2005 -008

June 2005 -009 Added line items.

October 2005 -010

June 2007 -011

August 2007 -012

November 2007 13 Applied Numonyx branding.

-002

Changed PSRAM Read values. Added new Transient Equivalent Testing Load Circuit figure. General text edits.

Added 90 nm product information. Added line items. Added DC and AC specs for the new line items and edits to related sections.

Added line items. Added 32WQ product information.

Removed Power-up sequence from Section 16; Added 70ns PSRAM (non-page mode) specification Updated Ordering Information

Updated Ordering information with active and retired line items. Updated AC spec & power-up specs for 38F2030W0YxQE & 38F2040W0YxQE

Rempved 38F2030W0YxQE & 38F2040W0YxQE Line Items Updated ordering information

November 2007 Datasheet Order Number: 251407-13 5

1.0 Introduction

This document contains information pertaining to the products in the Numonyx™ Wireless Flash Memory (W18/W30 SCSP) family with asynchronous RAM. The W18/ W30 SCSP 32WQ and 64WQ families offer a wide variety of stacked combinations that include single flash die, two flash die, flash + PSRAM, and flash + SRAM options. This document provides information where this SCSP family differs from the Numonyx Wireless Flash Memory (W18/W30) discrete device.

Refer to the discrete datasheets Numonyx™ Wireless Flash Memory (W18) Datasheet (order number 290701) and Numonyx™ Wireless Flash Memory (W30) Datasheet (order number 290702) for flash product details not included in this SCSP datasheet.

The Numonyx Wireless Flash Memory (W18/W30 SCSP) family offers various flash plus static RAM combinations in a common package footprint. The flash memory features

1.8 V low-power operations with flexible, multi-partition, dual-operation Read-WhileWrite / Read-While-Erase, asynchronous, and synchronous reads. This SCSP device integrates up to two flash die, and one PSRAM or SRAM die in a low-profile package compatible with other SCSP families with QUAD+ ballout.

1.1 Nomenclature

0x Hexadecimal prefix

32WQ and 64WQ Family with Asynchronous RAM

0b Binary prefix

Byte 8 bits

CFI Common Flash Interface

CUI Command User Interface

DU Don’t Use

ETOX EPROM Tunnel Oxide

FDI Numonyx™ Flash Data Integrator (software solution)

K(noun) 1 thousand

Kb 1024 bits

KB 1024 bytes

Kword 1024 words

M (noun) 1 million

Mb 1,048,576 bits

MB 1,048,576 bytes

OTP One-Time Programmable

PLR Protection Lock Register

PR Protection Register

PRD Protection Register Data

RCR Read Configuration Register

Datasheet November 2007 6 Order Number: 251407-13

32WQ and 64WQ Family with Asynchronous RAM

RFU Reserved for Future Use

SCSP Stacked Chip Scale Package

SR Status Register

SRD Status Register Data

Word 16 bits

WSM Write State Machine

1.2 Conventions

Group Membership Brackets: Square brackets are used to designate group membership or to define a group of signals with a similar function, such as A[21:1] and SR[4,1].

VCC vs. V used is VCC, etc. When referring to a timing or electrical level, the notation used is subscripted such as V

: When referring to a signal or package-connection name, the notation

, etc.

Device: This term is used i n ter chan geably throu ghou t this document to denote ei the r a particular die, or the combination of multiple die within a single package.

F[3:1]-CE#, F[2:1]-OE#: This is the method used to refer to more than one chipenable or output enable at the same time. When each is referred to individually, the reference will be F1-CE# and F1-OE# (for die #1), and F2-CE# and F2-OE# (for die #2).

F-VCC, P-VCC or S-VCC: When referencing flash memory signals or timings, the notation used is F-VCC or F-V or timings, the notation is prefixed with “P-” (e.g., P-VCC, P-V SRAM signals or timings, the notation is prefixed with “S-” (e.g., S-VCC or S-V VCC and S-VCC are RFU for stacked combinations that do not include PSRAM or SRAM.

respectively. When the reference is to PSRAM signals

CC,

). When referencing

). P-

R-OE#, R-LB#, R-UB#, R-WE#: These are used to identify RAM OE#, LB#, UB#, WE# signals, and are usually shared between 2 or more RAM die. R-OE#, R-LB#, RUB# and R-WE are RFU for stacked combinations that do not include PSRAM or SRAM.

November 2007 Datasheet Order Number: 251407-13 7

2.0 Functional Overview

This section provides an overview of the features and capabilities of the Numonyx Wireless Flash Memory (W18/W30 SCSP) family with asynchronous RAM device.

The W18/W30 SCSP device provides flash + RAM die combinations. Products range from single flash die, two flash die, flash + PSRAM, or flash + SRAM. You can choose a W18 SCSP device or a W30 SCSP device with SRAM or PSRAM offered with the same package footprint and signal ballout.

2.1 Block Diagram

Show here are all internal package connections for the SCSP family with multiple die. See Table 21, “Ordering Information on Active Line Items” on page 40 for valid combinations of flash and RAM die. Unused connections on combinations with less than three die are reserved and should not be used.

Please contact your local Numonyx representative for details regarding any reserved or RFU pins.

Figure 1: Block Diagram

32WQ and 64WQ Family with Asynchronous RAM

F2-VCC

F2-CE#

F2-OE#

Flash Die #2

32- or 64-Mbit W18/W30

CLK

ADV#

F-WP#

F-RST#

Flash Die #1

F1-OE#

F1-CE#

F1-VCC

A[MAX:0]

A[MAX:0] D[15:0]

S-VCC/P-VCC P-CS#/S-CS1#

S-CS2

R-OE#

32- or 64-Mbit W18/W30

RAM Die

4-, 8-, 16-Mbit SRAM

16- or 32-Mbit PSRAM

F-WE# F-VPP VCCQ

WAIT

VSS

R-WE# P-MODE R-UB# R-LB#

Datasheet November 2007 8 Order Number: 251407-13

32WQ and 64WQ Family with Asynchronous RAM

2.2 Flash Memory Map and Partitioning

Consult the latest Numonyx™ Wireless Flash Memory (W18) Datasheet (order number

290701) and the Numonyx™ Wireless Flash Memory (W30) Datasheet (order number

290702), for individual flash die memory map and partitioning information.

Tab l e 1 and Ta b l e 2 show memory map and partitioning information for dual-flash

memory die configurations. Flash Die #1 (with F1-CE# as its Chip Select) is configured as a bottom parameter while Flash Die #2 (with F2-CE# as its Chip Select) is configured as top parameter.

November 2007 Datasheet Order Number: 251407-13 9

32WQ and 64WQ Family with Asynchronous RAM

3.0 Package Information

The following two packages are offered with the 32WQ and 64WQ Family.

Figure 2: Mechanical Specifications for 1- or 2-Die SCSP Device (8x10x1.2 mm)

A1 Index

Mark

123 456 78

Top View - Ball

Down

2345678

Bottom View - Ball Up

Drawi ng not to scale.

Millimeters Inches

Di me n s i on s S ymbol Mi n Nom Ma x No t e s Mi n No m Max

Package Heigh t A 1.200 0.0472 Ball Heig h t A1 0.200 0.0079 Package Body Thickne s s A2 0.860 0.0339 Ball (Lead) W idth b 0.325 0.375 0.425 0.0128 0.0148 0.0167 Package Body Len gth D 9.900 10.000 10.100 0.3898 0.3937 0.3976 Package Body W id th E 7.900 8.000 8.100 0.3110 0.3150 0.3189 Pitch e 0.800 0.0315 Ball (Lea d) Co u nt N 88 88 Seating Plane Coplanarity Y 0.100 0.0039 Corner t o Ball A1 Dis tan ce Along E S1 1.100 1.200 1.300 0.0433 0.0472 0.0512 Corner t o Ball A1 Dis tan ce Along D S2 0.500 0.600 0.700 0.0197 0.0236 0.0276

Datasheet November 2007 10 Order Number: 251407-13

32WQ and 64WQ Family with Asynchronous RAM

Figure 3: Mechanical Specifications for Triple-Die SCSP Device (8x10x1.4 mm)

Ind ex

Mark

12345678

Top View - Ball Down Bo tt om View - Ball Up

12345678

Drawing not to scale.

Millimeters Inches

Dimens i ons Symbol Min Nom Max Notes Min Nom Max

Pac kage Heigh t A 1.400 0.0551 Ball Heigh t A 1 0.200 0.0079 Package Body Thickness A2 1.070 0.0421 Ball (Lea d) W idth b 0.325 0.375 0.425 0.0128 0.0148 0.0167 Package Body Length D 9.900 10.000 10.100 0.3898 0.3937 0.3976 Package Body Width E 7.900 8.000 8.100 0.3110 0.3150 0.3189 Pitc h e 0.800 0.0315 Ball (Lead) Count N 88 88 Sea ting Plane Cop lan arity Y 0.100 0.0039 Corner to Ball A1 Distance Along E S1 1.100 1.200 1.300 0.0433 0.0472 0.0512 Corner to Ball A1 Distance Along D S2 0.500 0.600 0.700 0.0197 0.0236 0.0276

November 2007 Datasheet Order Number: 251407-13 11

32WQ and 64WQ Family with Asynchronous RAM

Table 1: 64-Mbit Flash + 32-Mbit Flash Die W18/W30 SCSP Memory Map and Partitioning

Block Size

(KW)

4 63-70 1F8000-1FFFFF

32 56-62 1C0000-1F7FFF

32 8-14 008000-03FFFF

4 0-7 000000-007FFF

Block # Address Range

Flash Die #2

(32-Mbit) To p

Parameter

Flash Die #1

(64-Mbit)

Bottom

Parameter

Partitioning

Parameter

Partition

Main Partitions

Parameter

Partition

Partition 0

Partition 1 32 48-55 180000-1BFFFF

Partition 2 32 40-47 140000-17FFFF

Partition 3 32 32-39 100000-13FFFF

Partitions 4-7 32 0-31 000000-0FFFFF

Partitions 8-15 32 71-134 200000-3FFFFF

Partitions 4-7 32 39-70 100000-1FFFFF

Partition 3 32 31-38 0C0000-0FFFFF

Partition 2 32 23-30 080000-0BFFFF

Partition 1 32 15-22 040000-07FFFF

Partition 0

Table 2: 64-Mbit Dual-Flash Die W18/W30 SCSP Memory Map and Partitioning

Partitioning

Block Size

(KW)

Block # Address Range

Parameter

Partition

Flash Die #2

(64-Mbit) Top

Parameter

Flash Die #1

(64-Mbit)

Bottom

Parameter

Datasheet November 2007 12 Order Number: 251407-13

Main Partitions

Parameter

Partition

Partition 0

Partition 1 32 112-119 380000-3BFFFF

Partition 2 32 104-111 340000-37FFFF

Partition 3 32 96-103 300000-33FFFF

Partitions 4-7 32 64-95 200000-2FFFFF

Partitions 8-15 32 0-63 000000-1FFFFF

Partitions 8-15 32 71-134 200000-3FFFFF

Partitions 4-7 32 39-70 100000-1FFFFF

Partition 3 32 31-38 0C0000-0FFFFF

Partition 2 32 23-30 080000-0BFFFF

Partition 1 32 15-22 040000-07FFFF

Partition 0

4 127-134 3F8000-3FFFFF

32 120-126 3C0000-3F7FFF

32 8-14 008000-03FFFF

4 0-7 000000-007FFF

32WQ and 64WQ Family with Asynchronous RAM

4.0 Ballout and Signal Description

4.1 Signal Ballout

Figure 4 shows the 32WQ and 64WQ W18/W30 SCSP family 88-ball (8x10 active ball

matrix) device.

Figure 4: 88-Ball (8x10 Active Ball Matrix) QUAD+ Ballout

Pin 1

12345678

A DU DU DU DU A

B A4 A18 A19 VSS F1-VCC F2-VCC A21 A11 B

C A5 R-LB# A23 VSS S-CS2 CLK A22 A12 C

D A3 A17 A24 F- VPP R-WE# P 1-C S# A9 A13 D

E A2 A7 A25 F-WP# ADV# A20 A10 A15 E

F A1 A6 R-UB# F-RST# F-WE# A8 A14 A16 F

G A0 DQ8 DQ2 DQ10 DQ5 DQ13 WAIT F2-CE# G

R-OE# DQ0 DQ1 DQ3 DQ12 DQ14 DQ7 F2-OE#

S-CS1# F1-OE# DQ9 DQ11 DQ4 DQ6 DQ15 VCCQ

F1-CE# P2-CS# F3-CE# S-VCC P-VCC F2-VCC VCCQ

VSS VSS VCCQ F1-VCC VSS VSS VSS VSS

DU DU DU DU

12345678

P-Mode/

P-CRE

Top View - Ball Side Down

Global Signals

Legend:

November 2007 Datasheet Order Number: 251407-13 13

De-Populated Balls

Flash Specific

SRAM/PSRAM Specific

Do Not Use

32WQ and 64WQ Family with Asynchronous RAM

4.2 Signal Descriptions

Table 3: Signal Descriptions (Sheet 1 of 2)

Symbol Type Name and Function

ADDRESS INPUTS: Inputs for all die addresses during read and write operations. Addresses are internally latched during write operations.

• 4-Mbit: A[17:0]

• 8-Mbit: A[18:0]

A[21:0] Input

D[15:0]

CLK Input

ADV# Input

WAIT Output

F[3:1]-CE# Input

S-CS1#

S-CS2

P[2:1]-CS# Input

F[2:1]-OE# Input

R-OE# I np ut

Input/

Output

Input

• 16-Mbit: A[19:0]

• 32-Mbit: A[20:0]

• 64-Mbit: A[21:0] A0 is the lowest-order word address. A[25:22] denote high-order addresses reserved for future device densities

DATA INPUTS/OUTPUTS: Inputs data and commands during write cycles; outputs data during read cycles. Data signals float when the device or its outputs are deselected. Data are internally latched during writes.

FLASH CLOCK: CLK synchronizes the selected flash die to the memory bus frequency in synchronous-read mode. During synchronous read operations, the initial address is latched on the rising edge of ADV#, or the rising/ falling edge of CLK when ADV# is low, whichever occurs first.

CLK is only used in synchronous-read mode. Refer to the flash discrete product datasheet for information on how to use this signal in asynchronous-read mode.

FLASH ADDRESS VALID: Low-true; During synchronous read operations, the initial address is latched on the rising edge of ADV#, or the rising/ falling edge of CLK when ADV# is low, whichever occurs first.

Refer to the flash discrete product datasheet for information on how to use this signal in asynchronous-read mode.

FLASH WAIT: When asserted, WAIT indicates invalid data from the selected flash die on D[15:0]. WAIT is High-Z whenever the flash die is deselected (CE# = V

WAIT is only used in synchronous array-read mode. Refer to the flash discrete product datasheet for information on how to use this signal in asynchronous-read mode.

FLASH CHIP ENABLE: Low-true; CE#-low selects the associated flash memory die. When asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. When deasserted, the associated flash die is deselected; power is reduced to standby levels, data and WAIT outputs are placed in High-Z.

F1-CE# selects flash die #1; F2-CE# selects flash die #2 and is RFU on combinations with only one flash die. F3-CE# selects flash die #3 and is RFU on SCSP combinations with only one or two flash die.

SRAM CHIP SELECTS: When both SRAM chip selects are asserted, SRAM internal control logic, input buffers, decoders, and sense amplifiers are active. When either/both SRAM chip selects are deasserted (S-CS1# = V standby levels.

S-CS1# and S-CS2 are only available on SCSP combinations with SRAM die.

PSRAM CHIP SELECTS: Low-true; When asserted, PSRAM internal control logic, input buffers, decoders, and sense amplifiers are active. When deasserted, the PSRAM is deselected and its power is reduced to standby levels.

P1-CS# selects PSRAM die #1 and is available only on SCSP combinations with PSRAM die. This ball is RFU on SCSP combinations without PSRAM. P2-CS# selects PSRAM die #2 and is available only on SCSP combinations with two PSRAM die. This ball is RFU on SCSP combinations without PSRAM or with a single PSRAM.

FLASH OUTPUT ENABLE: Low-true; OE#-low enables the flash output buffers. OE#-high disables the flash output buffers, and places the flash outputs in High-Z.

F1-OE# controls the outputs of flash die #1; F2-OE# controls the outputs of flash die #2 and #3, and is available only on SCSP combinations with two or three flash die and is RFU on SCSP combinations with only one flash die.

RAM OUTPUT ENABLE: Low-true; R-OE#-low enables the RAM output buffers. R-OE#-high disables the RAM output buffers, and places the RAM outputs in High-Z.

R-OE# is only available on SCSP combinations with RAM die.

and/or S-CS2 = VIL), the SRAM is deselected and its power is reduced to

). WAIT is not gated by OE#.

Datasheet November 2007 14 Order Number: 251407-13

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Numonyx Wireless Flash Memory Datasheet

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