Numonyx NAND01G-B2B, NAND02G-B2C Technical data

2112-byte/1056-word page, 1.8 V/3 V, NAND flash memory

Features

■ High density NAND flash memories

– Up to 2 Gb its of mem o ry array
– Cost effective solutions for mass storage

applications

■ NAND interface

– x8 or x16 bus width
– Multiplexed address/ data
– Pinout compatibility for all densities

■ Supply voltage: 1.8 V/3.0 V

■ Page size

– x8 device: (2048 + 64 spare) bytes
– x16 device: (1024 + 32 spare) words

■ Block size

– x8 device: (128 K + 4 K spare) bytes
– x16 device: (64 K + 2 K spare) words

■ Page read/program

– Random access: 25 µs (max)
– Sequential access: 30 ns (min)
– Page program time: 200 µs (typ)

■ Copy back program mode

■ Cache program and cache read modes

■ Fast block erase: 2 ms (typ)

■ Status register

■ Electronic signature

■ Chip enable ‘don’t care’

Table 1. Device summary

NAND01G-B2B
NAND02G-B2C

1-Gbit, 2-Gbit,

TSOP48 12 x 20 mm

FBGA

VFBGA63 9.5 x 12 x 1 mm

VFBGA63 9 x 11 x 1 mm

■ Serial number option

■ Data protection

– Hardware block locking
– Hardware program/erase locked during

power transitions

■ Data integrity

– 100 000 program/erase cycles per block

(with ECC)

– 10 years data retentio n

■ ECOPACK

■ Development tools

– Error correction code models
– Bad blocks management and wear lev e ling

algorithms

– Hardware simulation models

®

packages

Reference Part number

NAND01G-B2B

NAND02G-B2C

1. x16 organization only available for MCP products.

April 2008 Rev 5 1/60

NAND01GR3B2B, NAND01GW3B2B

NAND01GR4B2B, NAND01GW4B2B

NAND02GR3B2C, NAND02GW3B2C

NAND02GR4B2C, NAND02GW4B2C

www.numonyx.com

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Contents NAND01G-B2B, NAND02G-B2C

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1 Bad blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3 Signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.1 Inputs/outputs (I/O0-I/O7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.2 Inputs/outputs (I/O8-I/O15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.3 Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.4 Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.5 Chip Enable (E

3.6 Read Enable (R

3.7 Write Enable (W

3.8 Write Protect (WP

3.9 Ready/Busy (RB

3.10 V

3.11 V

supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

DD

ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

SS

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1 Command input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.2 Address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.3 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.4 Data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.5 Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.6 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5 Command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6 Device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.1 Read memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.1.1 Random read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.1.2 Page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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NAND01G-B2B, NAND02G-B2C Contents

6.2 Cache read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6.3 Page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.3.1 Sequential input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.3.2 Random data input in a page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.4 Copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.5 Cache program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.6 Block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.7 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.8 Read status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.8.1 Write protection bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.8.2 P/E/R controller and cache ready/busy bit (SR6) . . . . . . . . . . . . . . . . . 30

6.8.3 P/E/R controller bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.8.4 Cache program error bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.8.5 Error bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.8.6 SR4, SR3 and SR2 are reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.9 Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

7 Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8 Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.1 Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.2 NAND flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8.3 Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.4 Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.5 Error correction code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.6 Hardware simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.6.1 Behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.6.2 IBIS simulations models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

9 Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 39

10 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

11 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

11.1 Ready/Busy signal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 52

11.2 Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

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Contents NAND01G-B2B, NAND02G-B2C

12 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

13 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

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NAND01G-B2B, NAND02G-B2C List of tables

List of tables

Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Product description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 3. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 4. Valid blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 5. Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 6. Address insertion, x8 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 7. Address insertion, x16 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 8. Address definitions, x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 9. Address definitions, x16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 10. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 11. Copy back program x8 addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 12. Copy back program x16 addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 13. Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 14. Electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 15. Electronic signature byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 16. Electronic signature byte/word 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 17. NAND flash failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 18. Program, erase times and program erase endurance cycles. . . . . . . . . . . . . . . . . . . . . . . 39

Table 19. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 20. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 21. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 22. DC characteristics, 1.8 V devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 23. DC characteristics, 3 V devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 24. AC characteristics for command, address, data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 25. AC characteristics for operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 26. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanic al data . . . . . 55

Table 27. VFBGA63 9.5 x 12 mm - 6 x 8 ball array, 0.80 mm pitch, package mechanical data. . . . . 56

Table 28. VFBGA63 9 x 11 mm - 6 x 8 active ball array, 0.80 mm pitch, package mechanical data. 57

Table 29. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 30. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

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List of figures NAND01G-B2B, NAND02G-B2C

List of figures

Figure 1. Logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 2. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 3. TSOP48 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 4. VFBGA63 connections (top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 5. Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 6. Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 7. Random data output during sequential data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 8. Cache read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 9. Page program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 10. Random data input during sequential data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 11. Copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 12. Page copy back program with random data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 13. Cache program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 14. Block erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 15. Bad block management flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 16. Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 17. Error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 18. Equivalent testing circuit for AC characteristics measurement. . . . . . . . . . . . . . . . . . . . . . 42

Figure 19. Command latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 20. Address latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 21. Data Input Latch AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 22. Sequential data output after read AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 23. Read status register AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 24. Read electronic signature AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 25. Page read operation AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 26. Page program AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 27. Block erase AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 28. Reset AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 29. Program/erase enable waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 30. Program/erase disable waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 31. Ready/Busy AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 32. Ready/Busy load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 33. Resistor value versus waveform timings for Ready/Busy signal. . . . . . . . . . . . . . . . . . . . . 54

Figure 34. Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 35. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline . . . . . . . . . . . . 55

Figure 36. VFBGA63 9.5 x 12 mm - 6 x 8 active ball array, 0.80 mm pitch, package outline . . . . . . . 56

Figure 37. VFBGA63 9 x 11 mm - 6 x 8 active ball array, 0.80 mm pitch, package outline. . . . . . . . . 57

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NAND01G-B2B, NAND02G-B2C Description

1 Description

NAND01G-B2B and NAND02G-B2C flash 2112-byte/1056-word page is a family of non­volatile flash memories that uses NAND cell technology. The devices range from 1 Gbit to 2
Gbits and operate with either a 1.8 V or 3 V vo ltage supply. The size of a page is either 2112
bytes (2048 + 64 spare) or 1056 w ords (1 024 + 32 spar e) dep ending on whet her the device
has a x8 or x16 bus width.

The address lines are multiplexed with the Data Input/Output signals on a multiplexed x8 or
x16 input/output bus. This interface reduces the pin count and makes it possible to migrate
to other densities without changing the footprint.

Each block can be programmed and erased over 100 000 cycles (with ECC on). To extend
the lifetime of NAND flash devices it is strongly recommended to implement an error
correction code (ECC).

The devices feature a write protect pin that allows performing hardware protection against
program and erase operations.

The devices feature an open-drain ready/busy output that can be used to identify if the
program/erase/read (P/E/R) controller is currently active. The use of an open-drain output
allows the ready/busy pins from several memories to be connected to a single pull-up
resistor.

A Copy Back Program command is av ailable to optimize the management of defective
blocks. When a page prog r am oper ation fails, the data can be pr ogr a mmed in ano ther pag e
without having to resend the data to be programmed.

Each device has cache program and cache read features which improve t he program and
read throughputs for lar ge files. During cache programming, the device loads the data in a
cache register while the pre vious data is tr ansf erred to the page b uff er and progr ammed into
the memory array. During cache reading, the de vice loads the data in a cache register while
the previous data is transferred to the I/O buffers to be read.

All devices have the chip enable don’t care feature, which allows code to be directly
downloaded by a microcontroller, as chip enable transitions during the latency time do no t
stop the read operation.

All devices have the option of a unique identifier (serial number), which allows each device
to be uniquely identified.

The unique identifier options is subject to an NDA (non disclosure agreement) and so not
described in the datasheet. For more details of this option contact your nearest Numonyx
sales office.

The devices are available in the following packages:

● TSOP48 (12 x 20 mm)

● VFBGA63 (9.5 x 12 x 1 mm, 0.8 mm pitch) for NAND02G-B2C devices

● VFBGA63 (9 x 11 x 1 mm, 0.8 mm pitch) for NAND01G-B2B devices.

For information on how to order these options refer to Table 29: Ordering information

scheme. Devices are shipped from the factory with Block 0 always valid and the memory

content bits, in valid blocks, erased to ’1’.
See Table 2: Product description, for all the devices available in the family.

7/60

Description NAND01G-B2B, NAND02G-B2C

Table 2. Product description

Reference Part number Den s it y

NAND01G

-B2B

NAND02G

-B2C

NAND01GR3B2B

NAND01GW3B2B

NAND01GR4B2B

NAND01GW4B2B

NAND02GR3B2C

NAND02GW3B2C

NAND02GR4B2C

NAND02GW4B2C

Bus

width

x8

1Gbit

x16

x8

2Gbits

x16

1. x16 organization only available for MCP.

Page

size

2048

+64

bytes

1024

+32

words

2048

+64

bytes

1024

+32

words

Block

size

128K

+4K

bytes

64K+

2K

words

128K

+4K

bytes

64K+

2K

words

Memory

array

64

pages x

1024

blocks

64

pages x

2048

blocks

Operating

voltage

1.7 to

1.95 V

2.7 to

3.6 V

1.7 to

1.95 V

2.7 to

3.6 V

1.7 to

1.95 V

2.7 to

3.6 V

1.7 to

1.95 V

2.7 to

3.6 V

Timings

Random

access

Sequential

time

(max)

25 µs 50 ns

25 µs 30 ns TSOP48

25 µs 50 ns

25 µs 30 ns

25 µs 50 ns

25 µs 30 ns TSOP48

25 µs 50 ns

25 µs 30 ns

access

time

(min)

Page
Progra
m time

(typ)

200 µs

Bloc

k

erase

(typ)

2ms

2ms

Package

VFBGA63
9x11mm

VFBGA63

9.5 x 12 m

(1)

(1)

m

(1)

(1)

Figure 1. Logic block diagram

Address

register/counter

AL

CL

W

E

WP

R

Command

interface

logic

Command register

P/E/R controller,

high voltage

generator

RB

NAND flash

memory array

X decoder

Page buffer

Cache register

Y decoder

I/O buffers & latches

I/O0-I/O7, x8/x16

I/O8-I/O15, x16

AI12799

8/60

NAND01G-B2B, NAND02G-B2C Description

Figure 2. Logic diagram

V

DD

E

R

W

AL

CL

WP

1. x16 organization only available for MCP.

Table 3. Signal names

Signal Function Direction

I/O8-15 Data input/outputs for x16 devices I/O

I/O0-7

Data input/outputs, address inputs, or command inputs
for x8 and x16 devices

AL Address Latch Enable Input

NAND01G-B2B
NAND02G-B2C

V

SS

I/O8-I/O15, x16

I/O0-I/O7, x8/x16

RB

AI13101

I/O

CL Command Latch Enable Input

E
R

RB

W

WP
V
V

DD
SS

Chip Enable Input
Read Enable Input
Ready/Busy (open-drain output) Output
Write Enable Input
Write Protect Input
Supply voltage Supply

Ground Supply
NC Not connected internally –
DU Do not use –

9/60

Description NAND01G-B2B, NAND02G-B2C

Figure 3. TSOP48 connections

V

V

WP

NC
NC
NC
NC
NC
NC

RB

NC
NC

DD

SS

NC
NC

CL
AL

NC
NC
NC
NC
NC

1

R
E

NAND01GW3B2B

12

NAND02GW3B2C

13

W

24 25

48

37
36

NC
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
NC

NC

V

DD

V

SS

NC
NC
NC
I/O3
I/O2

I/O1
I/O0

NC
NC
NC
NC

1. Available only for NAND01GW3B2B and NAND02GW3B2C 8-bit devices.

10/60

AI13102

NAND01G-B2B, NAND02G-B2C Description

Figure 4. VFBGA63 connections (top vie w through package)

87654321

A

B

C

D

E

F

G

DU DU

DU

WP

NC

NC NC

AL

NCNC

NC

DU

DU

V

SS

R

CL

NC

NC

NCNC

NC

NC

E

W

NC

NC

NC

NCNC

RB

NCNC

NC

NC

NC

109

DU

DU

H

J

K

L

M

DU DU

DU

DU

NC

NC

V

SS

I/O0

I/O1

I/O2

NC

NC

DD

I/O4I/O3

1. Available only for NAND01GR3B2B and NAND02GR3B2C 8-bit devices.

NCNC

I/O5V

I/O6

V

DD

I/O7

V

SS

DU DU

DU

DU

AI13103

11/60

Memory array organization NAND01G-B2B, NAND02G-B2C

2 Memory array organization

The memory array is made up of NAND structures wh er e 32 cells are co nn ected in series.
The memory array is organized in blocks where each block contains 64 pages. The array is

split into two areas, the main ar ea and t he spa re area . The main are a of th e array is used to
store data whereas the spare area is typically used to store e rror correction cod es, softw are
flags or bad block identification.

In x8 devices the pages are split in to a 2048-b yte main are a and a spare area of 64 b ytes. In
the x16 devices the pages are split into a 1,024-word main area and a 32-word spare area.
Refer to Figure 5: Memory array organization.

2.1 Bad blocks

The NAND flash 2112-byte/1056-word page devices may contain bad blocks, that is blocks
that contain one or more invalid bits whose reliability is not guaranteed. Additional bad
blocks may develop during the lifetime of the device.

The bad block Information is written prior to shipping (refer to Section 8.1: Bad block

management for more details).
Table 4: Valid blocks shows the minimum number of valid blocks in each device. The values

shown include both the bad blocks that are present when the de vice is shipped and t he bad
blocks that could develop later on.

These blocks need to be managed using bad blocks management, block replacement or
error correction codes (refer to Section 8: Software algorithms).

Table 4. Valid blocks

Density of device Min Max

2 Gbits 2008 2048

1 Gbit 1004 1024

12/60

NAND01G-B2B, NAND02G-B2C Memory array organization

Figure 5. Memory array organization

x8 DEVICES x16 DEVICES

Block = 64 pages
Page = 2112 bytes (2,048 + 64)

Block = 64 pages
Page = 1056 words (1024 + 32)

Block

Page

Main area

2048 bytes

bytes

Page buffer, 2112 bytes

2,048 bytes

64

64

bytes

Spare area

8 bits

8 bits

Block

Page

Main area

1024 words

Page buffer, 1056 words

1,024 words

32

words

32

words

Spare area

16 bits

16 bits

AI09854

13/60

Signals description NAND01G-B2B, NAND02G-B2C

3 Signals description

See Figure 2: Logic diagram, and Table 3: Signal names, for a brief overview of the signals
connected to this device.

3.1 Inputs/outputs (I/O0-I/O7)

Input/outputs 0 to 7 are used to input the selected address, output the data during a read
operation or input a command or data during a write operation. The inputs are latched on
the rising edge of Write Enable. I/O0-I/O7 are left floating when the device is deselected or
the outputs are disabled.

3.2 Inputs/outputs (I/O8-I/O15)

Input/outputs 8 to 15 are only available in x16 devices. They are used to output the data
during a read operation or input data during a write operation. Comma nd and address
Inputs only require I/O0 to I/O7.

The inputs are latched on the rising edge of Write Enable. I/O8-I/O15 are left floating when
the device is deselected or the outputs are disabled.

3.3 Address Latch Enable (AL)

The Address Latch Enable activates the latching of the address inputs in the command
interface. When AL is High, the inputs are latched on the rising edge of Write Enable.

3.4 Command Latch Enable (CL)

The Command Latch Enable activates the latching of the command inputs in the command
interface. When CL is High, the inputs are latched on the rising edge of Write Enable .

3.5 Chip Enable (E)

The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is Low, V
High, v
mode.

, while the device is busy, the device remains selected and does not go into standb y

IH

3.6 Read Enable (R)

The Read Enable pin, R, controls the sequential data output during read oper atio ns. Data is
valid t
column address counter by one.

after the falling edge of R. The falling edge of R also increments the internal

RLQV

, the device is selected. If Chip Enable goes

IL

14/60

NAND01G-B2B, NAND02G-B2C Signals description

3.7 Write Enable (W)

The Write Enable input, W, controls writing to the command interface, input address and
data latches. Both addresses a nd data are latched on the rising edge of Write Enable.

During power-up and power-down a recovery time of 10 µs (min) is required before the
command interface is ready t o accept a co mmand. It is r ecommended t o k eep Write Enab le
High during the recovery time.

3.8 Write Protect (WP)

The Write Protect pin is an input that giv es a hardware protect ion against unwanted program
or erase operations. When Write Protect is Low , V
program or erase operations.

, the device does not accept any

IL

It is recommended to keep the Write Protect pin Lo w, V

3.9 Ready/Busy (RB)

The Ready/Busy output, RB, is an open- drain outp ut that can be u sed to identif y if the P/E/R
controller is currently active. When Ready/Busy is Low, V
operation is in progress. When the operation completes Ready/Busy goes High, V

The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the
memories is busy.

Refer to the Section 11.1: Ready/Busy signal electrical characteristics for details on how to
calculate the value of the pull-up resistor.

During power-up and power-down a minimum recovery time of 10 µs is required before the
command interface is ready to accept a command. During this period the RB
V

.

OL

3.10 V

supply voltage

DD

VDD provides the power supply to the internal core of the memory device. It is the main
power supply for all operations (read, program and erase).

An internal voltage detector disables all functions whenever V

Table 22 and Table 23) to protect the device from any involuntary program/erase during

power-transitions.

, during power-up and po w er-do wn.

IL

, a read, program or erase

OL

is below V

DD

signal is Low,

LKO

OH

(see

.

Each device in a system should have V
widths should be sufficient to carry the required program and erase currents.

3.11 VSS ground

Ground, V
ground.

is the reference for the power supply. It must be connected to the system

SS,

decoupled with a 0.1 µF capacitor. The PCB track

DD

15/60

Bus operations NAND01G-B2B, NAND02G-B2C

4 Bus operations

There are six standard bus operations that control the memory. Each of these is described
in this section, see Table 5: Bus operations, for a summary.

Typically, glitches of less than 5 ns on Chip Enable, Write Enable and Read Enable are
ignored by the memory and do not affect bus operations.

4.1 Command input

Command input bus operations are used to giv e comm ands to the me mory. Commands are
accepted when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable
is Low and Read Enable is High. They are latched on the rising edge of the Write Enable
signal.

Only I/O0 to I/O7 are used to input commands.
See Figure 19 and Table 24 for details of the timings requirements.

4.2 Address input

Address input bus operati ons are used to inpu t the me mory addresses. Four bus cycles are
required to input the addresses for 1-Gbit devices whereas five bus cycles are required for
the 2-Gbit device (refer to Table 6 and Table 7, Address insertion).

The addresses are accepted when Chip Enable is Low , Address Latch Enable is High,
Command Latch Enable is Low and Read Enable is High. They are latched on the rising
edge of the Write Enable signal. Only I/O0 to I/O7 are used to input add resse s.

See Figure 20 and Table 24 for details of the timings requirements.

4.3 Data input

Data input bus operations are used to input the data to be programmed.
Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command

Latch Enable is Low and Read Enable is High. The data is latched on the rising edge of the
Write Enable signal. The data is input sequentially using the Write Enab le signal.

See Figure 21 and Table 24 and Table 25 for details of the timings requirements.

4.4 Data output

Data output bus operations are used to read: the data in the memory array, the status
register, the lock status, the electronic signature and the unique identifier.

Data is output when Chip Enable is Low , Write Enable is High, Address Latch Enable is Low,
and Command Latch Enable is Low. The data is output sequentially using the Read Enable
signal.

See Figure 22 and Table 25 for details of the timings requirements.

16/60

NAND01G-B2B, NAND02G-B2C Bus operations

4.5 Write Protect

Write Protect bus operations are used to protect the memory against program or erase
operations. When the Write Protect signal is Low the device will not accept progr am or erase
operations and so the contents of the memory array cannot be altered. The Write Protect
signal is not latched by Write Enable to ensure protection even during power-up.

4.6 Standby

When Chip Enable is High the memory enters standby mode, the device is deselected,
outputs are disabled and po wer consumption is reduced.

Table 5. Bus operations

Bus operation E AL CL R W WP I/O0 - I/O7 I/O8 - I/O15

Command input V

Address input V

Data input V

Data output V

V

IL

V

IL

V

IL

V

IL

V

IL

V

IH

V

IL

V

IL

IH
IL
IL
IL

V

Rising X

IH

V

Rising X Address X

IH

V

Rising V

IH

Falling V

IH

Write Protect X X X X X V

Standby V

XXX X

IH

(2)

Command X

Data input Data input

IH

X Data output Data output

XX

XX

V

IL/VD

IL

D

1. Only for x16 devices.

2. WP must be VIH when issuing a program or erase command.

Table 6. Address insertion, x8 devices

5

1

nd

2

3
4

th(2)

(1)

I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0

st

rd
th

A7 A6 A5 A4 A3 A2 A1 A0
V

IL

V

IL

V

IL

V

IL

A11 A10 A9 A8
A19 A18 A17 A16 A15 A14 A13 A12
A27 A26 A25 A24 A23 A22 A21 A20

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

V

IL

Bus cycle

1. Any additional address input cycles will be ignored.

2. The fifth cycle is valid for 2-Gbit devices. A28 is for 2-Gbit devices only.

(1)

A28

17/60

Bus operations NAND01G-B2B, NAND02G-B2C

Table 7. Address insertion, x16 devices

Bus

cycle

1

nd

2

rd

3
4

th(2)

5

1. Any additional address input cycles will be ignored.

2. The fifth cycle is valid for 2-Gbit devices. A27 is for 2-Gbit devices only.

Table 8. Address definitions, x8

I/O8-

(1)

I/O15

st

X A7A6A5A4A3A2A1A0
X V

I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0

IL

V

IL

V

IL

V

IL

V

X A18 A17 A16 A15 A14 A13 A12 A11

th

X A26 A25 A24 A23 A22 A21 A20 A19
X V

IL

V

IL

V

IL

V

IL

V

Address Definition

A0 - A11 Column address
A12 - A17 Page address
A18 - A27 Block address 1-Gbit device
A18 - A28 Block address 2-Gbit device

Table 9. Address definitions, x16

Address Definition

IL

IL

A10 A9 A8

V

IL

V

IL

A27

A0 - A10 Column address
A11 - A16 Page address
A17 - A26 Block address 1-Gbit device
A17 - A27 Block address 2-Gbit device

18/60