Numonyx M45PE40 Technical data
4-Mbit, page-erasable serial flash memory
with byte-alterability and a 75 MHz SPI bus interface
Features
■ SPI bus compatible serial interface
■ 75 MHz clock rate (maximum)
■ 2.7 V to 3.6 V single supply voltage
■ 4-Mbit page-erasable flash memory
■ Page size: 256 bytes:
– Page write in 11 ms (typical)
– Page program in 0.8 ms (typical)
– Page erase in 10 ms (typical)
■ Sector erase (64 Kbytes)
■ Hardware write protection of the bottom sector
(64 Kbytes)
■ Electronic signature
– JEDEC standard two-byte signature
(4013h)
– Unique ID code (UID) with 16 bytes read-
only, available upon customer request only
in the T9HX process
■ Deep power-down mode 1 µA (typical)
■ More than 100 000 write cycles
■ More than 20 years data retention
■ Packages
– ECOPACK® (RoHS compliant)
M45PE40
VFQFPN8 (MP)
6 × 5 mm (MLP8)
SO8W (MW)
208 mils width
SO8N (MN)
150 mils width
May 2008 Rev 9 1/49
www.numonyx.com
1
Contents M45PE40
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Serial data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Serial data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Chip Select (S
2.5 Reset (Reset
2.6 Write Protect (W
2.7 V
2.8 V
supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CC
ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SS
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Sharing the overhead of modifying data . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 An easy way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 A fast way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4 Polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . . 13
4.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.6 Active power, standby power and deep power-down modes . . . . . . . . . . 13
4.7 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.8 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2 Write disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3 Read identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4 Read status register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.4.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/49
M45PE40 Contents
6.4.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.5 Read data bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.6 Read data bytes at higher speed (FAST_READ) . . . . . . . . . . . . . . . . . . . 23
6.7 Page write (PW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.8 Page program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.9 Page erase (PE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.10 Sector erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.11 Deep power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.12 Release from deep power-down (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7 Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
10 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
11 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
12 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3/49
List of tables M45PE40
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4. Read identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5. Status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 6. Power-up timing and VWI threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 8. Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 9. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 10. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 11. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 12. AC characteristics (25 MHz operation). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 13. AC characteristics (33 MHz operation). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 14. AC characteristics (50 MHz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 15. AC characteristics (75 MHz operation, T9HX (0.11 µm) process) . . . . . . . . . . . . . . . . . . . 40
Table 16. Reset conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 17. VFQFPN8 (MLP8) 8-lead very thin dual fl at package no lead, 6 × 5 mm,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 18. SO8 wide – 8 lead plastic small outline, 208 mils body width, package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 19. SO8N – 8 lead plastic small outline, 150 mils body width, package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 20. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 21. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4/49
M45PE40 List of figures
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. VFQFPN and SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Bus master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 6. Write enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 7. Write disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8. Read identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 20
Figure 9. Read status register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . . 21
Figure 10. Read data bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 22
Figure 11. Read data bytes at higher speed (FAST_READ) instruction sequence
and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12. Page write (PW) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 13. Page program (PP) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 14. Page erase (PE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 15. Sector erase (SE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 16. Deep power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 17. Release from deep power-down (RDP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . 31
Figure 18. Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 19. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 20. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 21. Write protect setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 22. Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 23. Reset AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 24. VFQFPN8 (MLP8) 8-lead very thin dual flat package no lead, 6 × 5 mm,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 25. SO8 wide – 8 lead plastic small outline, 208 mils body width, package outline . . . . . . . . . 45
Figure 26. SO8N – 8 lead plastic small outline, 15 0 mils body widt h, pa ckage outline . . . . . . . . . . . . 46
5/49
Description M45PE40
1 Description
The M45PE40 is a 4-Mbit (512 Kbit x8 bit) serial paged flash memory accessed by a high
speed SPI-compatible bus.
The memory can be written or programmed 1 to 256 bytes at a time , using the pa ge write or
page program instruction. The page write instruction consists of an integrated page erase
cycle followed by a page program cycle.
The memory is organized as 8 sectors, each containing 256 pages. Each page is 256 bytes
wide. Thus, the whole m emory can be viewed as consisting of 2048 pages , or 524288 b ytes .
The memory can be erased a page at a time , using the page erase instruction, or a sector at
a time, using the sector erase instruction.
Important note
This datasheet details the functionality of the M45PE40 de vices, based on the previous T7X
process or based on the current T9HX process (available since August 2007). Delivery of
parts operating with a maximum clock rate of 75 MHz starts from week 8 of 2008.
Figure 1. Logic diagram
W
Reset
V
CC
D
C
S
M45PE40
V
SS
Q
AI04040C
6/49
M45PE40 Description
Table 1. Signal names
Signal name Function Direction
C Serial Clock Input
D Serial data input Input
Q Serial data output Output
S Chip Select Input
W
Reset Input
Reset
Write Protect Input
V
CC
V
SS
Supply voltage
Ground
Figure 2. VFQFPN and SO connections
M45PE40
DQ
1
C
2
Reset
3
4
1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally, to
VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB.
2. See Section11: Package mechanical for package dimensions, and how to identify pin-1.
AI04041D
8
V
7
SS
V
6
CC
WS
5
7/49
Signal descriptions M45PE40
2 Signal descriptions
2.1 Serial data output (Q)
This output signal is used to transf er data serially out of the de vice . Data is shifted out on the
falling edge of Serial Clock (C).
2.2 Serial data input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be programmed. Values are latched on the rising edge of Serial
Clock (C).
2.3 Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at serial data input (D) are latched on the rising edge of Serial Cloc k (C). Data on
serial data output (Q) changes after the falling edge of Serial Clock (C).
2.4 Chip Select (S)
When this input signal is High, the device is deselect ed and se rial data output (Q) is at high
impedance. Unless an internal read, program, er ase or write cycle is in prog ress , the device
will be in the standby power mode (this is not the deep power-down mode). Driving Chip
Select (S
After power-up, a falling edge on Chip Select (S
instruction.
) Low selects the device, placing it in the active power mode.
2.5 Reset (Reset)
The Reset (Reset) input provides a hardw are reset f or the memory. In this mode , the outputs
are high impedance.
When Reset (Reset
Reset (Reset
operation is currently in prog ress. Driving Reset (Reset
progress has no effect on that internal operation (a write cycle, program cycle, or erase
cycle).
) is driven High, the memory is in the normal operating mode. When
) is driven Low , the memory will enter the reset mode, pro vided that no internal
2.6 Write Protect (W)
This input signal puts the device in the har dw are protect ed mode , when Write Protect (W ) is
connected to V
them from write, program and erase operations. When Write Protect (W
V
, the first 256 pages of memor y be h ave like the other pages of memory.
CC
, causing the first 256 pages of memory to become read- only by pr otecting
SS
) is required prior to the start of any
) Low while an internal operation is in
) is connected to
8/49
M45PE40 Signal descriptions
2.7 VCC supply voltage
VCC is the supply voltage.
2.8 VSS ground
VSS is the reference for the VCC supply voltage.
9/49
SPI modes M45PE40
3 SPI modes
These devices can be drive n by a microcontroller with its SPI peripheral running in either of
the two following modes:
● CPOL=0, CPHA=0
● CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 4, is the clock polarity when the
bus master is in standby mode and not transferring data:
● C remains at 0 for (CPOL=0, CPHA=0)
● C remains at 1 for (CPOL=1, CPHA=1)
Figure 3. Bus master and memory devices on the SPI bus
V
SS
V
CC
R
SPI interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SPI bus master
CS3 CS2 CS1
1. The Write Protect (W) signal should be driven, High or Low as appropriate.
SDO
SDI
SCK
device
W
V
CC
Reset
CQD
V
SS
SPI memory
S
CQD
RR R
SPI memory
S
device
V
CC
W
Reset
V
CQD
SS
S
V
SPI memory
device
W
CC
Reset
AI12836c
V
SS
Figure 3 shows an e xample of three de vices conn ected to an MCU , on an SPI b us. Only one
device is selected at a time, so only one device drives the serial data output (Q) line at a
time, the other devices are high impedance. Resistors R (represente d in Figure 3) ensure
that the M45PE40 is not selected if the bus master leaves the S
line in the high impedance
state. As the bus master ma y enter a state where all inpu ts/outputs are in high impedance at
the same time (for example, when the bus mast er is reset), the clock line (C) must be
connected to an external pull-down resistor so that, when all inputs/outputs become high
impedance, the S
C do not become High at the same time, and so, that the t
typical value of R is 100 kΩ, assuming that the time constant R*C
line is pulled High while the C line is pulled Low (thus ensuring that S a nd
requirement is met). The
SHCH
(Cp = parasitic
p
capacitance of the bus line) is shorter than the time during which the bus master leaves the
SPI bus in high impedance.
10/49
M45PE40 SPI modes
Example: Cp = 50 pF, that is R*Cp = 5 µs <=> the application must ensure that the bus
master never leaves the SPI bus in the high impedance state for a time period shorter than
5µs.
Figure 4. SPI modes supported
CPHA
CPOL
C
0
0
1
1
C
D
Q
MSB
MSB
AI01438B
11/49
Operating features M45PE40
4 Operating features
4.1 Sharing the overhead of modifying data
To write or program one (or more) data bytes, two instructions are required: write enable
(WREN), which is one byte, and a page write (PW) or page program (PP) sequence, which
consists of four byte s plus data. This is followed by the int ernal cycle (of duration t
To share this overhead, the page write (PW) or page program (PP) instruction allows up to
256 bytes to be prog rammed (chan ging bits from 1 to 0) or written (changing bit s to 0 or 1) at
a time, provided that they lie in consecutive addresses on the same page of memory.
4.2 An easy way to modify data
The page write (PW) instruction provides a convenient way of modifying data (up to 256
contiguous bytes at a time), and simply requires the start address, and the new data in the
instruction sequence.
PW
or tPP).
The page write (PW) instruction is entered by driving Chip Select (S
transmitting the instruction byte, three address bytes (A23-A0) and at least one data b yte,
and then driving Chip Select (S
bytes are written to the data buffer, starting at the address given in the third address byte
(A7-A0). When Chip Select (S
unchanged, bytes of the data buffer are automatically loaded with th e values of the
corresponding bytes of the addressed memory page. The addressed memory page then
automatically put into an erase cycle. Finally, the addressed memory page is programmed
with the contents of the data buffer.
All of this buffer management is handled internally, and is transparent to the user. The user
is given the facility of being able to alter the contents of the memory on a byte-by-b yte basis .
For optimized timings, it is recommended to use the page write (PW) instruction to write all
consecutive targeted bytes in a single sequence versus using several page write (PW)
sequences with each containing only a few bytes (see Section 6.7: Page write (PW),
Table 14: AC characteristics (50 MHz operation), and Table 15: AC characteristics (75 MHz
operation, T9HX (0.11 µm) process)).
) High. While Chip Select (S) is being held Low, the data
) is driven High, the write cycle starts. The remaining,
) Low, and then
12/49
M45PE40 Operating features
4.3 A fast way to modify data
The page program (PP) instruction provides a fast way of modifying data (up to 256
contiguous bytes at a time), provided that it only involves resetting bits to ‘0’ that had
previously been set to ‘1’.
This might be:
● when the designer is programming the device for the first time
● when the designer knows that the page has already been erased by an earlier page
erase (PE) or sector erase (SE) instruction. This is useful, for example, when storing a
fast stream of data, having first performed the erase cycle when time was available
● when the designer knows that the only changes in volve resetting bits to ‘0’ that are still
set to ‘1’. When this method is possible, it has the additional advantage of minimizing
the number of unnecessary erase operations, and the extra stress incurred by each
page.
For optimized timings, it is recommended to use the page program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several page
program (PP) sequences with each containing only a few bytes (see Section 6.8: Page
program (PP), Table 14: AC characteristics (50 MHz operation), and Table 15: AC
characteristics (75 MHz operation, T9HX (0.11 µm) process)).
4.4 Polling during a write, program or erase cycle
A further improvement in the write, progra m or erase time can be achie v ed by not w aiting f or
the worst case delay (t
status register so that the application program can monitor its value, polling it to establish
when the previous cycle is complete.
, tPP, tPE, or tSE). The write in progress (WIP) bit is provided in the
PW
4.5 Reset
An internal power on reset circuit helps protect against inadvertent data writes. Addition
protection is provided by driving Reset (Reset
driving it High when V
has reached the correct voltage level, VCC(min).
CC
) Low during the power-on process, and only
4.6 Active power, standby power and deep power-down modes
When Chip Select (S) is Low, the device is selected, and in the active power mode.
When Chip Select (S
mode until all internal cycles have completed (program, erase, write). The device then goes
in to the standby power mode. The device consumption drops to I
The deep power-do wn mo de is en tere d when th e specific in struction (the de ep power-down
(DP) instruction) is executed. The device consumption drops further to I
remains in this mode until another specific instruction (the release from deep power-down
and read electronic signature (RES) instruction) is executed.
) is High, the device is dese lected, b ut could rema in in the activ e pow er
.
CC1
. The device
CC2
All other instructions are ignored while the de vice is in the deep pow er-down mo de. This can
be used as an extra softw are protection mech anism, when the device is not in active use, to
protect the device from inadvertent write, program or erase instructions.
13/49
Operating features M45PE40
4.7 Status register
The status register contains two status bits that can be read by the read status register
(RDSR) instruction. See Section 6.4: Read status register (RDSR) for a detailed description
of the status register bits.
4.8 Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M45PE40 features the following data protection mechanisms:
● Power on reset and an internal timer (t
changes while the power supply is outside the operating specification
● Program, erase and write instructions are checked that they consist of a number of
clock pulses that is a multiple of eight, before they are accepted for execution
● All instructions that modify data must be preceded by a write enable (WREN)
instruction to set the write enable latch (WEL) bit. This bit is returned to its reset state
by the following events:
–Power-up
– Reset (R
eset) driven Low
– Write disable (WRDI) instruction completion
– Page write (PW) instruction completion
– Page program (PP) instruction completion
– Page erase (PE) instruction completion
– Sector erase (SE) instruction completion
● The hardware protected mode is entered when Write Protect (W) is driven Low,
causing the first 256 pages of memory to become read-only. When write protect (W
driven High, the first 256 pages of memory behave like the other pages of memory
● The Reset (Reset) signal can be driven Low to protect the contents of the memory
during any critical time, not just during power-up and power-down
● In addition to the low power consumption feature, the deep power-down mod e offers
extra software protection from inadvertent write, program and erase instructions while
the device is not in active use.
) can provide protection against inadvertent
PUW
) is
14/49
M45PE40 Memory organization
5 Memory organization
The memory is organized as:
● 2048 pages (256 bytes each)
● 524288 bytes (8 bits each)
● 8 sectors (512 Kbits, 65536 bytes each).
Each page can be individually:
● programmed (bits are programmed from 1 to 0)
● erased (bits are erased from 0 to 1)
● written (bits are changed to either 0 or 1)
The device is page or sector erasa ble (bits are erased from 0 to 1).
Table 2. Memory organization
Sector Address range
7 70000h 7FFFFh
6 60000h 6FFFFh
5 50000h 5FFFFh
4 40000h 4FFFFh
3 30000h 3FFFFh
2 20000h 2FFFFh
1 10000h 1FFFFh
0 00000h 0FFFFh
15/49
Loading...