Numonyx M36L0T7050T2, M36L0T7050B2 Technical data

查询M36L0T7050B2供应商

128 Mbit (Multiple Bank, Multi-Level, Burst) Flash memory

and 32 Mbit (2Mb x16) PSRAM, Multi-Chip Package

Feature summary

■ Multi-Chip Package

– 1 die of 128 Mbit (8Mb x16, Multiple Bank,

Multi-level, Burst) Flash Memory

– 1 die of 32 Mbit (2Mb x16) Pseudo SRAM

■ Supply voltage

–V
–V
–V

■ Electronic signature

– Manufacturer Code: 20h
– Device Code (Top Flash Configuration)

– Device Code (Bottom Flash Configuration)

■ ECOPACK® packages available

Flash memory

■ Synchronous / Asynchronous Read

– Synchronous Burst Read mode: 52MHz
– Random Access: 85ns

■ Synchronous Burst Read Suspend

■ Programming time

– 2.5µs typical Word program time using

■ Memory organization

– Multiple Bank Memory Array: 8 Mbit Banks
– Parameter Blocks (Top or Bottom location)

■ Dual operations

– program/erase in one Bank while read in

– No delay between read and write

= 1.7 to 1.95V

DDF

= V

CCP

= 9V for fast program

PPF

= 2.7 to 3.1V

DDQ

M36L0T7050T2: 88C4h

M36L0T7050B2: 88C5h

Buffer Enhanced Factory Program
command

others

operations

M36L0T7050T2

M36L0T7050B2

Preliminary Data

FBGA

TFBGA88 (ZAQ)

8 x 10mm

■ Block locking

– All blocks locked at power-up
– Any combination of blocks can be locked

with zero latency
–WP
– Absolute Write Protection with V

■

Security
– 64 bit unique device number
– 2112 bit user programmable OTP Cells

■ Common Flash Interface (CFI)

■ 100,000 program/erase cycles per block

PSRAM

■ Access time: 65ns

■ 8-Word Page Access capability: 18ns

■ Low standby current: 100µA

■ Deep power down current: 10µA

■ Compatible with standard LPSRAM

■ Power-down modes

– Deep Power-Down
– 4 Mbit Partial Array Refresh
– 8 Mbit Partial Array Refresh

for Block Lock-Down

PP

= V

SS

November 2007 Rev 0.2 1/22

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.

www.numonyx.com

1

Contents M36L0T7050T2, M36L0T7050B2

Contents

1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1 Address Inputs (A0-A22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2 Data Input/Output (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3 Flash Chip Enable (E

2.4 Flash Output Enable (G

2.5 Flash Write Enable (W

2.6 Flash Write Protect (WP

2.7 Flash Reset (RP

2.8 Flash Latch Enable (L

2.9 Flash Clock (K

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

F

2.10 Flash Wait (WAIT

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

F

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

F

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

F

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

F

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

F

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

F

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

F

2.11 PSRAM Chip Enable Input (E1

2.12 PSRAM Chip Enable Input (E2

2.13 PSRAM Write Enable (W

2.14 PSRAM Output Enable (G

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

P

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

P

2.15 PSRAM Upper Byte Enable (UB

2.16 PSRAM Lower Byte Enable (LB

2.17 V

2.18 V

2.19 V

2.20 V

2.21 V

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

DDF

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

CCP

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

DDQ

Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

PPF

Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

SS

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

P

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

P

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

P

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

P

3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2/22

M36L0T7050T2, M36L0T7050B2 Contents

7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3/22

List of tables M36L0T7050T2, M36L0T7050B2

List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 4. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 5. Device Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 6. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Data . . . . . . 19

Table 7. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4/22

M36L0T7050T2, M36L0T7050B2 List of figures

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3. Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 4. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 5. AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 6. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch,

Bottom View Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5/22

Summary description M36L0T7050T2, M36L0T7050B2

1 Summary description

The M36L0T7050T2 and M36L0T7050B2 combine two memory devices in a Multi-Chip
Package:

● a 128-Mbit, Multiple Bank, Multi-Level, Burst, Flash memory, the M58LT128HT or

M58LT128HB

● a 32-Mbit PseudoSRAM, the M69KW048BD.

The purpose of this document is to describe how the two memory components operate with
respect to each other. It should be read in conjunction with the M58LT128HTB and

M69KW048BD datasheets, where all specifications required to operate the Flash memory

and PSRAM components are fully detailed. These datasheets are available from your local
Numonyx distributor.

Recommended operating conditions do not allow more than one memory to be active at the
same time.

The memory is offered in a Stacked TFBGA88 (8 x 10mm, 8x10 ball array, 0.8mm pitch)
package. The devices are supplied with all the bits erased (set to ‘1’).

Figure 1. Logic diagram

A0-A22

E

G

W

RP

WP

L

K

E1

G

W

E2

UB

LB

V

DDQ

V

DDF

23

F

F

F

F

F

F

F

P

P

P

P

P

P

M36L0T7050T2

M36L0T7050B2

V

PPF

V

CCP

16

DQ0-DQ15

WAIT

F

6/22

V

SS

AI12878

M36L0T7050T2, M36L0T7050B2 Summary description

Table 1. Signal names

(1)

A0-A22

DQ0-DQ15 Common Data Input/Output

V

DDF

V

DDQ

V

PPF

V

SS

V

CCP

NC Not Connected Internally

DU Do Not Use as Internally Connected

Flash memory signals

L

F

E

F

G

F

W

F

RP

F

WP

F

Burst Clock

K

F

WAIT

F

PSRAM signals

E1

P

G

P

W

P

E2

P

UB

P

LB

P

1. A22-A21 are not connected to the PSRAM component.

Address Inputs

Power Supply for Flash Memory

Flash Memory Power Supply for I/O Buffers

Flash Optional Supply Voltage for Fast Program and Erase

Ground

PSRAM Power Supply

Latch Enable Input

Chip Enable Input

Output Enable Input

Write Enable Input

Reset Input

Write Protect Input

Wait Data in Burst Mode

Chip Enable Input

Output Enable Input

Write Enable Input

Power-down Input

Upper Byte Enable Input

Lower Byte Enable Input

7/22