Numonyx M29W640FT, M29W640FB Technical data
M29W640FT
M29W640FB
64 Mbit (8Mb x8 or 4Mb x16, Page, Boot Block)
3V Supply Flash Memory
Feature summary
■ Supply voltage
–V
–V
■ Asynchronous Random/Page Read
– Page Width: 4 Words
– Page Access: 25ns
– Random Access: 60ns, 70ns
■ Programming time
– 10µs per Byte/Word typical
– 4 Words / 8 Bytes Program
■ 135 Memory Blocks
– 1 Boot Block and 7 Parameter Blocks,
– 127 Main Blocks, 64 KBytes each
■ Program/Erase Controller
– Embedded Byte/Word Program algorithms
■ Program/Erase Suspend and Resume
– Read from any Block during Program
– Read and Program another Block during
■ Unlock Bypass Program command
– Faster Production/Batch Programming
■ V
PP
■ Temporary Block Unprotection mode
■ Common Flash Interface
– 64-bit Security Code
2.7V to 3.6V for Program, Erase,
CC =
Read
=12 V for Fast Program (optional)
PP
8 KBytes each (Top or Bottom location)
Suspend
Erase Suspend
/WP pin for Fast Program and Write Protect
TSOP48 (N)
12 x 20mm
FBGA
TFBGA48 (ZA)
6x8mm
■ Extended Memory Block
■ Extra block used as security block or to store
additional information
■ Low power consumption
– Standby and Automatic Standby
■ 100,000 Program/Erase cycles per block
■ Electronic Signature
– Manufacturer Code: 0020h
■ ECOPACK
®
packages
Table 1. Device Codes
Root Part Number Device Code
M29W640FT 22EDh
M29W640FB 22FDh
December 2007 Rev 7 1/71
www.numonyx.com
1
Contents M29W640FT, M29W640FB
Contents
1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 Address Inputs (A0-A21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Data Inputs/Outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 Data Inputs/Outputs (DQ8-DQ14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 Data Input/Output or Address Input (DQ15A–1) . . . . . . . . . . . . . . . . . . . 11
2.5 Chip Enable (E
2.6 Output Enable (G
2.7 Write Enable (W
2.8 V
/Write Protect (V
PP
2.9 Reset/Block Temporary Unprotect (RP
2.10 Ready/Busy Output (RB
2.11 Byte/Word Organization Select (BYTE
2.12 V
2.13 V
Supply Voltage (2.7V to 3.6V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
CC
Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SS
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PP/
) . . . . . . . . . . . . . . . . . . . . . . . . . . 13
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
) . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5 Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6 Special Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6.1 Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6.2 Block Protect and Chip Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 Standard commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1.1 Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1.2 Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1.3 Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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M29W640FT, M29W640FB Contents
4.1.4 Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1.5 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1.6 Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1.7 Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1.8 Program Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1.9 Program Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1.10 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2 Fast Program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.2.1 Double Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.2.2 Quadruple Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.2.3 Octuple Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2.4 Double Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2.5 Quadruple Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.2.6 Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.2.7 Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.2.8 Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.3 Block Protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.3.1 Enter Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.3.2 Exit Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.3.3 Block Protect and Chip Unprotect commands . . . . . . . . . . . . . . . . . . . . 26
5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.1 Data Polling Bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.2 Toggle Bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3 Error Bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.4 Erase Timer Bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.5 Alternative Toggle Bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Appendix A Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3/71
Contents M29W640FT, M29W640FB
Appendix B Common Flash Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Appendix C Extended Memory Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
C.1 Factory Locked Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
C.2 Customer Lockable Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Appendix D Block protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
D.1 Programmer technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
D.2 In-System technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4/71
M29W640FT, M29W640FB List of tables
List of tables
Table 1. Device Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Hardware protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. Bus operations, BYTE
Table 5. Bus operations, BYTE
Table 6. Commands, 16-bit mode, BYTE
Table 7. Commands, 8-bit mode, BYTE = V
Table 8. Program, Erase times and Program, Erase Endurance cycles. . . . . . . . . . . . . . . . . . . . . . 29
Table 9. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 10. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 11. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 12. Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 13. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 14. Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 15. Write AC characteristics, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 16. Write AC characteristics, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 17. Reset/Block Temporary Unprotect AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 18. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, package mechanical data . . . 44
Table 19. TFBGA48 6x8mm - 6x8 active ball array, 0.8mm pitch, package mechanical data . . . . . . 45
Table 20. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 21. Top Boot Block addresses, M29W640FT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 22. Bottom Boot Block addresses, M29W640FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 23. Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 24. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 25. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 26. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 27. Primary Algorithm-specific Extended Query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 28. Security Code Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 29. Extended Block address and data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 30. Programmer technique bus operations, BYTE
Table 31. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
= VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
= VIH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
= V
IH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
IL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
= VIH or V
IL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
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List of figures M29W640FT, M29W640FB
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2. TSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3. TFBGA48 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. Data Polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 5. Data Toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 6. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 7. AC measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 8. Read Mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 9. Page Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 10. Write AC waveforms, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 11. Write AC waveforms, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 12. Reset/Block Temporary Unprotect AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 13. Accelerated Program Timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 14. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, top view package outline . . . . 44
Figure 15. TFBGA48 6x8mm - 6x8 active ball array, 0.8mm pitch, package outline . . . . . . . . . . . . . . 45
Figure 16. Programmer Equipment Group Protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 17. Programmer Equipment Chip Unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 18. In-System Equipment Group Protect flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 19. In-System Equipment Chip Unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
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M29W640FT, M29W640FB Summary description
1 Summary description
The M29W640F is a 64 Mbit (8Mb x8 or 4Mb x16) non-volatile memory that can be read,
erased and reprogrammed. These operations can be performed using a single low voltage
(2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode.
The memory is divided into blocks that can be erased independently so it is possible to
preserve valid data while old data is erased. Blocks can be protected in units of 256 KByte
(generally groups of four 64 KByte blocks), to prevent accidental Program or Erase
commands from modifying the memory. Program and Erase commands are written to the
Command Interface of the memory. An on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by taking care of all of the special
operations that are required to update the memory contents. The end of a program or erase
operation can be detected and any error conditions identified. The command set required to
control the memory is consistent with JEDEC standards.
The device features an asymmetrical blocked architecture. The device has an array of 135
blocks:
● 8 Parameters Blocks of 8 KBytes each (or 4 KWords each)
● 127 Main Blocks of 64 KBytes each (or 32 KWords each)
M29W640FT has the Parameter Blocks at the top of the memory address space while the
M29W640FB locates the Parameter Blocks starting from the bottom.
The M29W640F has an extra block, the Extended Block, of 128 Words in x16 mode or of
256 Byte in x8 mode that can be accessed using a dedicated command. The Extended
Block can be protected and so is useful for storing security information. However the
protection is not reversible, once protected the protection cannot be undone.
Chip Enable, Output Enable and Write Enable signals control the bus operation of the
memory. They allow simple connection to most microprocessors, often without additional
logic.
The V
word/byte programming. If this signal is held at V
/WP signal is used to enable faster programming of the device, enabling multiple
PP
, the boot block, and its adjacent
SS
parameter block, are protected from program and erase operations.
The device supports Asynchronous Random Read and Page Read from all blocks of the
memory array.
The memories are offered in TSOP48 (12x 20mm) and TFBGA48 (6x8mm, 0.8mm pitch)
packages.
In order to meet environmental requirements, ST offers the M29W640FT and the
M29W640FB in ECOPACK
®
packages. ECOPACK packages are Lead-free. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
The memory is delivered with all the bits erased (set to 1).
7/71
Summary description M29W640FT, M29W640FB
Figure 1. Logic diagram
VPP/WP
V
CC
A0-A21
W
22
E
M29W640FT
M29W640FB
G
15
DQ0-DQ14
DQ15A–1
BYTE
RB
RP
V
SS
AI11250
Table 2. Signal names
A0-A21 Address Inputs
DQ0-DQ7 Data Inputs/Outputs
DQ8-DQ14 Data Inputs/Outputs
DQ15A–1 (or DQ15) Data Input/Output or Address Input (or Data Input/Output)
E Chip Enable
G
W
RP
RB
BYTE
V
CC
/WP Supply voltage for Fast Program (optional) or Write Protect
V
PP
V
SS
Output Enable
Write Enable
Reset/Block Temporary Unprotect
Ready/Busy Output
Byte/Word Organization Select
Supply voltage
Ground
NC Not Connected Internally
8/71
M29W640FT, M29W640FB Summary description
Figure 2. TSOP connections
A15
1
48
A14
A13
A12
A11
A10 DQ14
A9
A8
A19
A20
M29W640FT
M29W640FB
W
RP
A21
12
13
37
36
VPP/WP
RB
A18
A17
A7
A6
A5
A4
A3
A2
24 25
A1
A16
BYTE
V
SS
DQ15A–1
DQ7
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
V
SS
E
A0
AI11251
9/71
Summary description M29W640FT, M29W640FB
Figure 3. TFBGA48 connections (top view through package)
654321
A
B
C
D
E
F
G
H
A3
A4
A2
A1
A0
E
G
V
SS
A7
A17
A6
A5 A20
DQ0
DQ8
DQ9
DQ1
RB
V
PP
A18
DQ2
DQ10
DQ11
DQ3
/
WP
W
RP
A21
A19
DQ5
DQ12
V
CC
DQ4
A9
A8
A10
A11
DQ7
DQ14
DQ13
DQ6
A13
A12
A14
A15
A16
BYTE
DQ15
A–1
V
SS
10/71
AI11554
M29W640FT, M29W640FB Signal descriptions
2 Signal descriptions
See Figure 1: Logic diagram, and Table 2: Signal names, for a brief overview of the signals
connected to this device.
2.1 Address Inputs (A0-A21)
The Address Inputs select the cells in the memory array to access during Bus Read
operations. During Bus Write operations they control the commands sent to the Command
Interface of the Program/Erase Controller.
2.2 Data Inputs/Outputs (DQ0-DQ7)
The Data I/O outputs the data stored at the selected address during a Bus Read operation.
During Bus Write operations they represent the commands sent to the Command Interface
of the Program/Erase Controller.
2.3 Data Inputs/Outputs (DQ8-DQ14)
The Data I/O outputs the data stored at the selected address during a Bus Read operation
when BYTE
impedance. During Bus Write operations the Command Register does not use these bits.
When reading the Status Register these bits should be ignored.
is High, VIH. When BYTE is Low, VIL, these pins are not used and are high
2.4 Data Input/Output or Address Input (DQ15A–1)
When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14).
When BYTE
LSB of the addressed Word, DQ15A–1 High will select the MSB. Throughout the text
consider references to the Data Input/Output to include this pin when BYTE
references to the Address Inputs to include this pin when BYTE
explicitly otherwise.
is Low, VIL, this pin behaves as an address pin; DQ15A–1 Low will select the
is Low except when stated
2.5 Chip Enable (E)
The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to
be performed. When Chip Enable is High, V
, all other pins are ignored.
IH
2.6 Output Enable (G)
The Output Enable, G, controls the Bus Read operation of the memory.
is High and
11/71
Signal descriptions M29W640FT, M29W640FB
2.7 Write Enable (W)
The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface.
2.8 VPP/Write Protect (VPP/WP)
The VPP/Write Protect pin provides two functions. The VPP function allows the memory to
use an external high voltage power supply to reduce the time required for Unlock Bypass
Program operations. The Write Protect function provides a hardware method of protecting
the two outermost boot blocks. The V
unconnected.
/Write Protect pin must not be left floating or
PP
When V
Program and Erase operations in this block are ignored while V
when RP
When V
/Write Protect is Low, VIL, the memory protects the two outermost boot blocks;
PP
/Write Protect is Low, even
PP
is at VID.
/Write Protect is High, VIH, the memory reverts to the previous protection status
PP
of the two outermost boot blocks. Program and Erase operations can now modify the data in
the two outermost boot blocks unless the block is protected using Block Protection.
Applying V
to the VPP/WP pin will temporarily unprotect any block previously protected
PPH
(including the two outermost parameter blocks) using a High Voltage Block Protection
technique (In-System or Programmer technique). See Table 3: Hardware protection for
details.
When V
Bypass mode. When V
During Unlock Bypass Program operations the memory draws I
/Write Protect is raised to V
PP
/Write Protect returns to VIH or VIL normal operation resumes.
PP
the memory automatically enters the Unlock
PP
from the pin to supply the
PP
programming circuits. See the description of the Unlock Bypass command in the Command
Interface section. The transitions from V
t
, see Figure 13: Accelerated Program Timing waveforms.
VHVPP
Never raise V
/Write Protect to VPP from any mode except Read mode, otherwise the
PP
to VPP and from VPP to VIH must be slower than
IH
memory may be left in an indeterminate state.
A 0.1µF capacitor should be connected between the V
/Write Protect pin and the VSS
PP
Ground pin to decouple the current surges from the power supply. The PCB track widths
must be sufficient to carry the currents required during Unlock Bypass Program, I
Table 3. Hardware protection
PP
.
VPP/WP RP Function
V
V
IL
or V
V
IH
ID
V
PPH
12/71
IH
V
ID
V
ID
VIH or V
2 outermost parameter blocks protected from Program/Erase operations
All blocks temporarily unprotected except the 2 outermost blocks
All blocks temporarily unprotected
All blocks temporarily unprotected
ID
M29W640FT, M29W640FB Signal descriptions
2.9 Reset/Block Temporary Unprotect (RP)
The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the
memory or to temporarily unprotect all Blocks that have been protected.
Note that if V
if RP is at V
/WP is at VIL, then the two outermost boot blocks will remain protected even
PP
.
ID
A Hardware Reset is achieved by holding Reset/Block Temporary Unprotect Low, V
least t
. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be
PLPX
ready for Bus Read and Bus Write operations after t
See the Ready/Busy Output section, Table 17: Reset/Block Temporary Unprotect AC
characteristics and Figure 12: Reset/Block Temporary Unprotect AC waveforms, for more
details.
Holding RP
at VID will temporarily unprotect the protected Blocks in the memory. Program
and Erase operations on all blocks will be possible. The transition from V
slower than t
PHPHH
.
2.10 Ready/Busy Output (RB)
The Ready/Busy pin is an open-drain output that can be used to identify when the device is
performing a Program or Erase operation. During Program or Erase operations Ready/Busy
is Low, V
Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy
becomes high-impedance. See Table 17: Reset/Block Temporary Unprotect AC
characteristics and Figure 12: Reset/Block Temporary Unprotect AC waveforms, for more
details.
. Ready/Busy is high-impedance during Read mode, Auto Select mode and
OL
PHEL
or t
, whichever occurs last.
RHEL
to VID must be
IH
, for at
IL
The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the
memories is busy.
2.11 Byte/Word Organization Select (BYTE)
The Byte/Word Organization Select pin is used to switch between the x8 and x16 Bus
modes of the memory. When Byte/Word Organization Select is Low, V
x8 mode, when it is High, V
, the memory is in x16 mode.
IH
, the memory is in
IL
13/71
Signal descriptions M29W640FT, M29W640FB
2.12 VCC Supply Voltage (2.7V to 3.6V)
VCC provides the power supply for all operations (Read, Program and Erase).
The Command Interface is disabled when the V
Voltage, V
. This prevents Bus Write operations from accidentally damaging the data
LKO
during power up, power down and power surges. If the Program/Erase Controller is
programming or erasing during this time then the operation aborts and the memory contents
being altered will be invalid.
A 0.1µF capacitor should be connected between the V
Ground pin to decouple the current surges from the power supply. The PCB track widths
must be sufficient to carry the currents required during Program and Erase operations, I
2.13 VSS Ground
VSS is the reference for all voltage measurements. The device features two VSS pins which
must be both connected to the system ground.
Supply voltage is less than the Lockout
CC
Supply voltage pin and the VSS
CC
CC3
.
14/71
M29W640FT, M29W640FB Bus operations
3 Bus operations
There are five standard bus operations that control the device. These are Bus Read, Bus
Write, Output Disable, Standby and Automatic Standby. See Table 4: Bus operations, BYTE
= V
and Table 5: Bus operations, BYTE = VIH, for a summary. Typically glitches of less than
IL
5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus
operations.
3.1 Bus Read
Bus Read operations read from the memory cells, or specific registers in the Command
Interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs, applying a Low signal, V
Enable High, V
AC waveforms, and Table 14: Read AC characteristics, for details of when the output
becomes valid.
3.2 Bus Write
. The Data Inputs/Outputs will output the value, see Figure 8: Read Mode
IH
, to Chip Enable and Output Enable and keeping Write
IL
Bus Write operations write to the Command Interface. To speed up the read operation the
memory array can be read in Page mode where data is internally read and stored in a page
buffer. The Page has a size of 4 Words and is addressed by the address inputs A0-A1.
A valid Bus Write operation begins by setting the desired address on the Address Inputs.
The Address Inputs are latched by the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the
Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs
first. Output Enable must remain High, V
Figure 10: Write AC waveforms, Write Enable controlled, Figure 11: Write AC waveforms,
Chip Enable controlled, and Table 15: Write AC characteristics, Write Enable controlled and
Table 16: Write AC characteristics, Chip Enable controlled, for details of the timing
requirements.
3.3 Output Disable
The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH.
3.4 Standby
When Chip Enable is High, VIH, the memory enters Standby mode and the Data
Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to
the Standby Supply Current, I
Standby current level see Table 13: DC characteristics.
, during the whole Bus Write operation. See
IH
, Chip Enable should be held within V
CC2
± 0.2V. For the
CC
During program or erase operations the memory will continue to use the Program/Erase
Supply Current, I
, for Program or Erase operations until the operation completes.
CC3
15/71
Bus operations M29W640FT, M29W640FB
3.5 Automatic Standby
If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 300ns or
more the memory enters Automatic Standby where the internal Supply Current is reduced to
the Standby Supply Current, I
. The Data Inputs/Outputs will still output data if a Bus
CC2
Read operation is in progress.
3.6 Special Bus operations
Additional bus operations can be performed to read the Electronic Signature and also to
apply and remove Block Protection. These bus operations are intended for use by
programming equipment and are not usually used in applications. They require V
applied to some pins.
3.6.1 Electronic Signature
The memory has two codes, the manufacturer code and the device code, that can be read
to identify the memory. These codes can be read by applying the signals listed in Ta bl e 4 :
Bus operations, BYTE = V
and Table 5: Bus operations, BYTE = VIH.
IL
3.6.2 Block Protect and Chip Unprotect
to be
ID
Groups of blocks can be protected against accidental Program or Erase. The Protection
Groups are shown in Appendix A: Block addresses Tab le 2 1 and Ta bl e 2 2 . The whole chip
can be unprotected to allow the data inside the blocks to be changed.
The V
V
PP
/Write Protect pin can be used to protect the two outermost boot blocks. When
PP
/Write Protect is at V
the two outermost boot blocks are protected and remain
IL
protected regardless of the Block Protection Status or the Reset/Block Temporary
Unprotect pin status.
Block Protect and Chip Unprotect operations are described in Appendix D: Block protection.
16/71
M29W640FT, M29W640FB Bus operations
Table 4. Bus operations, BYTE = VIL
Operation E G W
Bus Read V
Bus Write V
Output Disable X V
Standby V
ILVILVIH
ILVIHVIL
IHVIH
X X X Hi-Z Hi-Z
IH
Read Manufacturer Code VILVILV
Cell address Hi-Z Data Output
Command address Hi-Z Data Input
X Hi-Z Hi-Z
A0-A3 = VIL, A6 = VIL,
IH
A9 = VID, Others VIL or V
A0 = VIH, A1-A3= VIL,
Read Device Code VILVILV
A6 = VIL, A9 = VID,
IH
Others VIL or V
Read Extended Memory
Block Verify Code
V
ILVILVIH
A0 -A1 = VIH, A2-A3= VIL,
A6 = VIL, A9 = VID,
Others V
A0,A2,A3, A6= VIL,
Read Block Protection
Status
V
ILVILVIH
A1= VIH, A9 = VID,
A12-A21 = Block address,
Others VIL or V
1. X = VIL or VIH.
Table 5. Bus operations, BYTE = V
IH
Operation E G W
(1)
Address Inputs
DQ15A–1, A0-A21
IH
or V
IL
IH
IH
(1)
Address Inputs
IH
A0-A21
Data Inputs/Outputs
DQ14-DQ8 DQ7-DQ0
Hi-Z 20h
Hi-Z
Hi-Z
Hi-Z
EDh (M29W640FT)
FDh (M29W640FB)
80h (Factory Locked)
00h (Customer Lockable)
01h (protected)
00h (unprotected)
Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
Bus Read V
Bus Write V
IL
IL
Output Disable X V
Standby V
Read Manufacturer Code V
Read Device Code V
Read Extended Memory
Block Verify Code
Read Block Protection
Status
1. X = VIL or VIH.
IH
IL
IL
V
IL
V
IL
V
VIHCell address Data Output
IL
V
VILCommand address Data Input
IH
VIHXHi-Z
IH
XXX Hi-Z
V
IL
V
IL
V
IL
V
IL
A0-A3 = VIL, A6 = VIL,
V
IH
A9 = V
A0 = VIH, A1-A3= VIL, A6 = VIL,
V
IH
A9 = VID, Others VIL or V
, Others VIL or V
ID
IH
IH
A0 -A1 = VIH, A2-A3= VIL,
V
IH
A6 = V
Others V
, A9 = VID,
IL
or V
IL
IH
A0,A2,A3, A6= VIL, A1 = VIH, A9 = VID,
V
A12-A21 = Block address,
IH
Others VIL or V
IH
0020h
22EDh (M29W640FT)
22FDh (M29W640FB)
80h (Factory Locked)
00h (Customer Lockable)
0001h (protected)
0000h (unprotected)
17/71
Command interface M29W640FT, M29W640FB
4 Command interface
All Bus Write operations to the memory are interpreted by the Command Interface.
Commands consist of one or more sequential Bus Write operations. Failure to observe a
valid sequence of Bus Write operations will result in the memory returning to Read mode.
The long command sequences are imposed to maximize data security.
The address used for the commands changes depending on whether the memory is in 16bit or 8-bit mode. See either Ta b le 6 , or Ta bl e 7 , depending on the configuration that is being
used, for a summary of the commands.
4.1 Standard commands
4.1.1 Read/Reset command
The Read/Reset command returns the memory to its Read mode. It also resets the errors in
the Status Register. Either one or three Bus Write operations can be used to issue the
Read/Reset command.
The Read/Reset command can be issued, between Bus Write cycles before the start of a
program or erase operation, to return the device to read mode. If the Read/Reset command
is issued during the timeout of a Block Erase operation then the memory will take up to 10µs
to abort. During the abort period no valid data can be read from the memory. The
Read/Reset command will not abort an Erase operation when issued while in Erase
Suspend.
4.1.2 Auto Select command
The Auto Select command is used to read the Manufacturer Code, the Device Code, the
Block Protection Status and the Extended Memory Block Verify Code. Three consecutive
Bus Write operations are required to issue the Auto Select command. Once the Auto Select
command is issued the memory remains in Auto Select mode until a Read/Reset command
is issued. Read CFI Query and Read/Reset commands are accepted in Auto Select mode,
all other commands are ignored.
In Auto Select mode, the Manufacturer Code and the Device Code can be read by using a
Bus Read operation with addresses and control signals set as shown in Tabl e 4: B us
operations, BYTE = V
Care’.
The Block Protection Status of each block can be read using a Bus Read operation with
addresses and control signals set as shown in Table 4: Bus operations, BYTE = V
Table 5: Bus operations, BYTE = V
block is protected then 01h is output on Data Inputs/Outputs DQ0-DQ7, otherwise 00h is
output (in 8-bit mode).
The protection status of the Extended Memory block, or Extended Memory Block Verify
code, can be read using a Bus Read operation with addresses and control signals set as
shown in Table 4: Bus operations, BYTE = V
except for A9 that is ‘Don’t Care’. If the Extended Block is "Factory Locked" then 80h is
output on Data Input/Outputs DQ0-DQ7, otherwise 00h is output (8-bit mode).
and Table 5: Bus operations, BYTE = VIH, except for A9 that is ‘Don’t
IL
and
, except for A9 that is ‘Don’t Care’. If the addressed
IH
and Table 5: Bus operations, BYTE = VIH,
IL
IL
18/71
M29W640FT, M29W640FB Command interface
4.1.3 Read CFI Query command
The Read CFI Query Command is used to read data from the Common Flash Interface
(CFI) Memory Area. This command is valid when the device is in the Read Array mode, or
when the device is in Autoselected mode.
One Bus Write cycle is required to issue the Read CFI Query Command. Once the
command is issued subsequent Bus Read operations read from the Common Flash
Interface Memory Area.
The Read/Reset command must be issued to return the device to the previous mode (the
Read Array mode or Autoselected mode). A second Read/Reset command would be
needed if the device is to be put in the Read Array mode from Autoselected mode.
See Appendix B: Common Flash Interface (CFI), Tables 23, 24, 25, 26, 27 and 28 for details
on the information contained in the Common Flash Interface (CFI) memory area.
4.1.4 Chip Erase command
The Chip Erase command can be used to erase the entire chip. Six Bus Write operations
are required to issue the Chip Erase Command and start the Program/Erase Controller.
If any blocks are protected then these are ignored and all the other blocks are erased. If all
of the blocks are protected the Chip Erase operation appears to start but will terminate
within about 100µs, leaving the data unchanged. No error condition is given when protected
blocks are ignored.
During the erase operation the memory will ignore all commands, including the Erase
Suspend command. It is not possible to issue any command to abort the operation. Typical
chip erase times are given in Table 8: Program, Erase times and Program, Erase Endurance
cycles. All Bus Read operations during the Chip Erase operation will output the Status
Register on the Data Inputs/Outputs. See the section on the Status Register for more
details.
After the Chip Erase operation has completed the memory will return to the Read Mode,
unless an error has occurred. When an error occurs the memory will continue to output the
Status Register. A Read/Reset command must be issued to reset the error condition and
return to Read Mode.
The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All
previous data is lost.
19/71
Command interface M29W640FT, M29W640FB
4.1.5 Block Erase command
The Block Erase command can be used to erase a list of one or more blocks. Six Bus Write
operations are required to select the first block in the list. Each additional block in the list can
be selected by repeating the sixth Bus Write operation using the address of the additional
block. The Block Erase operation starts the Program/Erase Controller about 50µs after the
last Bus Write operation. Once the Program/Erase Controller starts it is not possible to
select any more blocks. Each additional block must therefore be selected within 50µs of the
last block. The 50µs timer restarts when an additional block is selected. The Status Register
can be read after the sixth Bus Write operation. See the Status Register section for details
on how to identify if the Program/Erase Controller has started the Block Erase operation.
If any selected blocks are protected then these are ignored and all the other selected blocks
are erased. If all of the selected blocks are protected the Block Erase operation appears to
start but will terminate within about 100µs, leaving the data unchanged. No error condition is
given when protected blocks are ignored.
During the Block Erase operation the memory will ignore all commands except the Erase
Suspend command. Typical block erase times are given in Table 8: Program, Erase times
and Program, Erase Endurance cycles. All Bus Read operations during the Block Erase
operation will output the Status Register on the Data Inputs/Outputs. See the section on the
Status Register for more details.
After the Block Erase operation has completed the memory will return to the Read Mode,
unless an error has occurred. When an error occurs the memory will continue to output the
Status Register. A Read/Reset command must be issued to reset the error condition and
return to Read mode.
The Block Erase Command sets all of the bits in the unprotected selected blocks to ’1’. All
previous data in the selected blocks is lost.
4.1.6 Erase Suspend command
The Erase Suspend Command may be used to temporarily suspend a Block Erase
operation and return the memory to Read mode. The command requires one Bus Write
operation.
The Program/Erase Controller will suspend within the Erase Suspend Latency time of the
Erase Suspend Command being issued. Once the Program/Erase Controller has stopped
the memory will be set to Read mode and the Erase will be suspended. If the Erase
Suspend command is issued during the period when the memory is waiting for an additional
block (before the Program/Erase Controller starts) then the Erase is suspended immediately
and will start immediately when the Erase Resume Command is issued. It is not possible to
select any further blocks to erase after the Erase Resume.
During Erase Suspend it is possible to Read and Program cells in blocks that are not being
erased; both Read and Program operations behave as normal on these blocks. If any
attempt is made to program in a protected block or in the suspended block then the Program
command is ignored and the data remains unchanged. The Status Register is not read and
no error condition is given. Reading from blocks that are being erased will output the Status
Register.
It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands
during an Erase Suspend. The Read/Reset command must be issued to return the device to
Read Array mode before the Resume command will be accepted.
20/71
M29W640FT, M29W640FB Command interface
4.1.7 Erase Resume command
The Erase Resume command must be used to restart the Program/Erase Controller after an
Erase Suspend. The device must be in Read Array mode before the Resume command will
be accepted. An erase can be suspended and resumed more than once.
4.1.8 Program Suspend command
The Program Suspend command allows the system to interrupt a program operation so that
data can be read from any block. When the Program Suspend command is issued during a
program operation, the device suspends the program operation within the Program Suspend
Latency time (see Table 8: Program, Erase times and Program, Erase Endurance cycles for
value) and updates the Status Register bits.
After the program operation has been suspended, the system can read array data from any
address. However, data read from Program-Suspended addresses is not valid.
The Program Suspend command may also be issued during a program operation while an
erase is suspended. In this case, data may be read from any addresses not in Erase
Suspend or Program Suspend. If a read is needed from the Extended Block area (One-time
Program area), the user must use the proper command sequences to enter and exit this
region.
The system may also issue the Auto Select command sequence when the device is in the
Program Suspend mode. The system can read as many Auto Select codes as required.
When the device exits the Auto Select mode, the device reverts to the Program Suspend
mode, and is ready for another valid operation. See Auto Select command sequence for
more information.
4.1.9 Program Resume command
After the Program Resume command is issued, the device reverts to programming. The
controller can determine the status of the program operation using the DQ7 or DQ6 status
bits, just as in the standard program operation. See Write Operation Status for more
information.
The system must write the Program Resume command, to exit the Program Suspend mode
and to continue the programming operation.
Further issuing of the Resume command is ignored. Another Program Suspend command
can be written after the device has resumed programming.
21/71
Command interface M29W640FT, M29W640FB
4.1.10 Program command
The Program command can be used to program a value to one address in the memory array
at a time. The command requires four Bus Write operations, the final write operation latches
the address and data, and starts the Program/Erase Controller.
Programming can be suspended and then resumed by issuing a Program Suspend
command and a Program Resume command, respectively (see Section 4.1.8: Program
Suspend command and Section 4.1.9: Program Resume command).
If the address falls in a protected block then the Program command is ignored, the data
remains unchanged. The Status Register is never read and no error condition is given.
During the program operation the memory will ignore all commands. It is not possible to
issue any command to abort or pause the operation. Typical program times are given in
Table 8: Program, Erase times and Program, Erase Endurance cycles. Bus Read operations
during the program operation will output the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more details.
After the program operation has completed the memory will return to the Read mode, unless
an error has occurred. When an error occurs the memory will continue to output the Status
Register. A Read/Reset command must be issued to reset the error condition and return to
Read mode.
Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase
Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.
22/71
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