Numonyx M29W640FT, M29W640FB Technical data

M29W640FT

M29W640FB

64 Mbit (8Mb x8 or 4Mb x16, Page, Boot Block)

3V Supply Flash Memory

Feature summary

■ Supply voltage

–V

–V

■ Asynchronous Random/Page Read

– Page Width: 4 Words
– Page Access: 25ns
– Random Access: 60ns, 70ns

■ Programming time

– 10µs per Byte/Word typical
– 4 Words / 8 Bytes Program

■ 135 Memory Blocks

– 1 Boot Block and 7 Parameter Blocks,

– 127 Main Blocks, 64 KBytes each

■ Program/Erase Controller

– Embedded Byte/Word Program algorithms

■ Program/Erase Suspend and Resume

– Read from any Block during Program

– Read and Program another Block during

■ Unlock Bypass Program command

– Faster Production/Batch Programming

■ V

PP

■ Temporary Block Unprotection mode

■ Common Flash Interface

– 64-bit Security Code

2.7V to 3.6V for Program, Erase,

CC =

Read

=12 V for Fast Program (optional)

PP

8 KBytes each (Top or Bottom location)

Suspend

Erase Suspend

/WP pin for Fast Program and Write Protect

TSOP48 (N)

12 x 20mm

FBGA

TFBGA48 (ZA)

6x8mm

■ Extended Memory Block

■ Extra block used as security block or to store

additional information

■ Low power consumption

– Standby and Automatic Standby

■ 100,000 Program/Erase cycles per block

■ Electronic Signature

– Manufacturer Code: 0020h

■ ECOPACK

®

packages

Table 1. Device Codes

Root Part Number Device Code

M29W640FT 22EDh

M29W640FB 22FDh

December 2007 Rev 7 1/71

www.numonyx.com

1

Contents M29W640FT, M29W640FB

Contents

1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1 Address Inputs (A0-A21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2 Data Inputs/Outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3 Data Inputs/Outputs (DQ8-DQ14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.4 Data Input/Output or Address Input (DQ15A–1) . . . . . . . . . . . . . . . . . . . 11

2.5 Chip Enable (E

2.6 Output Enable (G

2.7 Write Enable (W

2.8 V

/Write Protect (V

PP

2.9 Reset/Block Temporary Unprotect (RP

2.10 Ready/Busy Output (RB

2.11 Byte/Word Organization Select (BYTE

2.12 V

2.13 V

Supply Voltage (2.7V to 3.6V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

CC

Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

SS

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

PP/

) . . . . . . . . . . . . . . . . . . . . . . . . . . 13

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

) . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.2 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.3 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.4 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.5 Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.6 Special Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.6.1 Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.6.2 Block Protect and Chip Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.1 Standard commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.1.1 Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.1.2 Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.1.3 Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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M29W640FT, M29W640FB Contents

4.1.4 Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.1.5 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1.6 Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1.7 Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.1.8 Program Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.1.9 Program Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.1.10 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.2 Fast Program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.2.1 Double Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.2.2 Quadruple Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.2.3 Octuple Byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2.4 Double Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.2.5 Quadruple Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2.6 Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2.7 Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.2.8 Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.3 Block Protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.3.1 Enter Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.3.2 Exit Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.3.3 Block Protect and Chip Unprotect commands . . . . . . . . . . . . . . . . . . . . 26

5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.1 Data Polling Bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.2 Toggle Bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.3 Error Bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.4 Erase Timer Bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.5 Alternative Toggle Bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

9 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Appendix A Block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

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Contents M29W640FT, M29W640FB

Appendix B Common Flash Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Appendix C Extended Memory Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

C.1 Factory Locked Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

C.2 Customer Lockable Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Appendix D Block protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

D.1 Programmer technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

D.2 In-System technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

4/71

M29W640FT, M29W640FB List of tables

List of tables

Table 1. Device Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 3. Hardware protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 4. Bus operations, BYTE
Table 5. Bus operations, BYTE
Table 6. Commands, 16-bit mode, BYTE
Table 7. Commands, 8-bit mode, BYTE = V

Table 8. Program, Erase times and Program, Erase Endurance cycles. . . . . . . . . . . . . . . . . . . . . . 29

Table 9. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 10. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 11. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 12. Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 13. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 14. Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 15. Write AC characteristics, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 16. Write AC characteristics, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 17. Reset/Block Temporary Unprotect AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 18. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, package mechanical data . . . 44

Table 19. TFBGA48 6x8mm - 6x8 active ball array, 0.8mm pitch, package mechanical data . . . . . . 45

Table 20. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 21. Top Boot Block addresses, M29W640FT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 22. Bottom Boot Block addresses, M29W640FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Table 23. Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 24. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 25. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 26. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 27. Primary Algorithm-specific Extended Query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 28. Security Code Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 29. Extended Block address and data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 30. Programmer technique bus operations, BYTE

Table 31. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

= VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

= VIH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

= V

IH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

IL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

= VIH or V

IL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

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List of figures M29W640FT, M29W640FB

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 2. TSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 3. TFBGA48 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 4. Data Polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 5. Data Toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 6. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 7. AC measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 8. Read Mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 9. Page Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 10. Write AC waveforms, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 11. Write AC waveforms, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 12. Reset/Block Temporary Unprotect AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 13. Accelerated Program Timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 14. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, top view package outline . . . . 44

Figure 15. TFBGA48 6x8mm - 6x8 active ball array, 0.8mm pitch, package outline . . . . . . . . . . . . . . 45

Figure 16. Programmer Equipment Group Protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 17. Programmer Equipment Chip Unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 18. In-System Equipment Group Protect flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 19. In-System Equipment Chip Unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

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M29W640FT, M29W640FB Summary description

1 Summary description

The M29W640F is a 64 Mbit (8Mb x8 or 4Mb x16) non-volatile memory that can be read,
erased and reprogrammed. These operations can be performed using a single low voltage
(2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode.

The memory is divided into blocks that can be erased independently so it is possible to
preserve valid data while old data is erased. Blocks can be protected in units of 256 KByte
(generally groups of four 64 KByte blocks), to prevent accidental Program or Erase
commands from modifying the memory. Program and Erase commands are written to the
Command Interface of the memory. An on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by taking care of all of the special
operations that are required to update the memory contents. The end of a program or erase
operation can be detected and any error conditions identified. The command set required to
control the memory is consistent with JEDEC standards.

The device features an asymmetrical blocked architecture. The device has an array of 135
blocks:

● 8 Parameters Blocks of 8 KBytes each (or 4 KWords each)

● 127 Main Blocks of 64 KBytes each (or 32 KWords each)

M29W640FT has the Parameter Blocks at the top of the memory address space while the
M29W640FB locates the Parameter Blocks starting from the bottom.

The M29W640F has an extra block, the Extended Block, of 128 Words in x16 mode or of
256 Byte in x8 mode that can be accessed using a dedicated command. The Extended
Block can be protected and so is useful for storing security information. However the
protection is not reversible, once protected the protection cannot be undone.

Chip Enable, Output Enable and Write Enable signals control the bus operation of the
memory. They allow simple connection to most microprocessors, often without additional
logic.

The V
word/byte programming. If this signal is held at V

/WP signal is used to enable faster programming of the device, enabling multiple

PP

, the boot block, and its adjacent

SS

parameter block, are protected from program and erase operations.

The device supports Asynchronous Random Read and Page Read from all blocks of the
memory array.

The memories are offered in TSOP48 (12x 20mm) and TFBGA48 (6x8mm, 0.8mm pitch)
packages.

In order to meet environmental requirements, ST offers the M29W640FT and the
M29W640FB in ECOPACK

®

packages. ECOPACK packages are Lead-free. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.

The memory is delivered with all the bits erased (set to 1).

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Summary description M29W640FT, M29W640FB

Figure 1. Logic diagram

VPP/WP

V

CC

A0-A21

W

22

E

M29W640FT

M29W640FB

G

15

DQ0-DQ14

DQ15A–1

BYTE

RB

RP

V

SS

AI11250

Table 2. Signal names

A0-A21 Address Inputs

DQ0-DQ7 Data Inputs/Outputs

DQ8-DQ14 Data Inputs/Outputs

DQ15A–1 (or DQ15) Data Input/Output or Address Input (or Data Input/Output)

E Chip Enable

G

W

RP

RB

BYTE

V

CC

/WP Supply voltage for Fast Program (optional) or Write Protect

V

PP

V

SS

Output Enable

Write Enable

Reset/Block Temporary Unprotect

Ready/Busy Output

Byte/Word Organization Select

Supply voltage

Ground

NC Not Connected Internally

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M29W640FT, M29W640FB Summary description

Figure 2. TSOP connections

A15

1

48
A14
A13
A12
A11
A10 DQ14

A9

A8
A19
A20

M29W640FT
M29W640FB

W

RP

A21

12
13

37
36

VPP/WP

RB
A18
A17

A7
A6
A5
A4
A3
A2

24 25

A1

A16
BYTE
V

SS

DQ15A–1
DQ7

DQ6
DQ13
DQ5
DQ12
DQ4
V

CC

DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
V

SS

E
A0

AI11251

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Summary description M29W640FT, M29W640FB

Figure 3. TFBGA48 connections (top view through package)

654321

A

B

C

D

E

F

G

H

A3

A4

A2

A1

A0

E

G

V

SS

A7

A17

A6

A5 A20

DQ0

DQ8

DQ9

DQ1

RB

V

PP

A18

DQ2

DQ10

DQ11

DQ3

/

WP

W

RP

A21

A19

DQ5

DQ12

V

CC

DQ4

A9

A8

A10

A11

DQ7

DQ14

DQ13

DQ6

A13

A12

A14

A15

A16

BYTE

DQ15

A–1

V

SS

10/71

AI11554

M29W640FT, M29W640FB Signal descriptions

2 Signal descriptions

See Figure 1: Logic diagram, and Table 2: Signal names, for a brief overview of the signals
connected to this device.

2.1 Address Inputs (A0-A21)

The Address Inputs select the cells in the memory array to access during Bus Read
operations. During Bus Write operations they control the commands sent to the Command
Interface of the Program/Erase Controller.

2.2 Data Inputs/Outputs (DQ0-DQ7)

The Data I/O outputs the data stored at the selected address during a Bus Read operation.
During Bus Write operations they represent the commands sent to the Command Interface
of the Program/Erase Controller.

2.3 Data Inputs/Outputs (DQ8-DQ14)

The Data I/O outputs the data stored at the selected address during a Bus Read operation
when BYTE
impedance. During Bus Write operations the Command Register does not use these bits.
When reading the Status Register these bits should be ignored.

is High, VIH. When BYTE is Low, VIL, these pins are not used and are high

2.4 Data Input/Output or Address Input (DQ15A–1)

When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14).
When BYTE
LSB of the addressed Word, DQ15A–1 High will select the MSB. Throughout the text
consider references to the Data Input/Output to include this pin when BYTE
references to the Address Inputs to include this pin when BYTE
explicitly otherwise.

is Low, VIL, this pin behaves as an address pin; DQ15A–1 Low will select the

is Low except when stated

2.5 Chip Enable (E)

The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to
be performed. When Chip Enable is High, V

, all other pins are ignored.

IH

2.6 Output Enable (G)

The Output Enable, G, controls the Bus Read operation of the memory.

is High and

11/71

Signal descriptions M29W640FT, M29W640FB

2.7 Write Enable (W)

The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface.

2.8 VPP/Write Protect (VPP/WP)

The VPP/Write Protect pin provides two functions. The VPP function allows the memory to
use an external high voltage power supply to reduce the time required for Unlock Bypass
Program operations. The Write Protect function provides a hardware method of protecting
the two outermost boot blocks. The V
unconnected.

/Write Protect pin must not be left floating or

PP

When V
Program and Erase operations in this block are ignored while V
when RP

When V

/Write Protect is Low, VIL, the memory protects the two outermost boot blocks;

PP

/Write Protect is Low, even

PP

is at VID.

/Write Protect is High, VIH, the memory reverts to the previous protection status

PP

of the two outermost boot blocks. Program and Erase operations can now modify the data in
the two outermost boot blocks unless the block is protected using Block Protection.

Applying V

to the VPP/WP pin will temporarily unprotect any block previously protected

PPH

(including the two outermost parameter blocks) using a High Voltage Block Protection
technique (In-System or Programmer technique). See Table 3: Hardware protection for
details.

When V
Bypass mode. When V
During Unlock Bypass Program operations the memory draws I

/Write Protect is raised to V

PP

/Write Protect returns to VIH or VIL normal operation resumes.

PP

the memory automatically enters the Unlock

PP

from the pin to supply the

PP

programming circuits. See the description of the Unlock Bypass command in the Command
Interface section. The transitions from V
t

, see Figure 13: Accelerated Program Timing waveforms.

VHVPP

Never raise V

/Write Protect to VPP from any mode except Read mode, otherwise the

PP

to VPP and from VPP to VIH must be slower than

IH

memory may be left in an indeterminate state.

A 0.1µF capacitor should be connected between the V

/Write Protect pin and the VSS

PP

Ground pin to decouple the current surges from the power supply. The PCB track widths
must be sufficient to carry the currents required during Unlock Bypass Program, I

Table 3. Hardware protection

PP

.

VPP/WP RP Function

V

V

IL

or V

V

IH

ID

V

PPH

12/71

IH

V

ID

V

ID

VIH or V

2 outermost parameter blocks protected from Program/Erase operations

All blocks temporarily unprotected except the 2 outermost blocks

All blocks temporarily unprotected

All blocks temporarily unprotected

ID

M29W640FT, M29W640FB Signal descriptions

2.9 Reset/Block Temporary Unprotect (RP)

The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the
memory or to temporarily unprotect all Blocks that have been protected.

Note that if V
if RP is at V

/WP is at VIL, then the two outermost boot blocks will remain protected even

PP

.

ID

A Hardware Reset is achieved by holding Reset/Block Temporary Unprotect Low, V
least t

. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be

PLPX

ready for Bus Read and Bus Write operations after t
See the Ready/Busy Output section, Table 17: Reset/Block Temporary Unprotect AC

characteristics and Figure 12: Reset/Block Temporary Unprotect AC waveforms, for more

details.

Holding RP

at VID will temporarily unprotect the protected Blocks in the memory. Program
and Erase operations on all blocks will be possible. The transition from V
slower than t

PHPHH

.

2.10 Ready/Busy Output (RB)

The Ready/Busy pin is an open-drain output that can be used to identify when the device is
performing a Program or Erase operation. During Program or Erase operations Ready/Busy
is Low, V
Erase Suspend mode.

After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy
becomes high-impedance. See Table 17: Reset/Block Temporary Unprotect AC

characteristics and Figure 12: Reset/Block Temporary Unprotect AC waveforms, for more

details.

. Ready/Busy is high-impedance during Read mode, Auto Select mode and

OL

PHEL

or t

, whichever occurs last.

RHEL

to VID must be

IH

, for at

IL

The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the
memories is busy.

2.11 Byte/Word Organization Select (BYTE)

The Byte/Word Organization Select pin is used to switch between the x8 and x16 Bus
modes of the memory. When Byte/Word Organization Select is Low, V
x8 mode, when it is High, V

, the memory is in x16 mode.

IH

, the memory is in

IL

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Signal descriptions M29W640FT, M29W640FB

2.12 VCC Supply Voltage (2.7V to 3.6V)

VCC provides the power supply for all operations (Read, Program and Erase).

The Command Interface is disabled when the V
Voltage, V

. This prevents Bus Write operations from accidentally damaging the data

LKO

during power up, power down and power surges. If the Program/Erase Controller is
programming or erasing during this time then the operation aborts and the memory contents
being altered will be invalid.

A 0.1µF capacitor should be connected between the V
Ground pin to decouple the current surges from the power supply. The PCB track widths
must be sufficient to carry the currents required during Program and Erase operations, I

2.13 VSS Ground

VSS is the reference for all voltage measurements. The device features two VSS pins which
must be both connected to the system ground.

Supply voltage is less than the Lockout

CC

Supply voltage pin and the VSS

CC

CC3

.

14/71

M29W640FT, M29W640FB Bus operations

3 Bus operations

There are five standard bus operations that control the device. These are Bus Read, Bus
Write, Output Disable, Standby and Automatic Standby. See Table 4: Bus operations, BYTE

= V

and Table 5: Bus operations, BYTE = VIH, for a summary. Typically glitches of less than

IL

5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus
operations.

3.1 Bus Read

Bus Read operations read from the memory cells, or specific registers in the Command
Interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs, applying a Low signal, V
Enable High, V

AC waveforms, and Table 14: Read AC characteristics, for details of when the output

becomes valid.

3.2 Bus Write

. The Data Inputs/Outputs will output the value, see Figure 8: Read Mode

IH

, to Chip Enable and Output Enable and keeping Write

IL

Bus Write operations write to the Command Interface. To speed up the read operation the
memory array can be read in Page mode where data is internally read and stored in a page
buffer. The Page has a size of 4 Words and is addressed by the address inputs A0-A1.

A valid Bus Write operation begins by setting the desired address on the Address Inputs.
The Address Inputs are latched by the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the
Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs
first. Output Enable must remain High, V

Figure 10: Write AC waveforms, Write Enable controlled, Figure 11: Write AC waveforms,
Chip Enable controlled, and Table 15: Write AC characteristics, Write Enable controlled and
Table 16: Write AC characteristics, Chip Enable controlled, for details of the timing

requirements.

3.3 Output Disable

The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH.

3.4 Standby

When Chip Enable is High, VIH, the memory enters Standby mode and the Data
Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to
the Standby Supply Current, I
Standby current level see Table 13: DC characteristics.

, during the whole Bus Write operation. See

IH

, Chip Enable should be held within V

CC2

± 0.2V. For the

CC

During program or erase operations the memory will continue to use the Program/Erase
Supply Current, I

, for Program or Erase operations until the operation completes.

CC3

15/71

Bus operations M29W640FT, M29W640FB

3.5 Automatic Standby

If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 300ns or
more the memory enters Automatic Standby where the internal Supply Current is reduced to
the Standby Supply Current, I

. The Data Inputs/Outputs will still output data if a Bus

CC2

Read operation is in progress.

3.6 Special Bus operations

Additional bus operations can be performed to read the Electronic Signature and also to
apply and remove Block Protection. These bus operations are intended for use by
programming equipment and are not usually used in applications. They require V
applied to some pins.

3.6.1 Electronic Signature

The memory has two codes, the manufacturer code and the device code, that can be read
to identify the memory. These codes can be read by applying the signals listed in Ta bl e 4 :

Bus operations, BYTE = V

and Table 5: Bus operations, BYTE = VIH.

IL

3.6.2 Block Protect and Chip Unprotect

to be

ID

Groups of blocks can be protected against accidental Program or Erase. The Protection
Groups are shown in Appendix A: Block addresses Tab le 2 1 and Ta bl e 2 2 . The whole chip
can be unprotected to allow the data inside the blocks to be changed.

The V
V

PP

/Write Protect pin can be used to protect the two outermost boot blocks. When

PP

/Write Protect is at V

the two outermost boot blocks are protected and remain

IL

protected regardless of the Block Protection Status or the Reset/Block Temporary
Unprotect pin status.

Block Protect and Chip Unprotect operations are described in Appendix D: Block protection.

16/71

M29W640FT, M29W640FB Bus operations

Table 4. Bus operations, BYTE = VIL

Operation E G W

Bus Read V

Bus Write V

Output Disable X V

Standby V

ILVILVIH

ILVIHVIL

IHVIH

X X X Hi-Z Hi-Z

IH

Read Manufacturer Code VILVILV

Cell address Hi-Z Data Output

Command address Hi-Z Data Input

X Hi-Z Hi-Z

A0-A3 = VIL, A6 = VIL,

IH

A9 = VID, Others VIL or V

A0 = VIH, A1-A3= VIL,

Read Device Code VILVILV

A6 = VIL, A9 = VID,

IH

Others VIL or V

Read Extended Memory
Block Verify Code

V

ILVILVIH

A0 -A1 = VIH, A2-A3= VIL,
A6 = VIL, A9 = VID,
Others V

A0,A2,A3, A6= VIL,
Read Block Protection
Status

V

ILVILVIH

A1= VIH, A9 = VID,

A12-A21 = Block address,

Others VIL or V

1. X = VIL or VIH.

Table 5. Bus operations, BYTE = V

IH

Operation E G W

(1)

Address Inputs

DQ15A–1, A0-A21

IH

or V

IL

IH

IH

(1)

Address Inputs

IH

A0-A21

Data Inputs/Outputs

DQ14-DQ8 DQ7-DQ0

Hi-Z 20h

Hi-Z

Hi-Z

Hi-Z

EDh (M29W640FT)
FDh (M29W640FB)

80h (Factory Locked)

00h (Customer Lockable)

01h (protected)

00h (unprotected)

Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

Bus Read V

Bus Write V

IL

IL

Output Disable X V

Standby V

Read Manufacturer Code V

Read Device Code V

Read Extended Memory
Block Verify Code

Read Block Protection
Status

1. X = VIL or VIH.

IH

IL

IL

V

IL

V

IL

V

VIHCell address Data Output

IL

V

VILCommand address Data Input

IH

VIHXHi-Z

IH

XXX Hi-Z

V

IL

V

IL

V

IL

V

IL

A0-A3 = VIL, A6 = VIL,

V

IH

A9 = V

A0 = VIH, A1-A3= VIL, A6 = VIL,

V

IH

A9 = VID, Others VIL or V

, Others VIL or V

ID

IH

IH

A0 -A1 = VIH, A2-A3= VIL,

V

IH

A6 = V
Others V

, A9 = VID,

IL

or V

IL

IH

A0,A2,A3, A6= VIL, A1 = VIH, A9 = VID,

V

A12-A21 = Block address,

IH

Others VIL or V

IH

0020h

22EDh (M29W640FT)
22FDh (M29W640FB)

80h (Factory Locked)

00h (Customer Lockable)

0001h (protected)

0000h (unprotected)

17/71

Command interface M29W640FT, M29W640FB

4 Command interface

All Bus Write operations to the memory are interpreted by the Command Interface.
Commands consist of one or more sequential Bus Write operations. Failure to observe a
valid sequence of Bus Write operations will result in the memory returning to Read mode.
The long command sequences are imposed to maximize data security.

The address used for the commands changes depending on whether the memory is in 16­bit or 8-bit mode. See either Ta b le 6 , or Ta bl e 7 , depending on the configuration that is being
used, for a summary of the commands.

4.1 Standard commands

4.1.1 Read/Reset command

The Read/Reset command returns the memory to its Read mode. It also resets the errors in
the Status Register. Either one or three Bus Write operations can be used to issue the
Read/Reset command.

The Read/Reset command can be issued, between Bus Write cycles before the start of a
program or erase operation, to return the device to read mode. If the Read/Reset command
is issued during the timeout of a Block Erase operation then the memory will take up to 10µs
to abort. During the abort period no valid data can be read from the memory. The
Read/Reset command will not abort an Erase operation when issued while in Erase
Suspend.

4.1.2 Auto Select command

The Auto Select command is used to read the Manufacturer Code, the Device Code, the
Block Protection Status and the Extended Memory Block Verify Code. Three consecutive
Bus Write operations are required to issue the Auto Select command. Once the Auto Select
command is issued the memory remains in Auto Select mode until a Read/Reset command
is issued. Read CFI Query and Read/Reset commands are accepted in Auto Select mode,
all other commands are ignored.

In Auto Select mode, the Manufacturer Code and the Device Code can be read by using a
Bus Read operation with addresses and control signals set as shown in Tabl e 4: B us

operations, BYTE = V

Care’.

The Block Protection Status of each block can be read using a Bus Read operation with
addresses and control signals set as shown in Table 4: Bus operations, BYTE = V

Table 5: Bus operations, BYTE = V

block is protected then 01h is output on Data Inputs/Outputs DQ0-DQ7, otherwise 00h is
output (in 8-bit mode).

The protection status of the Extended Memory block, or Extended Memory Block Verify
code, can be read using a Bus Read operation with addresses and control signals set as
shown in Table 4: Bus operations, BYTE = V
except for A9 that is ‘Don’t Care’. If the Extended Block is "Factory Locked" then 80h is
output on Data Input/Outputs DQ0-DQ7, otherwise 00h is output (8-bit mode).

and Table 5: Bus operations, BYTE = VIH, except for A9 that is ‘Don’t

IL

and

, except for A9 that is ‘Don’t Care’. If the addressed

IH

and Table 5: Bus operations, BYTE = VIH,

IL

IL

18/71

M29W640FT, M29W640FB Command interface

4.1.3 Read CFI Query command

The Read CFI Query Command is used to read data from the Common Flash Interface
(CFI) Memory Area. This command is valid when the device is in the Read Array mode, or
when the device is in Autoselected mode.

One Bus Write cycle is required to issue the Read CFI Query Command. Once the
command is issued subsequent Bus Read operations read from the Common Flash
Interface Memory Area.

The Read/Reset command must be issued to return the device to the previous mode (the
Read Array mode or Autoselected mode). A second Read/Reset command would be
needed if the device is to be put in the Read Array mode from Autoselected mode.

See Appendix B: Common Flash Interface (CFI), Tables 23, 24, 25, 26, 27 and 28 for details
on the information contained in the Common Flash Interface (CFI) memory area.

4.1.4 Chip Erase command

The Chip Erase command can be used to erase the entire chip. Six Bus Write operations
are required to issue the Chip Erase Command and start the Program/Erase Controller.

If any blocks are protected then these are ignored and all the other blocks are erased. If all
of the blocks are protected the Chip Erase operation appears to start but will terminate
within about 100µs, leaving the data unchanged. No error condition is given when protected
blocks are ignored.

During the erase operation the memory will ignore all commands, including the Erase
Suspend command. It is not possible to issue any command to abort the operation. Typical
chip erase times are given in Table 8: Program, Erase times and Program, Erase Endurance

cycles. All Bus Read operations during the Chip Erase operation will output the Status

Register on the Data Inputs/Outputs. See the section on the Status Register for more
details.

After the Chip Erase operation has completed the memory will return to the Read Mode,
unless an error has occurred. When an error occurs the memory will continue to output the
Status Register. A Read/Reset command must be issued to reset the error condition and
return to Read Mode.

The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All
previous data is lost.

19/71

Command interface M29W640FT, M29W640FB

4.1.5 Block Erase command

The Block Erase command can be used to erase a list of one or more blocks. Six Bus Write
operations are required to select the first block in the list. Each additional block in the list can
be selected by repeating the sixth Bus Write operation using the address of the additional
block. The Block Erase operation starts the Program/Erase Controller about 50µs after the
last Bus Write operation. Once the Program/Erase Controller starts it is not possible to
select any more blocks. Each additional block must therefore be selected within 50µs of the
last block. The 50µs timer restarts when an additional block is selected. The Status Register
can be read after the sixth Bus Write operation. See the Status Register section for details
on how to identify if the Program/Erase Controller has started the Block Erase operation.

If any selected blocks are protected then these are ignored and all the other selected blocks
are erased. If all of the selected blocks are protected the Block Erase operation appears to
start but will terminate within about 100µs, leaving the data unchanged. No error condition is
given when protected blocks are ignored.

During the Block Erase operation the memory will ignore all commands except the Erase
Suspend command. Typical block erase times are given in Table 8: Program, Erase times

and Program, Erase Endurance cycles. All Bus Read operations during the Block Erase

operation will output the Status Register on the Data Inputs/Outputs. See the section on the
Status Register for more details.

After the Block Erase operation has completed the memory will return to the Read Mode,
unless an error has occurred. When an error occurs the memory will continue to output the
Status Register. A Read/Reset command must be issued to reset the error condition and
return to Read mode.

The Block Erase Command sets all of the bits in the unprotected selected blocks to ’1’. All
previous data in the selected blocks is lost.

4.1.6 Erase Suspend command

The Erase Suspend Command may be used to temporarily suspend a Block Erase
operation and return the memory to Read mode. The command requires one Bus Write
operation.

The Program/Erase Controller will suspend within the Erase Suspend Latency time of the
Erase Suspend Command being issued. Once the Program/Erase Controller has stopped
the memory will be set to Read mode and the Erase will be suspended. If the Erase
Suspend command is issued during the period when the memory is waiting for an additional
block (before the Program/Erase Controller starts) then the Erase is suspended immediately
and will start immediately when the Erase Resume Command is issued. It is not possible to
select any further blocks to erase after the Erase Resume.

During Erase Suspend it is possible to Read and Program cells in blocks that are not being
erased; both Read and Program operations behave as normal on these blocks. If any
attempt is made to program in a protected block or in the suspended block then the Program
command is ignored and the data remains unchanged. The Status Register is not read and
no error condition is given. Reading from blocks that are being erased will output the Status
Register.

It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands
during an Erase Suspend. The Read/Reset command must be issued to return the device to
Read Array mode before the Resume command will be accepted.

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M29W640FT, M29W640FB Command interface

4.1.7 Erase Resume command

The Erase Resume command must be used to restart the Program/Erase Controller after an
Erase Suspend. The device must be in Read Array mode before the Resume command will
be accepted. An erase can be suspended and resumed more than once.

4.1.8 Program Suspend command

The Program Suspend command allows the system to interrupt a program operation so that
data can be read from any block. When the Program Suspend command is issued during a
program operation, the device suspends the program operation within the Program Suspend
Latency time (see Table 8: Program, Erase times and Program, Erase Endurance cycles for
value) and updates the Status Register bits.

After the program operation has been suspended, the system can read array data from any
address. However, data read from Program-Suspended addresses is not valid.

The Program Suspend command may also be issued during a program operation while an
erase is suspended. In this case, data may be read from any addresses not in Erase
Suspend or Program Suspend. If a read is needed from the Extended Block area (One-time
Program area), the user must use the proper command sequences to enter and exit this
region.

The system may also issue the Auto Select command sequence when the device is in the
Program Suspend mode. The system can read as many Auto Select codes as required.
When the device exits the Auto Select mode, the device reverts to the Program Suspend
mode, and is ready for another valid operation. See Auto Select command sequence for
more information.

4.1.9 Program Resume command

After the Program Resume command is issued, the device reverts to programming. The
controller can determine the status of the program operation using the DQ7 or DQ6 status
bits, just as in the standard program operation. See Write Operation Status for more
information.

The system must write the Program Resume command, to exit the Program Suspend mode
and to continue the programming operation.

Further issuing of the Resume command is ignored. Another Program Suspend command
can be written after the device has resumed programming.

21/71

Command interface M29W640FT, M29W640FB

4.1.10 Program command

The Program command can be used to program a value to one address in the memory array
at a time. The command requires four Bus Write operations, the final write operation latches
the address and data, and starts the Program/Erase Controller.

Programming can be suspended and then resumed by issuing a Program Suspend
command and a Program Resume command, respectively (see Section 4.1.8: Program

Suspend command and Section 4.1.9: Program Resume command).

If the address falls in a protected block then the Program command is ignored, the data
remains unchanged. The Status Register is never read and no error condition is given.

During the program operation the memory will ignore all commands. It is not possible to
issue any command to abort or pause the operation. Typical program times are given in

Table 8: Program, Erase times and Program, Erase Endurance cycles. Bus Read operations

during the program operation will output the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more details.

After the program operation has completed the memory will return to the Read mode, unless
an error has occurred. When an error occurs the memory will continue to output the Status
Register. A Read/Reset command must be issued to reset the error condition and return to
Read mode.

Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase
Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.

22/71

M29W640FT, M29W640FB Command interface

4.2 Fast Program commands

There are four Fast Program commands available to improve the programming throughput,
by writing several adjacent words or bytes in parallel. The Double, Quadruple and Octuple
Byte Program commands are available for x8 operations, while the Double Quadruple Word
Program command are available for x16 operations.

Fast Program commands can be suspended and then resumed by issuing a Program
Suspend command and a Program Resume command, respectively (see Section 4.1.8:

Program Suspend command and Section 4.1.9: Program Resume command).

When V
Program mode. The user can then choose to issue any of the Fast Program commands.
Care must be taken because applying a V
any protected block.

is applied to the VPP/Write Protect pin the memory automatically enters the Fast

PPH

PPH

4.2.1 Double Byte Program command

The Double Byte Program command is used to write a page of two adjacent Bytes in
parallel. The two bytes must differ only in DQ15A-1. Three bus write cycles are necessary to
issue the Double Byte Program command.

1. The first bus cycle sets up the Double Byte Program Command.

2. The second bus cycle latches the Address and the Data of the first byte to be written.

3. The third bus cycle latches the Address and the Data of the second byte to be written.

4.2.2 Quadruple Byte Program command

The Quadruple Byte Program command is used to write a page of four adjacent Bytes in
parallel. The four bytes must differ only for addresses A0, DQ15A-1. Five bus write cycles
are necessary to issue the Quadruple Byte Program command.

1. The first bus cycle sets up the Quadruple Byte Program Command.

2. The second bus cycle latches the Address and the Data of the first byte to be written.

3. The third bus cycle latches the Address and the Data of the second byte to be written.

4. The fourth bus cycle latches the Address and the Data of the third byte to be written.

5. The fifth bus cycle latches the Address and the Data of the fourth byte to be written and
starts the Program/Erase Controller.

to the VPP/WP pin will temporarily unprotect

23/71

Command interface M29W640FT, M29W640FB

4.2.3 Octuple Byte Program command

This is used to write eight adjacent Bytes, in x8 mode, simultaneously. The addresses of the
eight Bytes must differ only in A1, A0 and DQ15A-1.

Nine bus write cycles are necessary to issue the command:

1. The first bus cycle sets up the command.

2. The second bus cycle latches the Address and the Data of the first Byte to be written.

3. The third bus cycle latches the Address and the Data of the second Byte to be written.

4. The fourth bus cycle latches the Address and the Data of the third Byte to be written.

5. The fifth bus cycle latches the Address and the Data of the fourth Byte to be written.

6. The sixth bus cycle latches the Address and the Data of the fifth Byte to be written.

7. The seventh bus cycle latches the Address and the Data of the sixth Byte to be written.

8. The eighth bus cycle latches the Address and the Data of the seventh Byte to be
written.

9. The ninth bus cycle latches the Address and the Data of the eighth Byte to be written
and starts the Program/Erase Controller.

4.2.4 Double Word Program command

The Double Word Program command is used to write a page of two adjacent Words in
parallel. The two Words must differ only for the address A0.

Three bus write cycles are necessary to issue the Double Word Program command.

● The first bus cycle sets up the Quadruple Word Program Command.

● The second bus cycle latches the Address and the Data of the first Word to be written.

● The third bus cycle latches the Address and the Data of the second Word to be written

and starts the Program/Erase Controller.

After the program operation has completed the memory will return to the Read mode, unless
an error has occurred. When an error occurs Bus Read operations will continue to output
the Status Register. A Read/Reset command must be issued to reset the error condition and
return to Read mode.

Note that the Fast Program commands cannot change a bit set at ’0’ back to ’1’. One of the
Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’
to ’1’.

Typical Program times are given in Table 8: Program, Erase times and Program, Erase

Endurance cycles.

24/71

M29W640FT, M29W640FB Command interface

4.2.5 Quadruple Word Program command

This is used to write a page of four adjacent Words (or 8 adjacent Bytes), in x16 mode,
simultaneously. The addresses of the four Words must differ only in A1 and A0.

Five bus write cycles are necessary to issue the command:

● The first bus cycle sets up the command.

● The second bus cycle latches the Address and the Data of the first Word to be written.

● The third bus cycle latches the Address and the Data of the second Word to be written.

● The fourth bus cycle latches the Address and the Data of the third Word to be written.

● The fifth bus cycle latches the Address and the Data of the fourth Word to be written

and starts the Program/Erase Controller.

4.2.6 Unlock Bypass command

The Unlock Bypass command is used in conjunction with the Unlock Bypass Program
command to program the memory faster than with the standard program commands. When
the cycle time to the device is long, considerable time saving can be made by using these
commands. Three Bus Write operations are required to issue the Unlock Bypass command.

Once the Unlock Bypass command has been issued the memory will only accept the Unlock
Bypass Program command and the Unlock Bypass Reset command. The memory can be
read as if in Read mode.

When V

is applied to the VPP/Write Protect pin the memory automatically enters the

PP

Unlock Bypass mode and the Unlock Bypass Program command can be issued
immediately.

4.2.7 Unlock Bypass Program command

The Unlock Bypass command is used in conjunction with the Unlock Bypass Program
command to program the memory. When the cycle time to the device is long, considerable
time saving can be made by using these commands. Three Bus Write operations are
required to issue the Unlock Bypass command.

Once the Unlock Bypass command has been issued the memory will only accept the Unlock
Bypass Program command and the Unlock Bypass Reset command. The memory can be
read as if in Read mode.

The memory offers accelerated program operations through the V
When the system asserts V

on the VPP/Write Protect pin, the memory automatically

PP

enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass
program command sequence. The memory uses the higher voltage on the V
Protect pin, to accelerate the Unlock Bypass Program operation.

Never raise V

/Write Protect to VPP from any mode except Read mode, otherwise the

PP

memory may be left in an indeterminate state.

4.2.8 Unlock Bypass Reset command

/Write Protect pin.

PP

/Write

PP

The Unlock Bypass Reset command can be used to return to Read/Reset mode from
Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass
Reset command. Read/Reset command does not exit from Unlock Bypass Mode.

25/71

Command interface M29W640FT, M29W640FB

4.3 Block Protection commands

4.3.1 Enter Extended Block command

The device has an extra 256 Byte block (Extended Block) that can only be accessed using
the Enter Extended Block command. Three Bus write cycles are required to issue the
Extended Block command. Once the command has been issued the device enters
Extended Block mode where all Bus Read or Write operations to the Boot Block addresses
access the Extended Block. The Extended Block (with the same address as the Boot
Blocks) cannot be erased, and can be treated as one-time programmable (OTP) memory. In
Extended Block mode the Boot Blocks are not accessible.

To exit from the Extended Block mode the Exit Extended Block command must be issued.

The Extended Block can be protected, however once protected the protection cannot be
undone.

4.3.2 Exit Extended Block command

The Exit Extended Block command is used to exit from the Extended Block mode and return
the device to Read mode. Four Bus Write operations are required to issue the command.

4.3.3 Block Protect and Chip Unprotect commands

Groups of blocks can be protected against accidental Program or Erase. The Protection
Groups are shown in Appendix A: Block addresses, Table 21: Top Boot Block addresses,

M29W640FT and Table 22: Bottom Boot Block addresses, M29W640FB. The whole chip

can be unprotected to allow the data inside the blocks to be changed.

Block Protect and Chip Unprotect operations are described in Appendix D: Block protection.

26/71

M29W640FT, M29W640FB Command interface

Table 6. Commands, 16-bit mode, BYTE = V

(1)

IH

Bus Write operations

Command

1st 2nd 3rd 4th 5th 6th

Length

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

1X F0

Read/Reset

3 555 AA 2AA 55 X F0

Auto Select 3 555 AA 2AA 55 555 90

Program 4 555 AA 2AA 55 555 A0 PA PD

Double Word Program 3 555 50 PA0 PD0 PA1 PD1

Quadruple Word
Program

5 5 5 5 5 6 PA 0 P D 0 PA 1 P D1 PA 2 P D2 PA 3 PD 3

Unlock Bypass 3 555 AA 2AA 55 555 20

Unlock Bypass
Program

2 X A0 PA PD

Unlock Bypass Reset 2 X 90 X 00

Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10

Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30

Program/Erase
Suspend

Program/Erase
Resume

1X B0

1X 30

Read CFI Query 1 55 98

Enter Extended Block 3 555 AA 2AA 55 555 88

Exit Extended Block 4 555 AA 2AA 55 555 90 X 00

1. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in
hexadecimal. The Command interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8­DQ14 and DQ15 are Don’t Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH.

27/71

Command interface M29W640FT, M29W640FB

Table 7. Commands, 8-bit mode, BYTE = V

Command

Read/Reset

IL

Bus Write operations

(1)

1st 2nd 3rd 4th 5th 6th 7th 8th 9th

Length

Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data Add Data

1XF0

3 AAA AA 555 55 X F0

Auto Select 3 AAA AA 555 55 AAA 90

Program 4 AAA AA 555 55 AAA A0 PA PD

Double Byte
Program

Quadruple
Byte Program

Octuple Byte
Program

3 AAA 50 PA0 PD0 PA1 PD1

5 AAA 56 PA0 PD0 PA1 PD1 PA2 PD2 PA3 PD3

9 A AA 8 B PA 0 P D 0 PA 1 P D1 PA 2 P D 2 PA 3 P D 3 PA 4 P D4 PA 5 PD 5 PA 6 P D6 PA 7 PD 7

Unlock Bypass 3 AAA AA 555 55 AAA 20

Unlock Bypass
Program

Unlock Bypass
Reset

2XA0PAPD

2X 90X 00

Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10

Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30

Program/Erase
Suspend

Program/Erase
Resume

Read CFI
Query

1XB0

1X 30

1AA 98

Enter
Extended

3 AAA AA 555 55 AAA 88

Block

Exit Extended
Block

1. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in
hexadecimal. The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8­DQ14 and DQ15 are Don’t Care. DQ15A–1 is A–1 when BYTE is V

4 AAA AA 555 55 AAA 90 X 00

IL or DQ15 when BYTE is VIH.

28/71

M29W640FT, M29W640FB Command interface

Table 8. Program, Erase times and Program, Erase Endurance cycles

Chip Erase 80 400

Block Erase (64 KBytes) 0.8 6

Erase Suspend Latency time 50

Program (Byte or Word) 10 200

Double Byte 10 200

Double Word /Quadruple Byte Program 10 200

Quadruple Word / Octuple Byte Program 10 200

Chip Program (Byte by Byte) 80 400

Chip Program (Word by Word) 40 200

Chip Program (Double Word/Quadruple Byte Program) 20 100

Chip Program (Quadruple Word/Octuple Byte Program) 10 50

Parameter Min Typ

(1)(2)

Max

(4)

(4)

(3)

(2)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

(3)

Unit

s

s

µs

µs

µs

µs

µs

s

s

s

s

Program Suspend Latency time 4 µs

Program/Erase Cycles (per Block) 100,000 cycles

Data Retention 20 years

1. Typical values measured at room temperature and nominal voltages.

2. Sampled, but not 100% tested.

3. Maximum value measured at worst case conditions for both temperature and V

4. Maximum value measured at worst case conditions for both temperature and V

after 100,00 program/erase cycles.

CC

.

CC

29/71

Status Register M29W640FT, M29W640FB

5 Status Register

Bus Read operations from any address always read the Status Register during Program and
Erase operations. It is also read during Erase Suspend when an address within a block
being erased is accessed.

The bits in the Status Register are summarized in Table 9: Status Register Bits.

5.1 Data Polling Bit (DQ7)

The Data Polling Bit can be used to identify whether the Program/Erase Controller has
successfully completed its operation or if it has responded to an Erase Suspend. The Data
Polling Bit is output on DQ7 when the Status Register is read.

During Program operations the Data Polling Bit outputs the complement of the bit being
programmed to DQ7. After successful completion of the Program operation the memory
returns to Read mode and Bus Read operations from the address just programmed output
DQ7, not its complement.

During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state
of DQ7. After successful completion of the Erase operation the memory returns to Read
Mode.

In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation
within a block being erased. The Data Polling Bit will change from a ’0’ to a ’1’ when the
Program/Erase Controller has suspended the Erase operation.

Figure 4: Data Polling flowchart, gives an example of how to use the Data Polling Bit. A Valid

Address is the address being programmed or an address within the block being erased.

5.2 Toggle Bit (DQ6)

The Toggle Bit can be used to identify whether the Program/Erase Controller has
successfully completed its operation or if it has responded to an Erase Suspend. The Toggle
Bit is output on DQ6 when the Status Register is read.

During Program and Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations at any address. After successful completion of the
operation the memory returns to Read mode.

During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block
being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has
suspended the Erase operation.

Figure 5: Data Toggle flowchart, gives an example of how to use the Data Toggle Bit.

30/71

M29W640FT, M29W640FB Status Register

5.3 Error Bit (DQ5)

The Error Bit can be used to identify errors detected by the Program/Erase Controller. The
Error Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the
correct data to the memory. If the Error Bit is set a Read/Reset command must be issued
before other commands are issued. The Error bit is output on DQ5 when the Status Register
is read.

Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting to
do so will set DQ5 to ‘1’. A Bus Read operation to that address will show the bit is still ‘0’.
One of the Erase commands must be used to set all the bits in a block or in the whole
memory from ’0’ to ’1’.

5.4 Erase Timer Bit (DQ3)

The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation
during a Block Erase command. Once the Program/Erase Controller starts erasing the
Erase Timer Bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer Bit
is set to ’0’ and additional blocks to be erased may be written to the Command Interface.
The Erase Timer Bit is output on DQ3 when the Status Register is read.

5.5 Alternative Toggle Bit (DQ2)

The Alternative Toggle Bit can be used to monitor the Program/Erase controller during
Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is
read.

During Chip Erase and Block Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’,
etc., with successive Bus Read operations from addresses within the blocks being erased. A
protected block is treated the same as a block not being erased. Once the operation
completes the memory returns to Read mode.

During Erase Suspend the Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with
successive Bus Read operations from addresses within the blocks being erased. Bus Read
operations to addresses within blocks not being erased will output the memory cell data as if
in Read mode.

After an Erase operation that causes the Error Bit to be set the Alternative Toggle Bit can be
used to identify which block or blocks have caused the error. The Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses
within blocks that have not erased correctly. The Alternative Toggle Bit does not change if
the addressed block has erased correctly.

31/71

Status Register M29W640FT, M29W640FB

Table 9. Status Register Bits

(1)

Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB

Program Any address DQ7 Toggle 0 – – 0

Program During Erase
Suspend

Any address DQ7 Toggle 0 – – 0

Program Error Any address DQ7 Toggle 1 – – Hi-Z

Chip Erase Any address 0 Toggle 0 1 Toggle 0

Block Erase before
timeout

Erasing Block 0 Toggle 0 0 Toggle 0

Non-Erasing Block 0 Toggle 0 0 No Toggle 0

Erasing Block 0 Toggle 0 1 Toggle 0

Block Erase

Non-Erasing Block 0 Toggle 0 1 No Toggle 0

Erasing Block 1 No Toggle 0 – Toggle Hi-Z

Erase Suspend

Non-Erasing Block Data read as normal Hi-Z

Good Block address 0 Toggle 1 1 No Toggle Hi-Z

Erase Error

Faulty Block address 0 Toggle 1 1 Toggle Hi-Z

1. Unspecified data bits should be ignored.

Figure 4. Data Polling flowchart

START

READ DQ5 & DQ7

at VALID ADDRESS

DQ7

DATA

NO

DQ5

READ DQ7

at VALID ADDRESS

DQ7

DATA

FAIL PASS

=

= 1

=

YES

NO

YES

YES

NO

AI90194

32/71

M29W640FT, M29W640FB Status Register

Figure 5. Data Toggle flowchart

START

READ DQ6

READ

DQ5 & DQ6

DQ6

=

TOGGLE

YES

NO

DQ5

= 1

YES

READ DQ6

TWICE

DQ6

=

TOGGLE

YES

FAIL PASS

NO

NO

AI90195B

33/71

Maximum rating M29W640FT, M29W640FB

6 Maximum rating

Stressing the device above the rating listed in the Absolute Maximum Ratings table may
cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions
for extended periods may affect device reliability. These are stress ratings only and
operation of the device at these or any other conditions above those indicated in the
Operating sections of this specification is not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents.

Table 10. Absolute maximum ratings

Symbol Parameter Min Max Unit

T

BIAS

T

STG

V

IO

V

CC

V

ID

(3)

V

PP

1. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions.

2. Maximum voltage may overshoot to V

3. VPP must not remain at 12V for more than a total of 80hrs.

Temperature under bias –50 125 °C

Storage temperature –65 150 °C

Input or Output voltage

(1)(2)

–0.6 VCC +0.6 V

Supply voltage –0.6 4 V

Identification voltage –0.6 13.5 V

Program voltage –0.6 13.5 V

+2V during transition and for less than 20ns during transitions.

CC

34/71

M29W640FT, M29W640FB DC and AC parameters

7 DC and AC parameters

This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC Characteristic tables that
follow are derived from tests performed under the Measurement Conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.

Table 11. Operating and AC measurement conditions

M29W640FT, M29W640FB Unit

Parameter

Min Max

V

Supply voltage 2.7 3.6 V

CC

Ambient Operating Temperature –40 85 °C

Load capacitance (CL)30pF

Input Rise and Fall times 10 ns

Input Pulse voltages 0 to V

Input and Output Timing Ref. voltages V

Figure 6. AC measurement I/O waveform

V

CC

0V

Figure 7. AC measurement Load Circuit

V

PP

V

CC

DEVICE
UNDER

TEST

V

CC

CC

/2 V

CC

VCC/2

AI05557

25kΩ

V

0.1µF

0.1µF

CL includes JIG capacitance

35/71

C

25kΩ

L

AI05558

DC and AC parameters M29W640FT, M29W640FB

Table 12. Device capacitance

Symbol Parameter Test condition Min Max Unit

C

IN

C

OUT

1. Sampled only, not 100% tested.

Table 13. DC characteristics

Input capacitance VIN = 0V 6 pF

Output capacitance V

= 0V 12 pF

OUT

Symbol Parameter Test condition Min Max Unit

I

I

CC1

I

CC2

I

CC3

V

V

V

Input Leakage Current 0V ≤ VIN ≤ V

I

LI

Output Leakage Current 0V ≤ V

LO

Supply Current (Read)

Supply Current (Standby)

Supply Current
(Program/Erase)

Input Low voltage –0.5 0.8 V

IL

Input High voltage 0.7V

IH

Voltage for V

PP

Program Acceleration

PP

/WP

Controller active

E = VIL, G = VIH,

f = 6MHz

E = VCC ±0.2V,

= VCC ±0.2V

RP

Program/Erase

V

= 2.7V ±10% 11.5 12.5 V

CC

CC

≤ V

OUT

V
V

VPP/WP = V

CC

PP

IL

/WP =
or V

IH

PP

CCVCC

±1 µA

±1 µA

10 mA

100

20 mA

20 mA

+0.3 V

µA

Current for V

I

PP

Program Acceleration

V

V

V

LKO

1. Sampled only, not 100% tested.

Output Low voltage IOL = 1.8mA 0.45 V

OL

Output High voltage IOH = –100µAV

OH

Identification voltage 11.5 12.5 V

V

ID

Program/Erase Lockout

(1)

Supply voltage

PP

/WP

= 2.7V ±10% 15 mA

V

CC

–0.4 V

CC

1.8 2.3 V

36/71

M29W640FT, M29W640FB DC and AC parameters

Figure 8. Read Mode AC waveforms

tAVAV

A0-A20/
A–1

tAVQV tAXQX

E

VALID

G

DQ0-DQ7/
DQ8-DQ15

tBHQV

BYTE

tELBL/tELBH tBLQZ

Figure 9. Page Read AC waveforms

A2-A21

A0-A1

tAVQV

VALID ADDRESS

tELQV

tELQX tEHQZ

tGLQX tGHQX

tGLQV

VALID

tGHQZ

VALID

VALID VALID VALID

tEHQX

AI05559

E

G

DQ0-DQ15

tELQV tEHQX

tEHQZ

tGHQX

tGHQZ

VALID

DATA

tAVQV1tGLQV

VALID DATA

VALID DATA VALID DATA

37/71

AI11553

DC and AC parameters M29W640FT, M29W640FB

Table 14. Read AC characteristics

M29W640FT,

Symbol Alt Parameter Test condition

= VIL,

t

AVAV

t

AVQ VtACC

t

AVQ V1tPAG E

t

ELQX

t

ELQV

t

GLQX

t

GLQVtOE

t

EHQZ

t

GHQZ

t

EHQX

t

GHQX

t

AXQX

t

ELBL

t

ELBH

t

BLQZtFLQZ

t

BHQVtFHQV

1. Sampled only, not 100% tested.

(1)

(1)

(1)

(1)

t

Address Valid to Next Address Valid

RC

Address Valid to Output Valid

Address Valid to Output Valid (Page)

t

Chip Enable Low to Output Transition G = V

LZ

t

Chip Enable Low to Output Valid G = V

CE

t

Output Enable Low to Output Transition E = V

OLZ

Output Enable Low to Output Valid E = V

t

Chip Enable High to Output Hi-Z G = V

HZ

t

Output Enable High to Output Hi-Z E = V

DF

Chip Enable, Output Enable or Address

t

OH

Transition to Output Transition

t

ELFL

Chip Enable to BYTE Low or High Max 5 5 ns

t

ELFH

BYTE Low to Output Hi-Z Max 25 25 ns

BYTE High to Output Valid Max 30 30 ns

E

G = V

E

= VIL,

G = V

= VIL,

E

= V

G

IL

Max 60 70 ns

IL

Max 25 25 ns

IL

IL

Max 60 70 ns

IL

IL

Max 25 25 ns

IL

Max 25 25 ns

IL

Max 25 25 ns

IL

M29W640FB

Unit

60 70

Min 60 70 ns

Min 0 0 ns

Min 0 0 ns

Min 0 0 ns

38/71

M29W640FT, M29W640FB DC and AC parameters

Figure 10. Write AC waveforms, Write Enable controlled

tAVAV

A0-A20/
A–1

tAVWL

E

VALID

tWLAX

tWHEH

G

W

DQ0-DQ7/
DQ8-DQ15

V

CC

RB

tVCHEL

tELWL

tWLWHtGHWL

tDVWH

tWHRL

tWHGL

tWHWL

tWHDX

VALID

AI05560

39/71

DC and AC parameters M29W640FT, M29W640FB

Table 15. Write AC characteristics, Write Enable controlled

Symbol Alt Parameter

t

AVAV

t

ELWL

t

WLWH

t

DVW H

t

WHDX

t

WHEH

t

WHWL

t

AVW L

t

WLAX

t

GHWL

t

WHGL

t

WHRL

t

VCHEL

1. Sampled only, not 100% tested.

(1)

t

WC

t

CS

t

WP

t

DS

t

DH

t

CH

t

WPH

t

AS

t

AH

t

OEH

t

BUSY

t

VCSVCC

Address Valid to Next Address Valid Min 60 70 ns

Chip Enable Low to Write Enable Low Min 0 0 ns

Write Enable Low to Write Enable High Min 45 45 ns

Input Valid to Write Enable High Min 45 45 ns

Write Enable High to Input Transition Min 0 0 ns

Write Enable High to Chip Enable High Min 0 0 ns

Write Enable High to Write Enable Low Min 30 30 ns

Address Valid to Write Enable Low Min 0 0 ns

Write Enable Low to Address Transition Min 45 45 ns

Output Enable High to Write Enable Low Min 0 0 ns

Write Enable High to Output Enable Low Min 0 0 ns

Program/Erase Valid to RB Low Max 30 30 ns

High to Chip Enable Low Min 50 50 µs

M29W640FT,
M29W640FB

60 70

Unit

40/71

M29W640FT, M29W640FB DC and AC parameters

Figure 11. Write AC waveforms, Chip Enable controlled

tAVAV

A0-A20/
A–1

tAVEL

W

VALID

tELAX

tEHWH

G

E

DQ0-DQ7/
DQ8-DQ15

V

CC

RB

tWLEL

tVCHWL

tELEHtGHEL

tDVEH

VALID

tEHRL

tEHGL

tEHEL

tEHDX

AI05561

41/71

DC and AC parameters M29W640FT, M29W640FB

Table 16. Write AC characteristics, Chip Enable controlled

Symbol Alt Parameter

t

AVAV

t

WLEL

t

ELEH

t

DVEH

t

EHDX

t

EHWH

t

EHEL

t

AVEL

t

ELAX

t

GHEL

t

EHGL

t

EHRL

t

VCHWLtVCSVCC

1. Sampled only, not 100% tested.

(1)

t

WC

t

WS

t

CP

t

DS

t

DH

t

WH

t

CPH

t

AS

t

AH

t

OEH

t

BUSY

Address Valid to Next Address Valid Min 60 70 ns

Write Enable Low to Chip Enable Low Min 0 0 ns

Chip Enable Low to Chip Enable High Min 45 45 ns

Input Valid to Chip Enable High Min 45 45 ns

Chip Enable High to Input Transition Min 0 0 ns

Chip Enable High to Write Enable High Min 0 0 ns

Chip Enable High to Chip Enable Low Min 30 30 ns

Address Valid to Chip Enable Low Min 0 0 ns

Chip Enable Low to Address Transition Min 45 45 ns

Output Enable High Chip Enable Low Min 0 0 ns

Chip Enable High to Output Enable Low Min 0 0 ns

Program/Erase Valid to RB Low Max 30 30 ns

High to Write Enable Low Min 50 50 µs

M29W640FT, M29W640FB

Unit

60 70

Figure 12. Reset/Block Temporary Unprotect AC waveforms

E, G

W,

tPHWL, tPHEL, tPHGL

RB

RP

tPLPX

tPLYH

tRHWL, tRHEL, tRHGL

tPHPHH

AI02931B

42/71

M29W640FT, M29W640FB DC and AC parameters

Figure 13. Accelerated Program Timing waveforms

V

PP

VPP/WP

V

or V

IL

IH

tVHVPP

tVHVPP

AI05563

Table 17. Reset/Block Temporary Unprotect AC characteristics

Symbol Alt Parameter

(1)

t

PHWL

t

PHEL

(1)

t

PHGL

(1)

t

RHWL

(1)

t

RHEL

(1)

t

RHGL

t

PLPX

t

PLYH

(1)

t

PHPHH

(1)

t

VHVPP

1. Sampled only, not 100% tested.

t

RH

t

t

t

READY

t

VIDR

RP High to Write Enable Low, Chip Enable Low,
Output Enable Low

RB High to Write Enable Low, Chip Enable Low,

RB

Output Enable Low

RP Pulse Width Min 500 ns

RP

RP Low to Read mode Max 50 µs

RP Rise Time to V

ID

VPP Rise and Fall Time Min 250 ns

M29W640FT,
M29W640FB

Unit

Min 50 ns

Min 0 ns

Min 500 ns

43/71

Package mechanical M29W640FT, M29W640FB

8 Package mechanical

Figure 14. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, top view

package outline

1

D1

24

E1

E

DIE

1. Drawing is not to scale.

Table 18. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, package

48

e

B

25

A2

C

CP

L1

A

LA1 α

TSOP-G

mechanical data

millimeters inches

Symbol

Typ Min Max Typ Min Max

A 1.200 0.0472

A1 0.100 0.050 0.150 0.0039 0.0020 0.0059

A2 1.000 0.950 1.050 0.0394 0.0374 0.0413

B 0.220 0.170 0.270 0.0087 0.0067 0.0106

C 0.100 0.210 0.0039 0.0083

CP 0.100 0.0039

D1 12.000 11.900 12.100 0.4724 0.4685 0.4764

E 20.000 19.800 20.200 0.7874 0.7795 0.7953

E1 18.400 18.300 18.500 0.7244 0.7205 0.7283

e 0.500 – – 0.0197 – –

L 0.600 0.500 0.700 0.0236 0.0197 0.0276

L1 0.800 0.0315

α 3° 0° 5° 3° 0° 5°

44/71

M29W640FT, M29W640FB Package mechanical

Figure 15. TFBGA48 6x8mm - 6x8 active ball array, 0.8mm pitch, package outline

D

FD

FE

BALL "A1"

E1E

eb

A

1. Drawing is not to scale.

Table 19. TFBGA48 6x8mm - 6x8 active ball array, 0.8mm pitch, package

D1

SD

SE

ddd

e

A2

A1

BGA-Z32

mechanical data

millimeters inches

Symbol

Typ Min Max Typ Min Max

A 1.200 0.0472

A1 0.260 0.0102

A2 0.900 0.0354

b 0.350 0.450 0.0138 0.0177

D 6.000 5.900 6.100 0.2362 0.2323 0.2402

D1 4.000 – – 0.1575 – –

ddd 0.100 0.0039

E 8.000 7.900 8.100 0.3150 0.3110 0.3189

E1 5.600 – – 0.2205 – –

e 0.800 – – 0.0315 – –

FD 1.000 – – 0.0394 – –

FE 1.200 – – 0.0472 – –

SD 0.400 – – 0.0157 – –

SE 0.400 – – 0.0157 – –

45/71

Part numbering M29W640FT, M29W640FB

9 Part numbering

Table 20. Ordering information scheme

Example: M29W640FB 70 N 6 F

Device Type

M29

Operating Voltage

W = VCC = 2.7 to 3.6V

Device Function

640F = 64 Mbit (x8 / x16), Boot Block

Array Matrix

T = Top Boot

B = Bottom Boot

Speed

60 = 60ns

70 = 70ns

Package

N = TSOP48: 12 x 20 mm

ZA = TFBGA48: 6x8mm, 0.80 mm pitch

Temperature Range

6 = −40 to 85 °C

Option

E = ECOPACK Package, Standard Packing

F = ECOPACK Package, Tape & Reel Packing

Note: This product is also available with the Extended Block factory locked. For further details and

ordering information contact your nearest ST sales office.

Devices are shipped from the factory with the memory content bits erased to 1. For a list of
available options (Speed, Package, etc.) or for further information on any aspect of this
device, please contact your nearest ST Sales Office.

46/71

M29W640FT, M29W640FB Block addresses

Appendix A Block addresses

Table 21. Top Boot Block addresses, M29W640FT

Block KBytes/KWords Protection Block Group (x8) (x16)

0 64/32

000000h–00FFFFh

(1)

000000h–007FFFh

1 64/32 010000h–01FFFFh 008000h–00FFFFh

Protection Group

2 64/32 020000h–02FFFFh 010000h–017FFFh

3 64/32 030000h–03FFFFh 018000h–01FFFFh

4 64/32

040000h–04FFFFh 020000h–027FFFh

5 64/32 050000h–05FFFFh 028000h–02FFFFh

Protection Group

6 64/32 060000h–06FFFFh 030000h–037FFFh

7 64/32 070000h–07FFFFh 038000h–03FFFFh

8 64/32

080000h–08FFFFh 040000h–047FFFh

9 64/32 090000h–09FFFFh 048000h–04FFFFh

Protection Group

10 64/32 0A0000h–0AFFFFh 050000h–057FFFh

11 64/32 0B0000h–0BFFFFh 058000h–05FFFFh

12 64/32

0C0000h–0CFFFFh 060000h–067FFFh

13 64/32 0D0000h–0DFFFFh 068000h–06FFFFh

Protection Group

14 64/32 0E0000h–0EFFFFh 070000h–077FFFh

(1)

15 64/32 0F0000h–0FFFFFh 078000h–07FFFFh

16 64/32

100000h–10FFFFh 080000h–087FFFh

17 64/32 110000h–11FFFFh 088000h–08FFFFh

Protection Group

18 64/32 120000h–12FFFFh 090000h–097FFFh

19 64/32 130000h–13FFFFh 098000h–09FFFFh

20 64/32

140000h–14FFFFh 0A0000h–0A7FFFh

21 64/32 150000h–15FFFFh 0A8000h–0AFFFFh

Protection Group

22 64/32 160000h–16FFFFh 0B0000h–0B7FFFh

23 64/32 170000h–17FFFFh 0B8000h–0BFFFFh

24 64/32

180000h–18FFFFh 0C0000h–0C7FFFh

25 64/32 190000h–19FFFFh 0C8000h–0CFFFFh

Protection Group

26 64/32 1A0000h–1AFFFFh 0D0000h–0D7FFFh

27 64/32 1B0000h–1BFFFFh 0D8000h–0DFFFFh

28 64/32

1C0000h–1CFFFFh 0E0000h–0E7FFFh

29 64/32 1D0000h–1DFFFFh 0E8000h–0EFFFFh

Protection Group

30 64/32 1E0000h–1EFFFFh 0F0000h–0F7FFFh

31 64/32 1F0000h–1FFFFFh 0F8000h–0FFFFFh

47/71

Block addresses M29W640FT, M29W640FB

Table 21. Top Boot Block addresses, M29W640FT (continued)

Block KBytes/KWords Protection Block Group (x8) (x16)

32 64/32

33 64/32 210000h–21FFFFh 108000h–10FFFFh

Protection Group

34 64/32 220000h–22FFFFh 110000h–117FFFh

35 64/32 230000h–23FFFFh 118000h–11FFFFh

36 64/32

37 64/32 250000h–25FFFFh 128000h–12FFFFh

Protection Group

38 64/32 260000h–26FFFFh 130000h–137FFFh

39 64/32 270000h–27FFFFh 138000h–13FFFFh

40 64/32

41 64/32 290000h–29FFFFh 148000h–14FFFFh

Protection Group

42 64/32 2A0000h–2AFFFFh 150000h–157FFFh

43 64/32 2B0000h–2BFFFFh 158000h–15FFFFh

44 64/32

45 64/32 2D0000h–2DFFFFh 168000h–16FFFFh

Protection Group

46 64/32 2E0000h–2EFFFFh 170000h–177FFFh

47 64/32 2F0000h–2FFFFFh 178000h–17FFFFh

48 64/32

49 64/32 310000h–31FFFFh 188000h–18FFFFh

Protection Group

50 64/32 320000h–32FFFFh 190000h–197FFFh

51 64/32 330000h–33FFFFh 198000h–19FFFFh

52 64/32

200000h–20FFFFh 100000h–107FFFh

240000h–24FFFFh 120000h–127FFFh

280000h–28FFFFh 140000h–147FFFh

2C0000h–2CFFFFh 160000h–167FFFh

300000h–30FFFFh 180000h–187FFFh

340000h–34FFFFh 1A0000h–1A7FFFh

53 64/32 350000h–35FFFFh 1A8000h–1AFFFFh

54 64/32 360000h–36FFFFh 1B0000h–1B7FFFh

55 64/32 370000h–37FFFFh 1B8000h–1BFFFFh

56 64/32

57 64/32 390000h–39FFFFh 1C8000h–1CFFFFh

58 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh

59 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh

60 64/32

61 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh

62 64/32 3E0000h–3EFFFFh 1F0000h–1F7FFFh

63 64/32 3F0000h–3FFFFFh 1F8000h–1FFFFFh

48/71

Protection Group

380000h–38FFFFh 1C0000h–1C7FFFh

Protection Group

3C0000h–3CFFFFh 1E0000h–1E7FFFh

Protection Group

M29W640FT, M29W640FB Block addresses

Table 21. Top Boot Block addresses, M29W640FT (continued)

Block KBytes/KWords Protection Block Group (x8) (x16)

64 64/32

65 64/32 410000h–41FFFFh 208000h–20FFFFh

Protection Group

66 64/32 420000h–42FFFFh 210000h–217FFFh

67 64/32 430000h–43FFFFh 218000h–21FFFFh

68 64/32

69 64/32 450000h–45FFFFh 228000h–22FFFFh

Protection Group

70 64/32 460000h–46FFFFh 230000h–237FFFh

71 64/32 470000h–47FFFFh 238000h–23FFFFh

72 64/32

73 64/32 490000h–49FFFFh 248000h–24FFFFh

Protection Group

74 64/32 4A0000h–4AFFFFh 250000h–257FFFh

75 64/32 4B0000h–4BFFFFh 258000h–25FFFFh

76 64/32

77 64/32 4D0000h–4DFFFFh 268000h–26FFFFh

Protection Group

78 64/32 4E0000h–4EFFFFh 270000h–277FFFh

79 64/32 4F0000h–4FFFFFh 278000h–27FFFFh

80 64/32

81 64/32 510000h–51FFFFh 288000h–28FFFFh

Protection Group

82 64/32 520000h–52FFFFh 290000h–297FFFh

83 64/32 530000h–53FFFFh 298000h–29FFFFh

84 64/32

400000h–40FFFFh 200000h–207FFFh

440000h–44FFFFh 220000h–227FFFh

480000h–48FFFFh 240000h–247FFFh

4C0000h–4CFFFFh 260000h–267FFFh

500000h–50FFFFh 280000h–287FFFh

540000h–54FFFFh 2A0000h–2A7FFFh

85 64/32 550000h–55FFFFh 2A8000h–2AFFFFh

86 64/32 560000h–56FFFFh 2B0000h–2B7FFFh

87 64/32 570000h–57FFFFh 2B8000h–2BFFFFh

88 64/32

89 64/32 590000h–59FFFFh 2C8000h–2CFFFFh

90 64/32 5A0000h–5AFFFFh 2D0000h–2D7FFFh

91 64/32 5B0000h–5BFFFFh 2D8000h–2DFFFFh

92 64/32

93 64/32 5D0000h–5DFFFFh 2E8000h–2EFFFFh

94 64/32 5E0000h–5EFFFFh 2F0000h–2F7FFFh

95 64/32 5F0000h–5FFFFFh 2F8000h–2FFFFFh

Protection Group

580000h–58FFFFh 2C0000h–2C7FFFh

Protection Group

5C0000h–5CFFFFh 2E0000h–2E7FFFh

Protection Group

49/71

Block addresses M29W640FT, M29W640FB

Table 21. Top Boot Block addresses, M29W640FT (continued)

Block KBytes/KWords Protection Block Group (x8) (x16)

96 64/32

97 64/32 610000h–61FFFFh 308000h–30FFFFh

Protection Group

98 64/32 620000h–62FFFFh 310000h–317FFFh

99 64/32 630000h–63FFFFh 318000h–31FFFFh

100 64/32

101 64/32 650000h–65FFFFh 328000h–32FFFFh

Protection Group

102 64/32 660000h–66FFFFh 330000h–337FFFh

103 64/32 670000h–67FFFFh 338000h–33FFFFh

104 64/32

105 64/32 690000h–69FFFFh 348000h–34FFFFh

Protection Group

106 64/32 6A0000h–6AFFFFh 350000h–357FFFh

107 64/32 6B0000h–6BFFFFh 358000h–35FFFFh

108 64/32

109 64/32 6D0000h–6DFFFFh 368000h–36FFFFh

Protection Group

110 64/32 6E0000h–6EFFFFh 370000h–377FFFh

111 64/32 6F0000h–6FFFFFh 378000h–37FFFFh

112 64/32

113 64/32 710000h–71FFFFh 388000h–38FFFFh

Protection Group

114 64/32 720000h–72FFFFh 390000h–397FFFh

115 64/32 730000h–73FFFFh 398000h–39FFFFh

116 64/32

600000h–60FFFFh 300000h–307FFFh

640000h–64FFFFh 320000h–327FFFh

680000h–68FFFFh 340000h–347FFFh

6C0000h–6CFFFFh 360000h–367FFFh

700000h–70FFFFh 380000h–387FFFh

740000h–74FFFFh 3A0000h–3A7FFFh

117 64/32 750000h–75FFFFh 3A8000h–3AFFFFh

118 64/32 760000h–76FFFFh 3B0000h–3B7FFFh

119 64/32 770000h–77FFFFh 3B8000h–3BFFFFh

120 64/32

121 64/32 790000h–79FFFFh 3C8000h–3CFFFFh

122 64/32 7A0000h–7AFFFFh 3D0000h–3D7FFFh

123 64/32 7B0000h–7BFFFFh 3D8000h–3DFFFFh

50/71

Protection Group

780000h–78FFFFh 3C0000h–3C7FFFh

Protection Group

M29W640FT, M29W640FB Block addresses

Table 21. Top Boot Block addresses, M29W640FT (continued)

Block KBytes/KWords Protection Block Group (x8) (x16)

124 64/32

125 64/32 7D0000h–7DFFFFh 3E8000h–3EFFFFh

126 64/32 7E0000h–7EFFFFh 3F0000h–3F7FFFh

127 8/4 7F0000h–7F1FFFh 3F8000h–3F8FFFh

128 8/4 7F2000h–7F3FFFh 3F9000h–3F9FFFh

129 8/4 7F4000h–7F5FFFh 3FA000h–3FAFFFh

130 8/4 7F6000h–7F7FFFh 3FB000h–3FBFFFh

131 8/4 7F8000h–7F9FFFh 3FC000h–3FCFFFh

132 8/4 7FA000h–7FBFFFh 3FD000h–3FDFFFh

133 8/4 7FC000h–7FDFFFh 3FE000h–3FEFFFh

134 8/4 7FE000h–7FFFFFh 3FF000h–3FFFFFh

1. Used as the Extended Block addresses in Extended Block mode.

Protection Group

7C0000h–7CFFFFh 3E0000h–3E7FFFh

51/71

Block addresses M29W640FT, M29W640FB

Table 22. Bottom Boot Block addresses, M29W640FB

Block KBytes/KWords Protection Block Group (x8) (x16)

08/4

000000h-001FFFh

(1)

000000h–000FFFh

1 8/4 002000h-003FFFh 001000h–001FFFh

2 8/4 004000h-005FFFh 002000h–002FFFh

3 8/4 006000h-007FFFh 003000h–003FFFh

4 8/4 008000h-009FFFh 004000h–004FFFh

5 8/4 00A000h-00BFFFh 005000h–005FFFh

Protection Group

6 8/4 00C000h-00DFFFh 006000h–006FFFh

7 8/4 00E000h-00FFFFh 007000h–007FFFh

8 64/32 010000h-01FFFFh 008000h–00FFFFh

9 64/32 020000h-02FFFFh 010000h–017FFFh

10 64/32 030000h-03FFFFh 018000h–01FFFFh

11 64/32

040000h-04FFFFh 020000h–027FFFh

12 64/32 050000h-05FFFFh 028000h–02FFFFh

Protection Group

13 64/32 060000h-06FFFFh 030000h–037FFFh

14 64/32 070000h-07FFFFh 038000h–03FFFFh

15 64/32

080000h-08FFFFh 040000h–047FFFh

16 64/32 090000h-09FFFFh 048000h–04FFFFh

Protection Group

17 64/32 0A0000h-0AFFFFh 050000h–057FFFh

18 64/32 0B0000h-0BFFFFh 058000h–05FFFFh

19 64/32

0C0000h-0CFFFFh 060000h–067FFFh

(1)

20 64/32 0D0000h-0DFFFFh 068000h–06FFFFh

Protection Group

21 64/32 0E0000h-0EFFFFh 070000h–077FFFh

22 64/32 0F0000h-0FFFFFh 078000h–07FFFFh

23 64/32

100000h-10FFFFh 080000h–087FFFh

24 64/32 110000h-11FFFFh 088000h–08FFFFh

Protection Group

25 64/32 120000h-12FFFFh 090000h–097FFFh

26 64/32 130000h-13FFFFh 098000h–09FFFFh

27 64/32

140000h-14FFFFh 0A0000h–0A7FFFh

28 64/32 150000h-15FFFFh 0A8000h–0AFFFFh

Protection Group

29 64/32 160000h-16FFFFh 0B0000h–0B7FFFh

30 64/32 170000h-17FFFFh 0B8000h–0BFFFFh

31 64/32

180000h-18FFFFh 0C0000h–0C7FFFh

32 64/32 190000h-19FFFFh 0C8000h–0CFFFFh

Protection Group

33 64/32 1A0000h-1AFFFFh 0D0000h–0D7FFFh

34 64/32 1B0000h-1BFFFFh 0D8000h–0DFFFFh

52/71

M29W640FT, M29W640FB Block addresses

Table 22. Bottom Boot Block addresses, M29W640FB (continued)

Block KBytes/KWords Protection Block Group (x8) (x16)

35 64/32

36 64/32 1D0000h-1DFFFFh 0E8000h–0EFFFFh

Protection Group

37 64/32 1E0000h-1EFFFFh 0F0000h–0F7FFFh

38 64/32 1F0000h-1FFFFFh 0F8000h–0FFFFFh

39 64/32

40 64/32 210000h-21FFFFh 108000h–10FFFFh

Protection Group

41 64/32 220000h-22FFFFh 110000h–117FFFh

42 64/32 230000h-23FFFFh 118000h–11FFFFh

43 64/32

44 64/32 250000h-25FFFFh 128000h–12FFFFh

Protection Group

45 64/32 260000h-26FFFFh 130000h–137FFFh

46 64/32 270000h-27FFFFh 138000h–13FFFFh

47 64/32

48 64/32 290000h-29FFFFh 148000h–14FFFFh

Protection Group

49 64/32 2A0000h-2AFFFFh 150000h–157FFFh

50 64/32 2B0000h-2BFFFFh 158000h–15FFFFh

51 64/32

52 64/32 2D0000h-2DFFFFh 168000h–16FFFFh

Protection Group

53 64/32 2E0000h-2EFFFFh 170000h–177FFFh

54 64/32 2F0000h-2FFFFFh 178000h–17FFFFh

55 64/32

1C0000h-1CFFFFh 0E0000h–0E7FFFh

200000h-20FFFFh 100000h–107FFFh

240000h-24FFFFh 120000h–127FFFh

280000h-28FFFFh 140000h–147FFFh

2C0000h-2CFFFFh 160000h–167FFFh

300000h-30FFFFh 180000h–187FFFh

56 64/32 310000h-31FFFFh 188000h–18FFFFh

57 64/32 320000h-32FFFFh 190000h–197FFFh

58 64/32 330000h-33FFFFh 198000h–19FFFFh

59 64/32

60 64/32 350000h-35FFFFh 1A8000h–1AFFFFh

61 64/32 360000h-36FFFFh 1B0000h–1B7FFFh

62 64/32 370000h-37FFFFh 1B8000h–1BFFFFh

63 64/32

64 64/32 390000h-39FFFFh 1C8000h–1CFFFFh

65 64/32 3A0000h-3AFFFFh 1D0000h–1D7FFFh

66 64/32 3B0000h-3BFFFFh 1D8000h–1DFFFFh

Protection Group

340000h-34FFFFh 1A0000h–1A7FFFh

Protection Group

380000h-38FFFFh 1C0000h–1C7FFFh

Protection Group

53/71

Block addresses M29W640FT, M29W640FB

Table 22. Bottom Boot Block addresses, M29W640FB (continued)

Block KBytes/KWords Protection Block Group (x8) (x16)

67 64/32

68 64/32 3D0000h-3DFFFFh 1E8000h–1EFFFFh

Protection Group

69 64/32 3E0000h-3EFFFFh 1F0000h–1F7FFFh

70 64/32 3F0000h-3FFFFFh 1F8000h–1FFFFFh

71 64/32

72 64/32 410000h-41FFFFh 208000h–20FFFFh

Protection Group

73 64/32 420000h-42FFFFh 210000h–217FFFh

74 64/32 430000h-43FFFFh 218000h–21FFFFh

75 64/32

76 64/32 450000h-45FFFFh 228000h–22FFFFh

Protection Group

77 64/32 460000h-46FFFFh 230000h–237FFFh

78 64/32 470000h-47FFFFh 238000h–23FFFFh

79 64/32

80 64/32 490000h-49FFFFh 248000h–24FFFFh

Protection Group

81 64/32 4A0000h-4AFFFFh 250000h–257FFFh

82 64/32 4B0000h-4BFFFFh 258000h–25FFFFh

83 64/32

84 64/32 4D0000h-4DFFFFh 268000h–26FFFFh

Protection Group

85 64/32 4E0000h-4EFFFFh 270000h–277FFFh

86 64/32 4F0000h-4FFFFFh 278000h–27FFFFh

87 64/32

3C0000h-3CFFFFh 1E0000h–1E7FFFh

400000h-40FFFFh 200000h–207FFFh

440000h-44FFFFh 220000h–227FFFh

480000h-48FFFFh 240000h–247FFFh

4C0000h-4CFFFFh 260000h–267FFFh

500000h-50FFFFh 280000h–287FFFh

88 64/32 510000h-51FFFFh 288000h–28FFFFh

89 64/32 520000h-52FFFFh 290000h–297FFFh

90 64/32 530000h-53FFFFh 298000h–29FFFFh

91 64/32

92 64/32 550000h-55FFFFh 2A8000h–2AFFFFh

93 64/32 560000h-56FFFFh 2B0000h–2B7FFFh

94 64/32 570000h-57FFFFh 2B8000h–2BFFFFh

95 64/32

96 64/32 590000h-59FFFFh 2C8000h–2CFFFFh

97 64/32 5A0000h-5AFFFFh 2D0000h–2D7FFFh

98 64/32 5B0000h-5BFFFFh 2D8000h–2DFFFFh

54/71

Protection Group

540000h-54FFFFh 2A0000h–2A7FFFh

Protection Group

580000h-58FFFFh 2C0000h–2C7FFFh

Protection Group

M29W640FT, M29W640FB Block addresses

Table 22. Bottom Boot Block addresses, M29W640FB (continued)

Block KBytes/KWords Protection Block Group (x8) (x16)

99 64/32

100 64/32 5D0000h-5DFFFFh 2E8000h–2EFFFFh

Protection Group

101 64/32 5E0000h-5EFFFFh 2F0000h–2F7FFFh

102 64/32 5F0000h-5FFFFFh 2F8000h–2FFFFFh

103 64/32

104 64/32 610000h-61FFFFh 308000h–30FFFFh

Protection Group

105 64/32 620000h-62FFFFh 310000h–317FFFh

106 64/32 630000h-63FFFFh 318000h–31FFFFh

107 64/32

108 64/32 650000h-65FFFFh 328000h–32FFFFh

Protection Group

109 64/32 660000h-66FFFFh 330000h–337FFFh

110 64/32 670000h-67FFFFh 338000h–33FFFFh

111 64/32

112 64/32 690000h-69FFFFh 348000h–34FFFFh

Protection Group

113 64/32 6A0000h-6AFFFFh 350000h–357FFFh

114 64/32 6B0000h-6BFFFFh 358000h–35FFFFh

115 64/32

116 64/32 6D0000h-6DFFFFh 368000h–36FFFFh

Protection Group

117 64/32 6E0000h-6EFFFFh 370000h–377FFFh

118 64/32 6F0000h-6FFFFFh 378000h–37FFFFh

119 64/32

5C0000h-5CFFFFh 2E0000h–2E7FFFh

600000h-60FFFFh 300000h–307FFFh

640000h-64FFFFh 320000h–327FFFh

680000h-68FFFFh 340000h–347FFFh

6C0000h-6CFFFFh 360000h–367FFFh

700000h-70FFFFh 380000h–387FFFh

120 64/32 710000h-71FFFFh 388000h–38FFFFh

121 64/32 720000h-72FFFFh 390000h–397FFFh

122 64/32 730000h-73FFFFh 398000h–39FFFFh

123 64/32

124 64/32 750000h-75FFFFh 3A8000h–3AFFFFh

125 64/32 760000h-76FFFFh 3B0000h–3B7FFFh

126 64/32 770000h-77FFFFh 3B8000h–3BFFFFh

127 64/32

128 64/32 790000h-79FFFFh 3C8000h–3CFFFFh

129 64/32 7A0000h-7AFFFFh 3D0000h–3D7FFFh

130 64/32 7B0000h-7BFFFFh 3D8000h–3DFFFFh

Protection Group

740000h-74FFFFh 3A0000h–3A7FFFh

Protection Group

780000h-78FFFFh 3C0000h–3C7FFFh

Protection Group

55/71

Block addresses M29W640FT, M29W640FB

Table 22. Bottom Boot Block addresses, M29W640FB (continued)

Block KBytes/KWords Protection Block Group (x8) (x16)

131 64/32

132 64/32 7D0000h-7DFFFFh 3E8000h–3EFFFFh

Protection Group

133 64/32 7E0000h-7EFFFFh 3F0000h–3F7FFFh

134 64/32 7F0000h-7FFFFFh 3F8000h–3FFFFFh

1. Used as the Extended Block addresses in Extended Block mode.

7C0000h-7CFFFFh 3E0000h–3E7FFFh

56/71

M29W640FT, M29W640FB Common Flash Interface (CFI)

Appendix B Common Flash Interface (CFI)

The Common Flash Interface is a JEDEC approved, standardized data structure that can be
read from the Flash memory device. It allows a system software to query the device to
determine various electrical and timing parameters, density information and functions
supported by the memory. The system can interface easily with the device, enabling the
software to upgrade itself when necessary.

When the CFI Query Command is issued the device enters CFI Query mode and the data
structure is read from the memory. Tables 23, 24, 25, 26, 27, and 28, show the addresses
used to retrieve the data.

The CFI data structure also contains a security area where a 64 bit unique security number
is written (see Table 28: Security Code Area). This area can be accessed only in Read
mode by the final user. It is impossible to change the security number after it has been
written by ST.

Table 23. Query structure overview

Address

Sub-section name Description

x16 x8

(1)

10h 20h CFI Query Identification String Command set ID and algorithm data offset

1Bh 36h System Interface Information Device timing & voltage information

27h 4Eh Device Geometry Definition Flash device layout

40h 80h

61h C2h Security Code Area 64 bit unique device number

1. Query data are always presented on the lowest order data outputs.

Primary Algorithm-specific Extended
Query table

Additional information specific to the
Primary Algorithm (optional)

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Common Flash Interface (CFI) M29W640FT, M29W640FB

Table 24. CFI Query Identification String

(1)

Address

Data Description Value

x16 x8

10h 20h 0051h “Q”

11h 22h 0052h Query Unique ASCII String "QRY" "R"

12h 24h 0059h "Y"

13h 26h 0002h

14h 28h 0000h

15h 2Ah 0040h

16h 2Ch 0000h

17h 2Eh 0000h

18h 30h 0000h

Primary Algorithm Command Set and Control Interface ID code
16 bit ID code defining a specific algorithm

Address for Primary Algorithm extended Query table (see

Ta bl e 2 7 )

Alternate Vendor Command Set and Control Interface ID Code
second vendor - specified algorithm supported

AMD

Compatible

P = 40h

NA

19h 32h 0000h

Address for Alternate Algorithm extended Query table NA

1Ah 34h 0000h

1. Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

Table 25. CFI Query System Interface Information

Address

Data Description Value

x16 x8

V

Logic Supply Minimum Program/Erase voltage

CC

1Bh 36h 0027h

bit 7 to 4BCD value in volts

2.7V

bit 3 to 0BCD value in 100 mV

VCC Logic Supply Maximum Program/Erase voltage

1Ch 38h 0036h

bit 7 to 4BCD value in volts

3.6V

bit 3 to 0BCD value in 100 mV

V

[Programming] Supply Minimum Program/Erase voltage

PP

1Dh 3Ah 00B5h

bit 7 to 4HEX value in volts

11.5V

bit 3 to 0BCD value in 100 mV

V

[Programming] Supply Maximum Program/Erase voltage

PP

1Eh 3Ch 00C5h

bit 7 to 4HEX value in volts

12.5V

bit 3 to 0BCD value in 100 mV

1Fh 3Eh 0004h Typical timeout per single byte/word program = 2n µs 16µs

n

20h 40h 0000h Typical timeout for minimum size write buffer program = 2

n

21h 42h 000Ah Typical timeout per individual Block Erase = 2

n

22h 44h 0000h Typical timeout for full Chip Erase = 2

ms NA

23h 46h 0004h Maximum timeout for byte/word program = 2

24h 48h 0000h Maximum timeout for write buffer program = 2

25h 4Ah 0003h Maximum timeout per individual Block Erase = 2

n

26h 4Ch 0000h Maximum timeout for Chip Erase = 2

times typical NA

ms 1s

n

times typical 256µs

n

times typical NA

n

times typical 8s

µs NA

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M29W640FT, M29W640FB Common Flash Interface (CFI)

Table 26. Device Geometry Definition

Address

Data Description Value

x16 x8

n

27h 4Eh 0017h Device Size = 2

28h
29h

2Ah
2Bh

2Ch 58h 0002h

2Dh
2Eh

2Fh

30h

31h
32h

33h
34h

35h
36h
37h
38h

39h
3Ah
3Bh
3Ch

50h
52h

54h
56h

5Ah

5Ch

5Eh
60h

62h
64h

66h
68h

6Ah

6Ch

6Eh
70h

72h
74h
76h
78h

0002h
0000h

0004h
0000h

0007h
0000h

0020h
0000h

007Eh
0000h

0000h
0001h

0000h
0000h
0000h
0000h

0000h
0000h
0000h
0000h

Flash Device Interface Code description

Maximum number of bytes in multi-byte program or page = 2

Number of Erase Block Regions. It specifies the number of
regions containing contiguous Erase Blocks of the same size.

Region 1 Information
Number of Erase Blocks of identical size = 0007h+1

Region 1 Information
Block size in Region 1 = 0020h * 256 byte

Region 2 Information
Number of Erase Blocks of identical size= 007Eh+1

Region 2 Information
Block size in Region 2 = 0100h * 256 byte

Region 3 Information
Number of Erase Blocks of identical size=007Fh+1
Region 3 Information
Block size in Region 3 = 0000h * 256 byte

Region 4 Information
Number of Erase Blocks of Identical size=007Fh+1
Region 4 Information
Block size in Region 4 = 0000h * 256 byte

in number of bytes 8 MByte

(1)

x8, x16
Async.

n

16 Bytes

2

8

8Kbyte

127

64Kbyte

0

0

0

0

1. For Bottom Boot devices, Erase Block Region 1 is located from address 000000h to 007FFFh and Erase
Block Region 2 from address 008000h to 3FFFFFh.
For Top Boot devices, Erase Block Region 1 is located from address 000000h to 3F7FFFh and Erase
Block Region 2 from address 3F8000h to 3FFFFFh.

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Common Flash Interface (CFI) M29W640FT, M29W640FB

Table 27. Primary Algorithm-specific Extended Query table

Address

Data Description Value

x16 x8

40h 80h 0050h

41h 82h 0052h "R"

Primary Algorithm extended Query table unique ASCII string
“PRI”

"P"

42h 84h 0049h "I"

43h 86h 0031h Major version number, ASCII “1”

44h 88h 0033h Minor version number, ASCII "3"

Address Sensitive Unlock (bits 1 to 0)

45h 8Ah 0000h

00h = required, 01h = not required

Ye s

Silicon Revision Number (bits 7 to 2)

46h 8Ch 0002h

47h 8Eh 0004h

48h 90h 0001h

49h 92h 0004h

Erase Suspend
00h = not supported, 01h = Read only, 02 = Read and Write

Block Protection
00h = not supported, x = number of blocks per protection group

Temporary Block Unprotect
00h = not supported, 01h = supported

Block Protect /Unprotect
04 = M29W640F

2

4

Ye s

04

4Ah 94h 0000h Simultaneous Operations, 00h = not supported No

4Bh 96h 0000h Burst Mode: 00h = not supported, 01h = supported No

4Ch 98h 0001h

Page Mode: 00h = not supported, 01h = 4 page word, 02h = 8
page word

Ye s

V

Supply Minimum Program/Erase voltage

PP

4Dh 9Ah 00B5h

bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV

V

Supply Maximum Program/Erase voltage

PP

4Eh 9Ch 00C5h

bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV

Top/Bottom Boot Block Flag

4Fh 9Eh 0002h

0003h

02h = Bottom Boot device
03h = Top Boot device

Program Suspend

50h A0h 0001h

00h = Not Supported
01h = Supported

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11.5V

12.5V

–

Suppor

ted

M29W640FT, M29W640FB Common Flash Interface (CFI)

Table 28. Security Code Area

Address

Data Description

x16 x8

61h C3h, C2h XXXX

62h C5h, C4h XXXX

63h C7h, C6h XXXX

64h C9h, C8h XXXX

64 bit: unique device number

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Extended Memory Block M29W640FT, M29W640FB

Appendix C Extended Memory Block

The M29W640F has an extra block, the Extended Block, that can be accessed using a
dedicated command.

This Extended Block is 128 Words in x16 mode and 256 Bytes in x8 mode. It is used as a
security block to provide a permanent security identification number) or to store additional
information.

The Extended Block is either Factory Locked or Customer Lockable, its status is indicated
by bit DQ7. This bit is permanently set to either ‘1’ or ‘0’ at the factory and cannot be
changed. When set to ‘1’, it indicates that the device is factory locked and the Extended
Block is protected. When set to ‘0’, it indicates that the device is customer lockable and the
Extended Block is unprotected. Bit DQ7 being permanently locked to either ‘1’ or ‘0’ is
another security feature which ensures that a customer lockable device cannot be used
instead of a factory locked one.

Bit DQ7 is the most significant bit in the Extended Block Verify Code and a specific
procedure must be followed to read it. See “Extended Memory Block Verify Code

Bus operations, BYTE = V

read bit DQ7.

The Extended Block can only be accessed when the device is in Extended Block mode. For
details of how the Extended Block mode is entered and exited, refer to the Section 4.3.1:

Enter Extended Block command and Section 4.3.2: Exit Extended Block command, and to
Ta bl e 6 and Table 7: Commands, 8-bit mode, BYTE = V

and Table 5: Bus operations, BYTE = VIH, for details of how to

IL

.

IL

” in Ta bl e 4 :

C.1 Factory Locked Extended Block

In devices where the Extended Block is factory locked, the Security Identification Number is
written to the Extended Block address space (see Table 29: Extended Block address and

data) in the factory. The DQ7 bit is set to ‘1’ and the Extended Block cannot be unprotected.

C.2 Customer Lockable Extended Block

A device where the Extended Block is customer lockable is delivered with the DQ7 bit set to
‘0’ and the Extended Block unprotected. It is up to the customer to program and protect the
Extended Block but care must be taken because the protection of the Extended Block is not
reversible.

There are two ways of protecting the Extended Block:

● Issue the Enter Extended Block command to place the device in Extended Block mode,

then use the In-System Technique with RP

Section D.2: In-System technique and to the corresponding flowcharts, Figure 18 and
Figure 19, for a detailed explanation of the technique).

● Issue the Enter Extended Block command to place the device in Extended Block mode,

then use the Programmer Technique (refer to Appendix D, Section D.1: Programmer

technique and to the corresponding flowcharts, Figure 16 and Figure 17, for a detailed

explanation of the technique).

Once the Extended Block is programmed and protected, the Exit Extended Block command
must be issued to exit the Extended Block mode and return the device to Read mode.

either at VIH or at V

(refer to Appendix D,

ID

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M29W640FT, M29W640FB Extended Memory Block

Table 29. Extended Block address and data

Address Data

x8 x16 Factory Locked Customer Lockable

000000h-00007Fh 000000h-00003Fh Security Identification Number

000080h-0000FFh 000040h-00007Fh Unavailable

Determined by

customer

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Block protection M29W640FT, M29W640FB

Appendix D Block protection

Block protection can be used to prevent any operation from modifying the data stored in the
memory. The blocks are protected in groups, refer to Appendix A: Block addresses, Ta b le 2 1
and Ta bl e 2 2 for details of the Protection Groups. Once protected, Program and Erase
operations within the protected group fail to change the data.

There are three techniques that can be used to control Block Protection, these are the
Programmer technique, the In-System technique and Temporary Unprotection. Temporary
Unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP
described in the Signal Descriptions section.

D.1 Programmer technique

The Programmer technique uses high (VID) voltage levels on some of the bus pins. These
cannot be achieved using a standard microprocessor bus, therefore the technique is
recommended only for use in Programming Equipment.

To protect a group of blocks follow the flowchart in Figure 16: Programmer Equipment Group

Protect flowchart. To unprotect the whole chip it is necessary to protect all of the groups first,

then all groups can be unprotected at the same time. To unprotect the chip follow Figure 17:

Programmer Equipment Chip Unprotect flowchart. Table 30: Programmer technique bus
operations, BYTE = V

The timing on these flowcharts is critical. Care should be taken to ensure that, where a
pause is specified, it is followed as closely as possible. Do not abort the procedure before
reaching the end. Chip Unprotect can take several seconds and a user message should be
provided to show that the operation is progressing.

or VIL, gives a summary of each operation.

IH

; this is

D.2 In-System technique

The In-System technique requires a high voltage level on the Reset/Blocks Temporary
Unprotect pin, RP
components on the microprocessor bus, therefore this technique is suitable for use after the
memory has been fitted to the system.

To protect a group of blocks follow the flowchart in Figure 18: In-System Equipment Group

Protect flowchart. To unprotect the whole chip it is necessary to protect all of the groups first,

then all the groups can be unprotected at the same time. To unprotect the chip follow

Figure 19: In-System Equipment Chip Unprotect flowchart.

The timing on these flowcharts is critical. Care should be taken to ensure that, where a
pause is specified, it is followed as closely as possible. Do not allow the microprocessor to
service interrupts that will upset the timing and do not abort the procedure before reaching
the end. Chip Unprotect can take several seconds and a user message should be provided
to show that the operation is progressing.

Note: RP

64/71

can be either at V

Extended Block.

(1)

. This can be achieved without violating the maximum ratings of the

or at V

IH

when using the In-System Technique to protect the

ID

M29W640FT, M29W640FB Block protection

(1)

Address Inputs

A0-A21

VILVIDVIL Pulse

IDVIDVIL

Pulse

A9 = VID, A12-A21 = Block address

Others = X

A9 = V

, A12 = VIH, A15 = VIH

ID

Others = X

A0, A2, A3 = VIL, A1 = VIH, A6 = VIL,

V

ILVIL

V

IH

A9 = VID, A12-A21 = Block address

Others = X

A0, A2, A3 = VIL, A1 = VIH, A6 = VIH,

V

ILVIL

V

IH

A9 = VID, A12-A21 = Block address

Others = X

Table 30. Programmer technique bus operations, BYTE = VIH or VIL

Operation E G W

Block (Group)
Protect

Chip Unprotect V

Block (Group)
Protection Verify

Block (Group)
Unprotection Verify

1. Block Protection Groups are shown in Appendix A, Tables 21 and 22.

Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

X

X

Pass = XX01h

Retry = XX00h

Retry = XX01h

Pass = XX00h

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Block protection M29W640FT, M29W640FB

Figure 16. Programmer Equipment Group Protect flowchart

START

ADDRESS = GROUP ADDRESS

W = V

IH

n = 0

G, A9 = VID,

E = V

IL

Wait 4µs

W = V

IL

Wait 100µs

W = V

IH

Verify Protect Set-upEnd

E, G = VIH,

A0, A2, A3 = VIL, A1 =VIH,

A6 =V

A9 = VID, Others = X

IL,

E = V

IL

Wait 4µs

G = V

IL

Wait 60ns

Read DATA

DATA

=

01h

YES

A9 = V

IH

E, G = V

IH

PASS

NO

++n

= 25

A9 = V

E, G = V

NO

YES

IH

IH

1. Block Protection Groups are shown in Appendix A, Tables 21 and 22.

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FAIL

AI11555

M29W640FT, M29W640FB Block protection

Figure 17. Programmer Equipment Chip Unprotect flowchart

START

PROTECT ALL GROUPS

CURRENT GROUP = 0

ADDRESS = CURRENT GROUP ADDRESS

A0, A2, A3 = VIL, A1 =VIH,

A6 =V

n = 0

A6, A12, A15 = V

E, G, A9 = V

Wait 4µs

W = V

IL

Wait 10ms

W = V

IH

E, G = V

IH

A9 = VID, Others = X

IH,

E = V

IL

Wait 4µs

(1)

IH

ID

G = V

IL

Wait 60ns

Verify Unprotect Set-upEnd

++n

NO

= 1000

YES

A9 = V

IH

E, G = V

IH

FAIL PASS

Read DATA

DATA

=

00h

YESNO

1. Block Protection Groups are shown in Appendix A, Tables 21 and 22.

67/71

CURRENT GROUP

LAST

GROUP

YES

A9 = V

IH

E, G = V

IH

INCREMENT

NO

AI11556b

Block protection M29W640FT, M29W640FB

Figure 18. In-System Equipment Group Protect flowchart

START

n = 0

RP = V

ID

Verify Protect Set-upEnd

ADDRESS = GROUP ADDRESS

A0, A2, A3, A6 = VIL, A1 = V

ADDRESS = GROUP ADDRESS

A0, A2, A3, A6 = VIL, A1 = V

ADDRESS = GROUP ADDRESS

A0, A2, A3, A6 = VIL, A1 = V

ADDRESS = GROUP ADDRESS

A0, A2, A3, A6 = VIL, A1 = V

WRITE 60h

WRITE 60h

Wait 100µs

WRITE 40h

Wait 4µs

READ DATA

DATA

=

01h

YES

RP = V

IH

IH

IH

IH

IH

NO

++n

= 25

NO

ISSUE READ/RESET

COMMAND

PASS

1. Block Protection Groups are shown in Appendix A, Tables 21 and 22.

can be either at V

2. RP

IH

or at V

when using the In-System Technique to protect the Extended Block.

ID

68/71

YES

RP = V

IH

ISSUE READ/RESET

COMMAND

FAIL

AI11563

M29W640FT, M29W640FB Block protection

Figure 19. In-System Equipment Chip Unprotect flowchart

START

PROTECT ALL GROUPS

Verify Unprotect Set-upEnd

CURRENT GROUP = 0

A0, A2, A3, A6 = VIL, A1 = V

A0, A2, A3 = VIL, A1, A6 = V

ADDRESS = CURRENT GROUP ADDRESS

A0, A2, A3 = VIL, A1, A6 = V

ADDRESS = CURRENT GROUP ADDRESS

A0, A2, A3 = VIL, A1, A6 = V

n = 0

RP = V

ID

WRITE 60h

ANY ADDRESS WITH

WRITE 60h

ANY ADDRESS WITH

Wait 10ms

WRITE 40h

Wait 4µs

READ DATA

IH

IH

IH

IH

INCREMENT

CURRENT GROUP

++n

NO

= 1000

YES

RP = V

IH

ISSUE READ/RESET

COMMAND

FAIL

DATA

=

00h

YESNO

1. Block Protection Groups are shown in Appendix A, Tables 21 and 22.

69/71

LAST

GROUP

RP = V

ISSUE READ/RESET

COMMAND

PASS

NO

YES

IH

AI11564

Revision history M29W640FT, M29W640FB

Revision history

Table 31. Document revision history

Date Revision Changes

01-Mar-2005 0.1 First Issue.

17-May-2005 0.2

Asynchronous Page mode added.
70ns speed class added.

Device codes modified.
TFBGA63 replaced by TFBGA48 6x8 package. ECOPACK text updated
Page size changed to 4 Word.
90ns speed class removed.
Quadruple Word/Octuple Byte Program command added.

07-Oct-2005 1.0

Table 4: Bus operations, BYTE = V
= VIH: A0-A21 addresses for reading the Device Code, the Manufacturer

Code, the Extended Memory Block Verify Code, and the Block Protection
Status, have been updated.

Appendix D: Block protection: Table 30: Programmer technique bus
operations, BYTE = V

or VIL: A0-A21 addresses updated for Block

IH

Protection/Unprotection Verify using the Programmer technique.

Datasheet status changed to “Full Datasheet”.
60ns speed class added.

02-Dec-2005 2

Program Suspend and Resume added.

Section 2.8: V

/Write Protect (V

PP

PP/

commands. Section 4: Command interface restructured.
Table 29: Extended Block address and data updated.

Double Byte Program commands added in Section 4: Command

interface.

15-Dec-2005 3

Table 4: Bus operations, BYTE = V

.: A6 changed from VIH to VIL for Read Block Protection Status

= V

IH

operation.

DQ7 changed to DQ7

for Program, Program During Erase Suspend and

Program Error in Table 9: Status Register Bits.

10-Mar-2006 4

A6 = V

Programmer Equipment Chip Unprotect flowchart.

corrected to A6 = VIH during the Verify phase in Figure 17:

IL

Address ranges modified for x8 and x16 modes in Table 29: Extended

Block address and data.

Amended mistake in second title (M29W640FT changed to

23-Aug-2006 5

M29W640FB); removed the 4th cycle from the double byte program of

Table 7: Commands, 8-bit mode, BYTE = V

25-Oct-2006 6 Table 9: Status Register Bits updated.

10-Dec-2007 7 Applied Numonyx branding.

and Table 5: Bus operations, BYTE

IL

WP) and Section 4.2: Fast Program

and Table 5: Bus operations, BYTE

IL

IL

70/71

M29W640FT, M29W640FB

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applications.

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