Numonyx M29W320DT, M29W320DB Technical data

32 Mbit (4Mbx8 or 2Mbx16, Non-uniform Parameter Blocks,

Feature summary

■ Supply Voltage

–V

–V

■ Access time: 70, 90ns

■ Programming time

– 10µs per Byte/Word typical

■ 67 memory blocks

– 1 Boot Block (Top or Bottom Location)
– 2 Parameter and 64 Main Blocks

■ Program/Erase controller

– Embedded Byte/Word Program algorithms

■ Erase Suspend and Resume modes

– Read and Program another Block during

■ Unlock Bypass Program command

– Faster Production/Batch Programming

■ V

PP

■ Temporary Block Unprotection mode

■ Common Flash Interface

– 64 bit Security code

■ Low power consumption

– Standby and Automatic Standby

■ 100,000 Program/Erase cycles per block

■ Electronic Signature

– Manufacturer Code: 0020h
– Top Device Code M29W320DT: 22CAh
– Bottom Device Code M29W320DB: 22CBh

■ ECOPACK

2.7V to 3.6V for Program, Erase and

CC =

Read

=12V for Fast Program (optional)

PP

Erase Suspend

/WP pin for Fast Program and Write Protect

®

packages available

M29W320DT

M29W320DB

Boot Block), 3V Supply Flash memory

TSOP48 (N)

12 x 20mm

FBGA

TFBGA48 (ZE)

March 2008 Rev 10 1/56

www.numonyx.com

1

Contents M29W320DT, M29W320DB

Contents

1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1 Address Inputs (A0-A20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.2 Data Inputs/Outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.3 Data Inputs/Outputs (DQ8-DQ14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.4 Data Input/Output or Address Input (DQ15A–1) . . . . . . . . . . . . . . . . . . . 12

2.5 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.6 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.7 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.8 V

2.9 Reset/Block Temporary Unprotect (RP

Write Protect (V

PP/

WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

PP/

) . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.10 Ready/Busy Output (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.11 Byte/Word Organization Select (BYTE) . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.12 V

2.13 V

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

CC

Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

SS

3 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.2 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.3 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.4 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.5 Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.6 Special bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.6.1 Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.6.2 Block Protect and Chip Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4 Command Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1 Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.2 Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.3 Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.4 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2/56

M29W320DT, M29W320DB Contents

4.5 Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.6 Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.7 Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.8 Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.9 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.10 Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.11 Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.12 Block Protect and Chip Unprotect commands . . . . . . . . . . . . . . . . . . . . . 21

5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.1 Data Polling Bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.2 Toggle Bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.3 Error Bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.4 Erase Timer Bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

5.5 Alternative Toggle Bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

7 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

8 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

9 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Appendix A Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Appendix B Common Flash Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Appendix C Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

C.1 Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

C.2 In-System Technique. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3/56

List of tables M29W320DT, M29W320DB

List of tables

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2. Bus Operations, BYTE = V
Table 3. Bus Operations, BYTE = V

Table 4. Commands, 16-bit mode, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 5. Commands, 8-bit mode, BYTE = V

Table 6. Program, Erase Times and Program, Erase Endurance Cycles. . . . . . . . . . . . . . . . . . . . . 24

Table 7. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 8. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 9. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 10. Device Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 11. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 12. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 13. Write AC Characteristics, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 14. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 15. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 16. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Package Mechanical Data. . . . . . . 37

Table 17. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Package Mechanical Data . . . . . . . . . . 38

Table 18. Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 19. Top Boot Block Addresses, M29W320DT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 20. Bottom Boot Block Addresses, M29W320DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 21. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 22. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 23. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 24. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 25. Primary Algorithm-Specific Extended Query Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 26. Security Code Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 27. Programmer Technique Bus Operations, BYTE = V

Table 28. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

IL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

IH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

IL

or V

IH

IL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4/56

M29W320DT, M29W320DB List of figures

List of figures

Figure 1. Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3. TFBGA48 Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 4. Block Addresses (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 5. Block Addresses (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 6. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 7. Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 8. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 9. Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 10. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 11. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 12. Reset/Block Temporary Unprotect AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 13. Accelerated Program Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 14. TSOP48 Lead Plastic Thin Small Outline, 12x20 Mm, Top View Package Outline . . . . . . 37

Figure 15. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Bottom View Package Outline . . . . . . . 38

Figure 16. Programmer Equipment Block Protect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 17. Programmer Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 18. In-System Equipment Block Protect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 19. In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

5/56

Summary description M29W320DT, M29W320DB

1 Summary description

The M29W320D is a 32 Mbit (4Mb x8 or 2Mb x16) non-volatile memory that can be read,
erased and reprogrammed. These operations can be performed using a single low voltage
(2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode where it can be
read in the same way as a ROM or EPROM.

The memory is divided into blocks that can be erased independently so it is possible to
preserve valid data while old data is erased. Each block can be protected independently to
prevent accidental Program or Erase commands from modifying the memory. Program and
Erase commands are written to the Command Interface of the memory. An on-chip
Program/Erase Controller simplifies the process of programming or erasing the memory by
taking care of all of the special operations that are required to update the memory contents.
The end of a program or erase operation can be detected and any error conditions
identified. The command set required to control the memory is consistent with JEDEC
standards.

The blocks in the memory are asymmetrically arranged, see Figure 4 and Figure 5, Ta b l e 1 9
and Ta bl e 2 0 . The first or last 64 Kbytes have been divided into four additional blocks. The
16 Kbyte Boot Block can be used for small initialization code to start the microprocessor, the
two 8 Kbyte Parameter Blocks can be used for parameter storage and the remaining 32
Kbyte is a small Main Block where the application may be stored.

Chip Enable, Output Enable and Write Enable signals control the bus operation of the
memory. They allow simple connection to most microprocessors, often without additional
logic.

The memory is offered in TSOP48 (12 x 20mm), and TFBGA48 (6x8mm, 0.8mm pitch)
packages. In order to meet environmental requirements, Numonyx offers the M29W320D in
ECOPACK
Interconnect is marked on the package and on the inner box label, in compliance with
JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also
marked on the inner box label.

The memory is supplied with all the bits erased (set to 1).

®

packages. ECOPACK packages are Lead-free. The category of second Level

6/56

M29W320DT, M29W320DB Summary description

Figure 1. Logic Diagram

VPP/WP

V

CC

21

15

A0-A20

W

E

M29W320DT
M29W320DB

G

RP

BYTE

V

SS

Table 1. Signal Names

A0-A20 Address Inputs

DQ0-DQ7 Data Inputs/Outputs

DQ8-DQ14 Data Inputs/Outputs

DQ15A–1 Data Input/Output or Address Input

E

Chip Enable

DQ0-DQ14

DQ15A–1

RB

AI90189B

G

W

RP

RB

BYTE

V

CC

V

/WP VPP/Write Protect

PP

V

SS

Output Enable

Write Enable

Reset/Block Temporary Unprotect

Ready/Busy Output

Byte/Word Organization Select

Supply Voltage

Ground

NC Not Connected Internally

7/56

Summary description M29W320DT, M29W320DB

Figure 2. TSOP Connections

A15

1

48
A14
A13
A12
A11
A10 DQ14

A9

A8
A19
A20

W
RP
NC

12

M29W320DT

M29W320DB

13

37
36

VPP/WP

RB
A18
A17

A7
A6
A5
A4
A3
A2

24 25

A1

AI90190

A16
BYTE
V

SS

DQ15A–1
DQ7

DQ6
DQ13
DQ5
DQ12
DQ4
V

CC

DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
V

SS

E
A0

8/56

M29W320DT, M29W320DB Summary description

Figure 3. TFBGA48 Connections (Top view through package)

654321

A

B

C

D

E

F

G

H

A3

A4

A2

A1

A0

E

G

V

SS

A7

A17

A6

A5 A20

DQ0

DQ8

DQ9

DQ1

RB

V

PP

A18

DQ2

DQ10

DQ11

DQ3

/

WP

W

RP

NC

A19

DQ5

DQ12

V

CC

DQ4

A9

A8

A10

A11

DQ7

DQ14

DQ13

DQ6

A13

A12

A14

A15

A16

BYTE

DQ15

A–1

V

SS

AI08084

9/56

Summary description M29W320DT, M29W320DB

Figure 4. Block Addresses (x8)

M29W320DT

Top Boot Block Addresses (x8)

Bottom Boot Block Addresses (x8)

M29W320DB

3FFFFFh

3FC000h
3FBFFFh

3FA000h

3F9FFFh

3F8000h

3F7FFFh

3F0000h

3EFFFFh

3E0000h

01FFFFh

010000h

00FFFFh

000000h

16 KByte

8 KByte

8 KByte

32 KByte

64 KByte

Total of 63

64 KByte Blocks

64 KByte

64 KByte

3FFFFFh

3F0000h

3EFFFFh

3E0000h

01FFFFh

010000h

00FFFFh

008000h

007FFFh

006000h

005FFFh

004000h

003FFFh

000000h

64 KByte

64 KByte

64 KByte

32 KByte

8 KByte

8 KByte

16 KByte

1. Also see Appendix A: Block Addresses, Table 19 and Table 20 for a full listing of the Block Addresses.

Total of 63

64 KByte Blocks

AI90192

10/56

M29W320DT, M29W320DB Summary description

Figure 5. Block Addresses (x16)

Top Boot Block Addresses (x16)

M29W320DT

Bottom Boot Block Addresses (x16)

M29W320DB

1FFFFFh

1FE000h

1FDFFFh

1FD000h

1FCFFFh

1FC000h

1FBFFFh

1F8000h

1F7FFFh

1F0000h

00FFFFh

008000h

007FFFh

000000h

8 KWord

4 KWord

4 KWord

16 KWord

32 KWord

Total of 63

32 KWord Blocks

32 KWord

32 KWord

1FFFFFh

1F8000h

1F7FFFh

1F0000h

00FFFFh

008000h

007FFFh

004000h

003FFFh

003000h

002FFFh

002000h

001FFFh

000000h

32 KWord

32 KWord

Total of 63

32 KWord Blocks

32 KWord

16 KWord

4 KWord

4 KWord

8 KWord

AI90193

1. Also see Appendix Appendix A: Block Addresses, Table 19 and Table 20 for a full listing of the Block Addresses.

11/56

Signal descriptions M29W320DT, M29W320DB

2 Signal descriptions

See Figure 1: Logic Diagram, and Table 1: Signal Names, for a brief overview of the signals
connected to this device.

2.1 Address Inputs (A0-A20)

The Address Inputs select the cells in the memory array to access during Bus Read
operations. During Bus Write operations they control the commands sent to the Command
Interface of the internal state machine.

2.2 Data Inputs/Outputs (DQ0-DQ7)

The Data I/O outputs the data stored at the selected address during a Bus Read operation.
During Bus Write operations they represent the commands sent to the Command Interface
of the internal state machine.

2.3 Data Inputs/Outputs (DQ8-DQ14)

The Data I/O outputs the data stored at the selected address during a Bus Read operation
when BYTE
impedance. During Bus Write operations the Command Register does not use these bits.
When reading the Status Register these bits should be ignored.

is High, VIH. When BYTE is Low, VIL, these pins are not used and are high

2.4 Data Input/Output or Address Input (DQ15A–1)

When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14).
When BYTE
LSB of the Word on the other addresses, DQ15A–1 High will select the MSB. Throughout
the text consider references to the Data Input/Output to include this pin when BYTE
and references to the Address Inputs to include this pin when BYTE
stated explicitly otherwise.

is Low, VIL, this pin behaves as an address pin; DQ15A–1 Low will select the

is Low except when

2.5 Chip Enable (E)

The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to
be performed. When Chip Enable is High, V

, all other pins are ignored.

IH

2.6 Output Enable (G)

The Output Enable, G, controls the Bus Read operation of the memory.

is High

12/56

M29W320DT, M29W320DB Signal descriptions

2.7 Write Enable (W)

The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface.

2.8 V

The VPP/Write Protect pin provides two functions. The VPP function allows the memory to
use an external high voltage power supply to reduce the time required for Unlock Bypass
Program operations. The Write Protect function provides a hardware method of protecting
the 16 Kbyte Boot Block. The V

When V
and Erase operations in this block are ignored while V

When V
of the 16 Kbyte boot block. Program and Erase operations can now modify the data in the 16
Kbyte Boot Block unless the block is protected using Block Protection.

When V
Bypass mode. When V
During Unlock Bypass Program operations the memory draws I
programming circuits. See the description of the Unlock Bypass command in the Command
Interface section. The transitions from V
t

Never raise V
memory may be left in an indeterminate state.

A 0.1µF capacitor should be connected between the V
Ground pin to decouple the current surges from the power supply. The PCB track widths
must be sufficient to carry the currents required during Unlock Bypass Program, I

Write Protect (VPP/WP)

PP/

/Write Protect is Low, VIL, the memory protects the 16 Kbyte Boot Block; Program

PP

/Write Protect is High, VIH, the memory reverts to the previous protection status

PP

/Write Protect is raised to V

PP

, see Figure 13.

VHVPP

/Write Protect to VPP from any mode except Read mode, otherwise the

PP

/Write Protect returns to VIH or VIL normal operation resumes.

PP

/Write Protect pin must not be left floating or unconnected.

PP

/Write Protect is Low.

PP

the memory automatically enters the Unlock

PP

from the pin to supply the

PP

to VPP and from VPP to VIH must be slower than

IH

/Write Protect pin and the VSS

PP

.

PP

2.9 Reset/Block Temporary Unprotect (RP)

The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the
memory or to temporarily unprotect all Blocks that have been protected.

Note that if V
even if RP is at V

A Hardware Reset is achieved by holding Reset/Block Temporary Unprotect Low, V
least t

PLPX

ready for Bus Read and Bus Write operations after t
See the Ready/Busy Output section, Tab le 1 5 and Figure 12, for more details.

Holding RP
and Erase operations on all blocks will be possible. The transition from V
slower than t

/WP is at VIL, then the 16 KByte outermost boot block will remain protect

PP

.

ID

. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be

PHEL

at VID will temporarily unprotect the protected Blocks in the memory. Program

.

PHPHH

13/56

or t

, whichever occurs last.

RHEL

to VID must be

IH

, for at

IL

Signal descriptions M29W320DT, M29W320DB

2.10 Ready/Busy Output (RB)

The Ready/Busy pin is an open-drain output that can be used to identify when the device is
performing a Program or Erase operation. During Program or Erase operations Ready/Busy
is Low, V
Erase Suspend mode.

. Ready/Busy is high-impedance during Read mode, Auto Select mode and

OL

Note that if V
even if RP is at V

/WP is at VIL, then the 16 KByte outermost boot block will remain protect

PP

.

ID

After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy
becomes high-impedance. See Tab l e 1 5 and Figure 12.

The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the
memories is busy.

2.11 Byte/Word Organization Select (BYTE)

The Byte/Word Organization Select pin is used to switch between the x8 and x16 Bus
modes of the memory. When Byte/Word Organization Select is Low, V
x8 mode, when it is High, V

, the memory is in x16 mode.

IH

2.12 VCC Supply Voltage

VCC provides the power supply for all operations (Read, Program and Erase).

The Command Interface is disabled when the V
Voltage, V

. This prevents Bus Write operations from accidentally damaging the data

LKO

during power up, power down and power surges. If the Program/Erase Controller is
programming or erasing during this time then the operation aborts and the memory contents
being altered will be invalid.

Supply Voltage is less than the Lockout

CC

, the memory is in

IL

A 0.1µF capacitor should be connected between the V
Ground pin to decouple the current surges from the power supply. The PCB track widths
must be sufficient to carry the currents required during Program and Erase operations, I

2.13 VSS Ground

VSS is the reference for all voltage measurements.

14/56

Supply Voltage pin and the VSS

CC

CC3

.

M29W320DT, M29W320DB Bus operations

3 Bus operations

There are five standard bus operations that control the device. These are Bus Read, Bus
Write, Output Disable, Standby and Automatic Standby. See Ta bl e 2 and Tab le 3 , Bus
operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write
Enable are ignored by the memory and do not affect bus operations.

3.1 Bus Read

Bus Read operations read from the memory cells, or specific registers in the Command
Interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs, applying a Low signal, V
Enable High, V

AC Waveforms, and Table 12: Read AC Characteristics, for details of when the output

becomes valid.

3.2 Bus Write

Bus Write operations write to the Command Interface. A valid Bus Write operation begins by
setting the desired address on the Address Inputs. The Address Inputs are latched by the
Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs
last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of
Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, V
during the whole Bus Write operation. See Figure 10 and Figure 11, Write AC waveforms,
and Ta bl e 1 3 and Tab le 1 4, Write AC Characteristics, for details of the timing requirements.

. The Data Inputs/Outputs will output the value, see Figure 9: Read Mode

IH

, to Chip Enable and Output Enable and keeping Write

IL

IH

,

3.3 Output Disable

The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH.

3.4 Standby

When Chip Enable is High, VIH, the memory enters Standby mode and the Data
Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to
the Standby Supply Current, I
Standby current level see Table 11: DC Characteristics.

During program or erase operations the memory will continue to use the Program/Erase
Supply Current, I

, for Program or Erase operations until the operation completes.

CC3

3.5 Automatic Standby

If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 300ns or
more the memory enters Automatic Standby where the internal Supply Current is reduced to
the Standby Supply Current, I
Read operation is in progress.

, Chip Enable should be held within V

CC2

. The Data Inputs/Outputs will still output data if a Bus

CC2

15/56

± 0.2V. For the

CC

Bus operations M29W320DT, M29W320DB

3.6 Special bus operations

Additional bus operations can be performed to read the Electronic Signature and also to
apply and remove Block Protection. These bus operations are intended for use by
programming equipment and are not usually used in applications. They require V
applied to some pins.

3.6.1 Electronic Signature

The memory has two codes, the manufacturer code and the device code, that can be read
to identify the memory. These codes can be read by applying the signals listed in Ta bl e 2
and Ta bl e 3 , Bus Operations.

3.6.2 Block Protect and Chip Unprotect

Each block can be separately protected against accidental Program or Erase. The whole
chip can be unprotected to allow the data inside the blocks to be changed.

Block Protect and Chip Unprotect operations are described in Appendix C: Block Protection.

Table 2. Bus Operations, BYTE = V

Operation E G W

(1)

IL

Address Inputs

DQ15A–1, A0-A20

Data Inputs/Outputs

DQ14-DQ8 DQ7-DQ0

to be

ID

Bus Read V

Bus Write V

Output Disable X V

Standby V

Read Manufacturer
Code

V

Read Device Code V

1. X = VIL or VIH.

Table 3. Bus Operations, BYTE = V

V

IL

V

IL

IH

V

IL

V

IL

VIHCell Address Hi-Z Data Output

IL

VILCommand Address Hi-Z Data Input

IH

VIHX Hi-Z Hi-Z

IH

X X X Hi-Z Hi-Z

V

IL

IL

IH

V

IH

Operation E G W

Bus Read V

Bus Write V

Output Disable X V

Standby V

Read Manufacturer
Code

V

Read Device Code V

1. X = VIL or VIH.

V

IL

V

IL

IH

V

IL

V

IL

VIHCell Address Data Output

IL

VILCommand Address Data Input

IH

VIHXHi-Z

IH

XXX Hi-Z

V

IL

IL

IH

V

IH

A0 = VIL, A1 = VIL, A9 = VID,
Others VIL or V

IH

A0 = VIH, A1 = VIL,
A9 = V

(1)

IH

, Others VIL or V

ID

Address Inputs

A0-A20

A0 = VIL, A1 = VIL, A9 = VID,
Others VIL or V

IH

A0 = VIH, A1 = VIL, A9 = VID,
Others V

IL

or V

IH

Hi-Z 20h

IH

Hi-Z

CAh (M29W320DT)
CBh (M29W320DB)

Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

0020h

22CAh (M29W320DT)
22CBh (M29W320DB)

16/56

M29W320DT, M29W320DB Command Interface

4 Command Interface

All Bus Write operations to the memory are interpreted by the Command Interface.
Commands consist of one or more sequential Bus Write operations. Failure to observe a
valid sequence of Bus Write operations will result in the memory returning to Read mode.
The long command sequences are imposed to maximize data security.

The address used for the commands changes depending on whether the memory is in 16­bit or 8-bit mode. See either Ta b le 4 , or Tab le 5 , depending on the configuration that is being
used, for a summary of the commands.

4.1 Read/Reset command

The Read/Reset command returns the memory to its Read mode where it behaves like a
ROM or EPROM, unless otherwise stated. It also resets the errors in the Status Register.
Either one or three Bus Write operations can be used to issue the Read/Reset command.

The Read/Reset Command can be issued, between Bus Write cycles before the start of a
program or erase operation, to return the device to read mode. Once the program or erase
operation has started the Read/Reset command is no longer accepted. The Read/Reset
command will not abort an Erase operation when issued while in Erase Suspend.

4.2 Auto Select command

The Auto Select command is used to read the Manufacturer Code, the Device Code and the
Block Protection Status. Three consecutive Bus Write operations are required to issue the
Auto Select command. Once the Auto Select command is issued the memory remains in
Auto Select mode until a Read/Reset command is issued. Read CFI Query and Read/Reset
commands are accepted in Auto Select mode, all other commands are ignored.

From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation
with A0 = V
Manufacturer Code for Numonyx is 0020h.

The Device Code can be read using a Bus Read operation with A0 = V
other address bits may be set to either V
22CAh and for the M29W320DB is 22CBh.

The Block Protection Status of each block can be read using a Bus Read operation with A0
= V

, A1 = VIH, and A12-A20 specifying the address of the block. The other address bits

IL

may be set to either V
Data Inputs/Outputs DQ0-DQ7, otherwise 00h is output.

and A1 = VIL. The other address bits may be set to either VIL or VIH. The

IL

or VIH. If the addressed block is protected then 01h is output on

IL

and A1 = VIL. The

or VIH. The Device Code for the M29W320DT is

IL

IH

17/56

Command Interface M29W320DT, M29W320DB

4.3 Read CFI Query command

The Read CFI Query Command is used to read data from the Common Flash Interface
(CFI) Memory Area. This command is valid when the device is in the Read Array mode, or
when the device is in Autoselected mode.

One Bus Write cycle is required to issue the Read CFI Query Command. Once the
command is issued subsequent Bus Read operations read from the Common Flash
Interface Memory Area.

The Read/Reset command must be issued to return the device to the previous mode (the
Read Array mode or Autoselected mode). A second Read/Reset command would be
needed if the device is to be put in the Read Array mode from Autoselected mode.

See Appendix B: Common Flash Interface (CFI), Tab le 2 1 , Tab le 2 2 , Tab l e 2 3, Ta bl e 2 4,

Ta bl e 2 5 and Tab le 2 6 for details on the information contained in the Common Flash

Interface (CFI) memory area.

4.4 Program command

The Program command can be used to program a value to one address in the memory array
at a time. The command requires four Bus Write operations, the final write operation latches
the address and data in the internal state machine and starts the Program/Erase Controller.

If the address falls in a protected block then the Program command is ignored, the data
remains unchanged. The Status Register is never read and no error condition is given.

During the program operation the memory will ignore all commands. It is not possible to
issue any command to abort or pause the operation. Typical program times are given in

Ta bl e 6 . Bus Read operations during the program operation will output the Status Register

on the Data Inputs/Outputs. See the section on the Status Register for more details.

After the program operation has completed the memory will return to the Read mode, unless
an error has occurred. When an error occurs the memory will continue to output the Status
Register. A Read/Reset command must be issued to reset the error condition and return to
Read mode.

Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase
Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.

4.5 Unlock Bypass command

The Unlock Bypass command is used in conjunction with the Unlock Bypass Program
command to program the memory. When the cycle time to the device is long (as with some
EPROM programmers) considerable time saving can be made by using these commands.
Three Bus Write operations are required to issue the Unlock Bypass command.

Once the Unlock Bypass command has been issued the memory will only accept the Unlock
Bypass Program command and the Unlock Bypass Reset command. The memory can be
read as if in Read mode.

The memory offers accelerated program operations through the V
When the system asserts V
enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass

18/56

on the VPP/Write Protect pin, the memory automatically

PP

/Write Protect pin.

PP

M29W320DT, M29W320DB Command Interface

program command sequence. The memory uses the higher voltage on the VPP/Write
Protect pin, to accelerate the Unlock Bypass Program operation.

Never raise V
memory may be left in an indeterminate state.

/Write Protect to VPP from any mode except Read mode, otherwise the

PP

4.6 Unlock Bypass Program command

The Unlock Bypass Program command can be used to program one address in the memory
array at a time. The command requires two Bus Write operations, the final write operation
latches the address and data in the internal state machine and starts the Program/Erase
Controller.

The Program operation using the Unlock Bypass Program command behaves identically to
the Program operation using the Program command. The operation cannot be aborted, the
Status Register is read and protected blocks cannot be programmed. Errors must be reset
using the Read/Reset command, which leaves the device in Unlock Bypass Mode. See the
Program command for details on the behavior.

4.7 Unlock Bypass Reset command

The Unlock Bypass Reset command can be used to return to Read/Reset mode from
Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass
Reset command. Read/Reset command does not exit from Unlock Bypass Mode.

4.8 Chip Erase command

The Chip Erase command can be used to erase the entire chip. Six Bus Write operations
are required to issue the Chip Erase Command and start the Program/Erase Controller.

If any blocks are protected then these are ignored and all the other blocks are erased. If all
of the blocks are protected the Chip Erase operation appears to start but will terminate
within about 100µs, leaving the data unchanged. No error condition is given when protected
blocks are ignored.

During the erase operation the memory will ignore all commands, including the Erase
Suspend command. It is not possible to issue any command to abort the operation. Typical
chip erase times are given in Tab le 6 . All Bus Read operations during the Chip Erase
operation will output the Status Register on the Data Inputs/Outputs. See the section on the
Status Register for more details.

After the Chip Erase operation has completed the memory will return to the Read Mode,
unless an error has occurred. When an error occurs the memory will continue to output the
Status Register. A Read/Reset command must be issued to reset the error condition and
return to Read Mode.

The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All
previous data is lost.

19/56

Command Interface M29W320DT, M29W320DB

4.9 Block Erase command

The Block Erase command can be used to erase a list of one or more blocks. Six Bus Write
operations are required to select the first block in the list. Each additional block in the list can
be selected by repeating the sixth Bus Write operation using the address of the additional
block. The Block Erase operation starts the Program/Erase Controller about 50µs after the
last Bus Write operation. Once the Program/Erase Controller starts it is not possible to
select any more blocks. Each additional block must therefore be selected within 50µs of the
last block. The 50µs timer restarts when an additional block is selected. The Status Register
can be read after the sixth Bus Write operation. See the Status Register section for details
on how to identify if the Program/Erase Controller has started the Block Erase operation.

If any selected blocks are protected then these are ignored and all the other selected blocks
are erased. If all of the selected blocks are protected the Block Erase operation appears to
start but will terminate within about 100µs, leaving the data unchanged. No error condition is
given when protected blocks are ignored.

During the Block Erase operation the memory will ignore all commands except the Erase
Suspend command. Typical block erase times are given in Ta bl e 6 . All Bus Read operations
during the Block Erase operation will output the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more details.

After the Block Erase operation has completed the memory will return to the Read Mode,
unless an error has occurred. When an error occurs the memory will continue to output the
Status Register. A Read/Reset command must be issued to reset the error condition and
return to Read mode.

The Block Erase Command sets all of the bits in the unprotected selected blocks to ’1’. All
previous data in the selected blocks is lost.

4.10 Erase Suspend command

The Erase Suspend Command may be used to temporarily suspend a Block Erase
operation and return the memory to Read mode. The command requires one Bus Write
operation.

The Program/Erase Controller will suspend within the Erase Suspend Latency Time (refer to

Ta bl e 6 for value) of the Erase Suspend Command being issued. Once the Program/Erase

Controller has stopped the memory will be set to Read mode and the Erase will be
suspended. If the Erase Suspend command is issued during the period when the memory is
waiting for an additional block (before the Program/Erase Controller starts) then the Erase is
suspended immediately and will start immediately when the Erase Resume Command is
issued. It is not possible to select any further blocks to erase after the Erase Resume.

During Erase Suspend it is possible to Read and Program cells in blocks that are not being
erased; both Read and Program operations behave as normal on these blocks. If any
attempt is made to program in a protected block or in the suspended block then the Program
command is ignored and the data remains unchanged. The Status Register is not read and
no error condition is given. Reading from blocks that are being erased will output the Status
Register.

It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands
during an Erase Suspend. The Read/Reset command must be issued to return the device to
Read Array mode before the Resume command will be accepted.

20/56

M29W320DT, M29W320DB Command Interface

4.11 Erase Resume command

The Erase Resume command must be used to restart the Program/Erase Controller after an
Erase Suspend. The device must be in Read Array mode before the Resume command will
be accepted. An erase can be suspended and resumed more than once.

4.12 Block Protect and Chip Unprotect commands

Each block can be separately protected against accidental Program or Erase. The whole
chip can be unprotected to allow the data inside the blocks to be changed.

Block Protect and Chip Unprotect operations are described in Appendix C: Block Protection.

21/56

Command Interface M29W320DT, M29W320DB

Table 4. Commands, 16-bit mode, BYTE = V

Command

1st 2nd 3rd 4th 5th 6th

Length

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read/Reset

(3)

1X F0

3 555 AA 2AA 55 X F0

Auto Select

Program

(4)

(5)

Unlock Bypass

Unlock Bypass
Program

Unlock Bypass
Reset

Chip Erase

Block Erase

(5)

(7)

(5)

(5)

Erase Suspend

Erase Resume

Read CFI Query

(6)

(8)

(9)

(10)

3 555 AA 2AA 55 555 90

4 555 AA 2AA 55 555 A0 PA PD

3 555 AA 2AA 55 555 20

2X A0PAPD

2X 90 X 00

6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10

6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30

1X B0

1X 30

155 98

(1)(2)

IH

Bus Write Operations

1. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in
hexadecimal.

2. The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15
are Don’t Care. DQ15A–1 is A–1 when BYTE

3. After a Read/Reset command, read the memory as normal until another command is issued. Read/Reset command is
ignored during algorithm execution.

4. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.

5. After Program, Unlock Bypass Program, Chip Erase, Block Erase commands read the Status Register until the
Program/Erase Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase
Command with additional Bus Write Operations until Timeout Bit is set.

6. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.

7. After the Unlock Bypass Reset command read the memory as normal until another command is issued.

8. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program
commands on non-erasing blocks as normal.

9. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the
Program/Erase Controller completes and the memory returns to Read Mode.

10. CFI Query command is valid when device is ready to read array data or when device is in autoselected mode.

is VIL or DQ15 when BYTE is VIH.

22/56

M29W320DT, M29W320DB Command Interface

Table 5. Commands, 8-bit mode, BYTE = V

Command

1st 2nd 3rd 4th 5th 6th

Length

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read/Reset

(3)

1X F0

3 AAA AA 555 55 X F0

Auto Select

Program

(4)

(5)

Unlock Bypass

Unlock Bypass
Program

Unlock Bypass
Reset

Chip Erase

Block Erase

(5)

(7)

(5)

(5)

Erase Suspend

Erase Resume

Read CFI Query

(6)

(8)

(9)

(10)

3 AAA AA 555 55 AAA 90

4 AAA AA 555 55 AAA A0 PA PD

3 AAA AA 555 55 AAA 20

2 X A0 PA PD

2X 90 X 00

6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10

6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30

1X B0

1X 30

1AA 98

(1)(2)

IL

Bus Write Operations

1. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in
hexadecimal.

2. The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15
are Don’t Care. DQ15A–1 is A–1 when BYTE

3. After a Read/Reset command, read the memory as normal until another command is issued. Read/Reset command is
ignored during algorithm execution.

4. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.

5. After a Program, Unlock Bypass Program, Chip Erase, Block Erase command read the Status Register until the
Program/Erase Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase
Command with additional Bus Write Operations until Timeout Bit is set.

6. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.

7. After the Unlock Bypass Reset command read the memory as normal until another command is issued.

8. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program
commands on non-erasing blocks as normal.

9. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the
Program/Erase Controller completes and the memory returns to Read Mode.

10. The CFI Query command is valid when device is ready to read array data or when device is in autoselected mode.

is VIL or DQ15 when BYTE is VIH.

23/56

Command Interface M29W320DT, M29W320DB

Table 6. Program, Erase Times and Program, Erase Endurance Cycles

Chip Erase 40 200

Block Erase (64 KBytes) 0.8 6

Erase Suspend Latency Time 15 25

Program (Byte or Word) 10 200

Accelerated Program (Byte or Word) 8 150

Chip Program (Byte by Byte) 40 200

Chip Program (Word by Word) 20 100

Parameter Min Typ

(1)(2)

Max

(4)

(4)

(3)

(3)

(3)

(3)

(3)

(2)

Unit

s

s

µs

µs

µs

s

s

Program/Erase Cycles (per Block) 100,000 cycles

Data Retention 20 years

1. Typical values measured at room temperature and nominal voltages.

2. Sampled, but not 100% tested.

3. Maximum value measured at worst case conditions for both temperature and V

4. Maximum value measured at worst case conditions for both temperature and V

after 100,00 program/erase cycles.

CC

.

CC

24/56

M29W320DT, M29W320DB Status Register

5 Status Register

Bus Read operations from any address always read the Status Register during Program and
Erase operations. It is also read during Erase Suspend when an address within a block
being erased is accessed.

The bits in the Status Register are summarized in Table 7: Status Register Bits.

5.1 Data Polling Bit (DQ7)

The Data Polling Bit can be used to identify whether the Program/Erase Controller has
successfully completed its operation or if it has responded to an Erase Suspend. The Data
Polling Bit is output on DQ7 when the Status Register is read.

During Program operations the Data Polling Bit outputs the complement of the bit being
programmed to DQ7. After successful completion of the Program operation the memory
returns to Read mode and Bus Read operations from the address just programmed output
DQ7, not its complement.

During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state
of DQ7. After successful completion of the Erase operation the memory returns to Read
Mode.

In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation
within a block being erased. The Data Polling Bit will change from a ’0’ to a ’1’ when the
Program/Erase Controller has suspended the Erase operation.

Figure 6: Data Polling Flowchart, gives an example of how to use the Data Polling Bit. A

Valid Address is the address being programmed or an address within the block being
erased.

5.2 Toggle Bit (DQ6)

The Toggle Bit can be used to identify whether the Program/Erase Controller has
successfully completed its operation or if it has responded to an Erase Suspend. The Toggle
Bit is output on DQ6 when the Status Register is read.

During Program and Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations at any address. After successful completion of the
operation the memory returns to Read mode.

During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block
being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has
suspended the Erase operation.

If any attempt is made to erase a protected block, the operation is aborted, no error is
signalled and DQ6 toggles for approximately 100µs. If any attempt is made to program a
protected block or a suspended block, the operation is aborted, no error is signalled and
DQ6 toggles for approximately 1µs.

Figure 7: Data Toggle Flowchart, gives an example of how to use the Data Toggle Bit.

25/56

Status Register M29W320DT, M29W320DB

5.3 Error Bit (DQ5)

The Error Bit can be used to identify errors detected by the Program/Erase Controller. The
Error Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the
correct data to the memory. If the Error Bit is set a Read/Reset command must be issued
before other commands are issued. The Error bit is output on DQ5 when the Status Register
is read.

Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting to
do so will set DQ5 to ‘1’. A Bus Read operation to that address will show the bit is still ‘0’.
One of the Erase commands must be used to set all the bits in a block or in the whole
memory from ’0’ to ’1’.

5.4 Erase Timer Bit (DQ3)

The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation
during a Block Erase command. Once the Program/Erase Controller starts erasing the
Erase Timer Bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer Bit
is set to ’0’ and additional blocks to be erased may be written to the Command Interface.
The Erase Timer Bit is output on DQ3 when the Status Register is read.

5.5 Alternative Toggle Bit (DQ2)

The Alternative Toggle Bit can be used to monitor the Program/Erase controller during
Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is
read.

During Chip Erase and Block Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’,
etc., with successive Bus Read operations from addresses within the blocks being erased. A
protected block is treated the same as a block not being erased. Once the operation
completes the memory returns to Read mode.

During Erase Suspend the Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with
successive Bus Read operations from addresses within the blocks being erased. Bus Read
operations to addresses within blocks not being erased will output the memory cell data as if
in Read mode.

After an Erase operation that causes the Error Bit to be set the Alternative Toggle Bit can be
used to identify which block or blocks have caused the error. The Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses
within blocks that have not erased correctly. The Alternative Toggle Bit does not change if
the addressed block has erased correctly.

26/56

M29W320DT, M29W320DB Status Register

Table 7. Status Register Bits

(1)

Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB

Program Any Address DQ7 Toggle0––0

Program During Erase
Suspend

Any Address DQ7 Toggle0––0

Program Error Any Address DQ7 Toggle1––0

Chip Erase Any Address 0 Toggle 0 1 Toggle 0

Block Erase before
timeout

Erasing Block 0 Toggle 0 0 Toggle 0

Non-Erasing Block 0 Toggle 0 0 No Toggle 0

Erasing Block 0 Toggle 0 1 Toggle 0

Block Erase

Non-Erasing Block 0 Toggle 0 1 No Toggle 0

Erasing Block 1 No Toggle 0 – Toggle 1

Erase Suspend

Non-Erasing Block Data read as normal 1

Good Block Address 0 Toggle 1 1 No Toggle 0

Erase Error

Faulty Block Address 0 Toggle 1 1 Toggle 0

1. Unspecified data bits should be ignored.

Figure 6. Data Polling Flowchart

START

READ DQ5 & DQ7

at VALID ADDRESS

DQ7

YES

=

DATA

NO

NO

DQ5

= 1

YES

READ DQ7

at VALID ADDRESS

DQ7

YES

=

DATA

NO

FAIL PASS

AI90194

27/56

Status Register M29W320DT, M29W320DB

Figure 7. Data Toggle Flowchart

START

READ DQ6

READ

DQ5 & DQ6

DQ6

=

TOGGLE

YES

NO

DQ5

= 1

YES

READ DQ6

TWICE

DQ6

=

TOGGLE

YES

FAIL PASS

NO

NO

AI01370C

28/56

M29W320DT, M29W320DB Maximum rating

6 Maximum rating

Stressing the device above the rating listed in the Absolute Maximum Ratings table may
cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions
for extended periods may affect device reliability. These are stress ratings only and
operation of the device at these or any other conditions above those indicated in the
Operating sections of this specification is not implied. Refer also to the Numonyx SURE
Program and other relevant quality documents.

Table 8. Absolute Maximum Ratings

Symbol Parameter Min Max Unit

T

BIAS

T

STG

V

IO

V

CC

V

ID

V

PP

1. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions.

2. Maximum voltage may overshoot to V

Temperature Under Bias –50 125 °C

Storage Temperature –65 150 °C

Input or Output Voltage

(1)(2)

–0.6 VCC +0.6 V

Supply Voltage –0.6 4 V

Identification Voltage –0.6 13.5 V

Program Voltage –0.6 13.5 V

+2V during transition and for less than 20ns during transitions.

CC

29/56

DC and AC parameters M29W320DT, M29W320DB

7 DC and AC parameters

This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristics Tables that
follow, are derived from tests performed under the Measurement Conditions summarized in

Table 9: Operating and AC Measurement Conditions. Designers should check that the

operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.

Table 9. Operating and AC Measurement Conditions

M29W320D

Parameter

70 90

Unit

Min Max Min Max

VCC Supply Voltage 3.0 3.6 2.7 3.6 V

Ambient Operating Temperature –40 85 –40 85 °C

Load Capacitance (CL)3030pF

Input Rise and Fall Times 10 10 ns

Input Pulse Voltages 0 to V

Input and Output Timing Ref. Voltages V

CC

CC

/2 VCC/2 V

0 to V

CC

V

Figure 8. AC Measurement I/O Waveform

V

CC

VCC/2

0V

AI90196

30/56

M29W320DT, M29W320DB DC and AC parameters

Figure 1. AC Measurement Load Circuit

V

PP

Table 10. Device Capacitance

V

0.1µF

CL includes JIG capacitance

CC

DEVICE
UNDER

TEST

0.1µF

(1)

V

CC

25kΩ

C

25kΩ

L

AI90197

Symbol Parameter Test Condition Min Max Unit

C

IN

C

OUT

1. Sampled only, not 100% tested.

Input Capacitance VIN = 0V 6 pF

Output Capacitance V

= 0V 12 pF

OUT

31/56

DC and AC parameters M29W320DT, M29W320DB

Table 11. DC Characteristics

Symbol Parameter Test Condition Min Typ. Max Unit

I

Input Leakage Current 0V ≤ VIN ≤ V

LI

Output Leakage Current 0V ≤ V

I

LO

I

I

I

CC3

V

V

V

V

V

V

1. Sampled only, not 100% tested.

Supply Current (Read)

CC1

Supply Current (Standby)

CC2

Supply Current

(1)

(Program/Erase)

V

Input Low Voltage –0.5 0.8 V

IL

Input High Voltage 0.7V

IH

Voltage for V

PP

Program Acceleration

Current for V

I

PP

Program Acceleration

Output Low Voltage IOL = 1.8mA 0.45 V

OL

Output High Voltage IOH = –100µAV

OH

Identification Voltage 11.5 12.5 V

ID

Identification Current A9 = V

I

ID

Program/Erase Lockout

LKO

Supply Voltage

PP

PP

/WP

/WP

E

= VIL, G = VIH,

f = 6MHz

E

= VCC ±0.2V,

= VCC ±0.2V

RP

Program/Eras

e

Controller

active

= 3.0V ±10% 11.5 12.5 V

V

CC

= 3.0V ±10% 10 mA

V

CC

OUT

CC

≤ V

CC

VPP/WP =

or V

V

IL

VPP/WP =

V

PP

ID

510mA

35 100 µA

IH

CC

–0.4 V

CC

1.8 2.3 V

±1 µA

±1 µA

20 mA

20 mA

VCC +0.3 V

100 µA

32/56

M29W320DT, M29W320DB DC and AC parameters

Figure 9. Read Mode AC Waveforms

tAVAV

A0-A20/
A–1

tAVQV tAXQX

E

VALID

tELQV

tELQX tEHQZ

G

tGLQX tGHQX

tGLQV

DQ0-DQ7/
DQ8-DQ15

tBHQV

BYTE

tELBL/tELBH tBLQZ

Table 12. Read AC Characteristics

Symbol Alt Parameter Test Condition

E

t

AVAV

t

AVQ V

(1)

t

ELQX

t

ELQV

(1)

t

GLQX

t

GLQV

(1)

t

EHQZ

(1)

t

GHQZ

t

EHQX

t

GHQX

t

AXQX

t

ELBL

t

ELBH

t

BLQZ

t

BHQV

1. Sampled only, not 100% tested.

t

t

ACC

t

t

t

OLZ

t

t

t

t

t

ELFL

t

ELFH

t

FLQZ

t

FHQV

Address Valid to Next Address Valid

RC

Address Valid to Output Valid

Chip Enable Low to Output Transition G = V

LZ

Chip Enable Low to Output Valid G = V

CE

Output Enable Low to Output
Tr an s i ti o n

Output Enable Low to Output Valid E = V

OE

Chip Enable High to Output Hi-Z G = V

HZ

Output Enable High to Output Hi-Z E = V

DF

Chip Enable, Output Enable or

OH

Address Transition to Output Transition

Chip Enable to BYTE Low or High Max 5 5 ns

BYTE Low to Output Hi-Z Max 25 30 ns

BYTE High to Output Valid Max 30 40 ns

= VIL,

G = V

= VIL,

E

= V

G

= V

E

IL

IL

IL

IL

IL

IL

IL

IL

tEHQX

tGHQZ

VALID

AI90198

M29W320D

Unit

70 90

Min 70 90 ns

Max 70 90 ns

Min 0 0 ns

Max 70 90 ns

Min 0 0 ns

Max 30 35 ns

Max 25 30 ns

Max 25 30 ns

Min 0 0 ns

33/56

DC and AC parameters M29W320DT, M29W320DB

Figure 10. Write AC Waveforms, Write Enable Controlled

tAVAV

A0-A20/
A–1

tAVWL

E

VALID

tWLAX

tWHEH

tELWL

G

tWLWHtGHWL

W

tDVWH

DQ0-DQ7/
DQ8-DQ15

V

CC

tVCHEL

RB

Table 13. Write AC Characteristics, Write Enable Controlled

VALID

tWHRL

Symbol Alt Parameter

t

AVAV

t

ELWL

t

WLWH

t

DVW H

t

WHDX

t

WHEH

t

WHWL

t

AVW L

t

WLAX

t

GHWL

t

WHGL

(1)

t

WHRL

t

VCHEL

1. Sampled only, not 100% tested.

t

WC

t

t

WP

t

t

t

t

WPH

t

t

t

OEH

t

BUSY

t

VCS

Address Valid to Next Address Valid Min 70 90 ns

Chip Enable Low to Write Enable Low Min 0 0 ns

CS

Write Enable Low to Write Enable High Min 45 50 ns

Input Valid to Write Enable High Min 45 50 ns

DS

Write Enable High to Input Transition Min 0 0 ns

DH

Write Enable High to Chip Enable High Min 0 0 ns

CH

Write Enable High to Write Enable Low Min 30 30 ns

Address Valid to Write Enable Low Min 0 0 ns

AS

Write Enable Low to Address Transition Min 45 50 ns

AH

Output Enable High to Write Enable Low Min 0 0 ns

Write Enable High to Output Enable Low Min 0 0 ns

Program/Erase Valid to RB Low Max 30 35 ns

VCC High to Chip Enable Low Min 50 50 µs

tWHGL

tWHWL

tWHDX

AI90199

M29W320D

Unit

70 90

34/56

M29W320DT, M29W320DB DC and AC parameters

Figure 11. Write AC Waveforms, Chip Enable Controlled

tAVAV

A0-A20/
A–1

tAVEL

W

VALID

tELAX

tEHWH

tWLEL

G

tELEHtGHEL

E

tDVEH

DQ0-DQ7/
DQ8-DQ15

V

CC

tVCHWL

RB

Table 14. Write AC Characteristics, Chip Enable Controlled

VALID

tEHRL

Symbol Alt Parameter

t

AVAV

t

WLEL

t

ELEH

t

DVEH

t

EHDX

t

EHWH

t

EHEL

t

AVEL

t

ELAX

t

GHEL

t

EHGL

(1)

t

EHRL

t

VCHWL

1. Sampled only, not 100% tested.

t

WC

t

WS

t

CP

t

DS

t

DH

t

WH

t

CPH

t

AS

t

AH

t

OEH

t

BUSY

t

VCS

Address Valid to Next Address Valid Min 70 90 ns

Write Enable Low to Chip Enable Low Min 0 0 ns

Chip Enable Low to Chip Enable High Min 45 50 ns

Input Valid to Chip Enable High Min 45 50 ns

Chip Enable High to Input Transition Min 0 0 ns

Chip Enable High to Write Enable High Min 0 0 ns

Chip Enable High to Chip Enable Low Min 30 30 ns

Address Valid to Chip Enable Low Min 0 0 ns

Chip Enable Low to Address Transition Min 45 50 ns

Output Enable High Chip Enable Low Min 0 0 ns

Chip Enable High to Output Enable Low Min 0 0 ns

Program/Erase Valid to RB Low Max 30 35 ns

VCC High to Write Enable Low Min 50 50 µs

tEHGL

tEHEL

tEHDX

AI90200

M29W320D

Unit

70 90

35/56

DC and AC parameters M29W320DT, M29W320DB

Figure 12. Reset/Block Temporary Unprotect AC Waveforms

E, G

W,

tPHWL, tPHEL, tPHGL

RB

tRHWL, tRHEL, tRHGL

RP

tPLPX

tPHPHH

tPLYH

AI02931c

Table 15. Reset/Block Temporary Unprotect AC Characteristics

Symbol Alt Parameter

(1)

t

PHWL

t

PHEL

(1)

t

PHGL

(1)

t

RHWL

(1)

t

RHEL

(1)

t

RHGL

t

PLPX

(1)

t

PLYH

(1)

t

PHPHH

(1)

t

VHVPP

1. Sampled only, not 100% tested.

t

RH

t

t

t

READY

t

VIDR

RP High to Write Enable Low, Chip Enable
Low, Output Enable Low

RB High to Write Enable Low, Chip Enable

RB

Low, Output Enable Low

RP Pulse Width Min 500 500 ns

RP

RP Low to Read Mode Max 25 25 µs

RP Rise Time to V

ID

VPP Rise and Fall Time Min 250 250 ns

Figure 13. Accelerated Program Timing Waveforms

V

PP

VPP/WP

M29W320D

Unit

70 90

Min 50 50 ns

Min 0 0 ns

Min 500 500 ns

V

or V

IL

IH

tVHVPP

36/56

tVHVPP

AI90202

M29W320DT, M29W320DB Package mechanical

8 Package mechanical

Figure 14. TSOP48 Lead Plastic Thin Small Outline, 12x20 Mm, Top View Package Outline

1

D1

24

E1

E

DIE

1. Drawing not to scale.

Table 16. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Package Mechanical Data

48

e

B

25

A2

C

CP

L1

A

LA1 α

TSOP-G

millimeters inches

Symbol

Typ Min Max Typ Min Max

A 1.200 0.0472

A1 0.100 0.050 0.150 0.0039 0.0020 0.0059

A2 1.000 0.950 1.050 0.0394 0.0374 0.0413

B 0.220 0.170 0.270 0.0087 0.0067 0.0106

C 0.100 0.210 0.0039 0.0083

CP 0.080 0.0031

D1 12.000 11.900 12.100 0.4724 0.4685 0.4764

E 20.000 19.800 20.200 0.7874 0.7795 0.7953

E1 18.400 18.300 18.500 0.7244 0.7205 0.7283

e 0.500 – – 0.0197 – –

L 0.600 0.500 0.700 0.0236 0.0197 0.0276

L1 0.800 0.0315

a305305

37/56

Package mechanical M29W320DT, M29W320DB

Figure 15. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Bottom View Package Outline

D

D1

SD

SE

ddd

e

FE

E1E

FD

BALL "A1"

e

A

1. Drawing not to scale.

Table 17. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Package Mechanical Data

b

A2

A1

BGA-Z32

millimeters inches

Symbol

Typ Min Max Typ Min Max

A 1.200 0.0472

A1 0.260 0.0102

A2 0.900 0.0354

b 0.350 0.450 0.0138 0.0177

D 6.000 5.900 6.100 0.2362 0.2323 0.2402

D1 4.000 – – 0.1575 – –

ddd 0.100 0.0039

E 8.000 7.900 8.100 0.3150 0.3110 0.3189

E1 5.600 – – 0.2205 – –

e 0.800 – – 0.0315 – –

FD 1.000 – – 0.0394 – –

FE 1.200 – – 0.0472 – –

SD 0.400 – – 0.0157 – –

SE 0.400 – – 0.0157 – –

38/56

M29W320DT, M29W320DB Part numbering

9 Part numbering

Table 18. Ordering Information Scheme

Example: M29W320DB 90 N 1 T

Device Type

M29

Operating Voltage

W = VCC = 2.7 to 3.6V

Device Function

320D = 32 Mbit (x8/x16), Non-Uniform Parameter Blocks,
Boot Block

Array Matrix

T = Top Boot

B = Bottom Boot

Speed

70 = 70 ns

90 = 90 ns

Package

N = TSOP48: 12 x 20 mm

ZE = TFBGA48: 6 x 8mm, 0.8mm pitch

Temperature Range

1 = 0 to 70 °C

6 = –40 to 85 °C

Option

Blank = Standard Packing

T = Tape & Reel Packing

E = ECOPACK Package, Standard Packing

F = ECOPACK Package, Tape & Reel Packing

Devices are shipped from the factory with the memory content bits erased to ’1’.

For a list of available options (Speed, Package, etc...) or for further information on any
aspect of this device, please contact the Numonyx Sales Office nearest to you.

39/56

Block Addresses M29W320DT, M29W320DB

Appendix A Block Addresses

Table 19. Top Boot Block Addresses, M29W320DT

Size

#

(KByte/KWor

d)

66 16/8 3FC000h-3FFFFFh 1FE000h-1FFFFFh

65 8/4 3FA000h-3FBFFFh 1FD000h-1FDFFFh

64 8/4 3F8000h-3F9FFFh 1FC000h-1FCFFFh

63 32/16 3F0000h-3F7FFFh 1F8000h-1FBFFFh

62 64/32 3E0000h-3EFFFFh 1F0000h-1F7FFFh

61 64/32 3D0000h-3DFFFFh 1E8000h-1EFFFFh

60 64/32 3C0000h-3CFFFFh 1E0000h-1E7FFFh

59 64/32 3B0000h-3BFFFFh 1D8000h-1DFFFFh

58 64/32 3A0000h-3AFFFFh 1D0000h-1D7FFFh

57 64/32 390000h-39FFFFh 1C8000h-1CFFFFh

56 64/32 380000h-18FFFFh 1C0000h-1C7FFFh

55 64/32 370000h-37FFFFh 1B8000h-1BFFFFh

54 64/32 360000h-36FFFFh 1B0000h-1B7FFFh

53 64/32 350000h-35FFFFh 1A8000h-1AFFFFh

52 64/32 340000h-34FFFFh 1A0000h-1A7FFFh

51 64/32 330000h-33FFFFh 198000h-19FFFFh

Address Range

(x8)

Address Range

(x16)

50 64/32 320000h-32FFFFh 190000h-197FFFh

49 64/32 310000h-31FFFFh 188000h-18FFFFh

48 64/32 300000h-30FFFFh 180000h-187FFFh

47 64/32 2F0000h-2FFFFFh 178000h-17FFFFh

46 64/32 2E0000h-2EFFFFh 170000h-177FFFh

45 64/32 2D0000h-2DFFFFh 168000h-16FFFFh

44 64/32 2C0000h-2CFFFFh 160000h-167FFFh

43 64/32 2B0000h-2BFFFFh 158000h-15FFFFh

42 64/32 2A0000h-2AFFFFh 150000h-157FFFh

41 64/32 290000h-29FFFFh 148000h-14FFFFh

40 64/32 280000h-28FFFFh 140000h-147FFFh

39 64/32 270000h-27FFFFh 138000h-13FFFFh

38 64/32 260000h-26FFFFh 130000h-137FFFh

37 64/32 250000h-25FFFFh 128000h-12FFFFh

36 64/32 240000h-24FFFFh 120000h-127FFFh

40/56

M29W320DT, M29W320DB Block Addresses

Table 19. Top Boot Block Addresses, M29W320DT (continued)

35 64/32 230000h-23FFFFh 118000h-11FFFFh

34 64/32 220000h-22FFFFh 110000h-117FFFh

33 64/32 210000h-21FFFFh 108000h-10FFFFh

32 64/32 200000h-20FFFFh 100000h-107FFFh

31 64/32 1F0000h-1FFFFFh 0F8000h-0FBFFFh

30 64/32 1E0000h-1EFFFFh 0F0000h-0F7FFFh

29 64/32 1D0000h-1DFFFFh 0E8000h-0EFFFFh

28 64/32 1C0000h-1CFFFFh 0E0000h-0E7FFFh

27 64/32 1B0000h-1BFFFFh 0D8000h-0DFFFFh

26 64/32 1A0000h-1AFFFFh 0D0000h-0D7FFFh

25 64/32 190000h-19FFFFh 0C8000h-0CFFFFh

24 64/32 180000h-18FFFFh 0C0000h-0C7FFFh

23 64/32 170000h-17FFFFh 0B8000h-0BFFFFh

22 64/32 160000h-16FFFFh 0B0000h-0B7FFFh

21 64/32 150000h-15FFFFh 0A8000h-0AFFFFh

20 64/32 140000h-14FFFFh 0A0000h-0A7FFFh

19 64/32 130000h-13FFFFh 098000h-09FFFFh

18 64/32 120000h-12FFFFh 090000h-097FFFh

17 64/32 110000h-11FFFFh 088000h-08FFFFh

16 64/32 100000h-10FFFFh 080000h-087FFFh

15 64/32 0F0000h-0FFFFFh 078000h-07FFFFh

14 64/32 0E0000h-0EFFFFh 070000h-077FFFh

13 64/32 0D0000h-0DFFFFh 068000h-06FFFFh

12 64/32 0C0000h-0CFFFFh 060000h-067FFFh

11 64/32 0B0000h-0BFFFFh 058000h-05FFFFh

10 64/32 0A0000h-0AFFFFh 050000h-057FFFh

9 64/32 090000h-09FFFFh 048000h-04FFFFh

8 64/32 080000h-08FFFFh 040000h-047FFFh

7 64/32 070000h-07FFFFh 038000h-03FFFFh

6 64/32 060000h-06FFFFh 030000h-037FFFh

5 64/32 050000h-05FFFFh 028000h-02FFFFh

4 64/32 040000h-04FFFFh 020000h-027FFFh

3 64/32 030000h-03FFFFh 018000h-01FFFFh

2 64/32 020000h-02FFFFh 010000h-017FFFh

1 64/32 010000h-01FFFFh 008000h-00FFFFh

0 64/32 000000h-00FFFFh 000000h-007FFFh

41/56

Block Addresses M29W320DT, M29W320DB

Table 20. Bottom Boot Block Addresses, M29W320DB

#

Size

(KByte/KWord)

Address Range

(x8)

Address Range

(x16)

66 64/32 3F0000h-3FFFFFh 1F8000h-1FFFFFh

65 64/32 3E0000h-3EFFFFh 1F0000h-1F7FFFh

64 64/32 3D0000h-3DFFFFh 1E8000h-1EFFFFh

63 64/32 3C0000h-3CFFFFh 1E0000h-1E7FFFh

62 64/32 3B0000h-3BFFFFh 1D8000h-1DFFFFh

61 64/32 3A0000h-3AFFFFh 1D0000h-1D7FFFh

60 64/32 390000h-39FFFFh 1C8000h-1CFFFFh

59 64/32 380000h-18FFFFh 1C0000h-1C7FFFh

58 64/32 370000h-37FFFFh 1B8000h-1BFFFFh

57 64/32 360000h-36FFFFh 1B0000h-1B7FFFh

56 64/32 350000h-35FFFFh 1A8000h-1AFFFFh

55 64/32 340000h-34FFFFh 1A0000h-1A7FFFh

54 64/32 330000h-33FFFFh 198000h-19FFFFh

53 64/32 320000h-32FFFFh 190000h-197FFFh

52 64/32 310000h-31FFFFh 188000h-18FFFFh

51 64/32 300000h-30FFFFh 180000h-187FFFh

50 64/32 2F0000h-2FFFFFh 178000h-17FFFFh

49 64/32 2E0000h-2EFFFFh 170000h-177FFFh

48 64/32 2D0000h-2DFFFFh 168000h-16FFFFh

47 64/32 2C0000h-2CFFFFh 160000h-167FFFh

46 64/32 2B0000h-2BFFFFh 158000h-15FFFFh

45 64/32 2A0000h-2AFFFFh 150000h-157FFFh

44 64/32 290000h-29FFFFh 148000h-14FFFFh

43 64/32 280000h-28FFFFh 140000h-147FFFh

42 64/32 270000h-27FFFFh 138000h-13FFFFh

41 64/32 260000h-26FFFFh 130000h-137FFFh

40 64/32 250000h-25FFFFh 128000h-12FFFFh

39 64/32 240000h-24FFFFh 120000h-127FFFh

38 64/32 230000h-23FFFFh 118000h-11FFFFh

37 64/32 220000h-22FFFFh 110000h-117FFFh

36 64/32 210000h-21FFFFh 108000h-10FFFFh

35 64/32 200000h-20FFFFh 100000h-107FFFh

34 64/32 1F0000h-1FFFFFh 0F8000h-0FBFFFh

33 64/32 1E0000h-1EFFFFh 0F0000h-0F7FFFh

42/56

M29W320DT, M29W320DB Block Addresses

Table 20. Bottom Boot Block Addresses, M29W320DB (continued)

32 64/32 1D0000h-1DFFFFh 0E8000h-0EFFFFh

31 64/32 1C0000h-1CFFFFh 0E0000h-0E7FFFh

30 64/32 1B0000h-1BFFFFh 0D8000h-0DFFFFh

29 64/32 1A0000h-1AFFFFh 0D0000h-0D7FFFh

28 64/32 190000h-19FFFFh 0C8000h-0CFFFFh

27 64/32 180000h-18FFFFh 0C0000h-0C7FFFh

26 64/32 170000h-17FFFFh 0B8000h-0BFFFFh

25 64/32 160000h-16FFFFh 0B0000h-0B7FFFh

24 64/32 150000h-15FFFFh 0A8000h-0AFFFFh

23 64/32 140000h-14FFFFh 0A0000h-0A7FFFh

22 64/32 130000h-13FFFFh 098000h-09FFFFh

21 64/32 120000h-12FFFFh 090000h-097FFFh

20 64/32 110000h-11FFFFh 088000h-08FFFFh

19 64/32 100000h-10FFFFh 080000h-087FFFh

18 64/32 0F0000h-0FFFFFh 078000h-07FFFFh

17 64/32 0E0000h-0EFFFFh 070000h-077FFFh

16 64/32 0D0000h-0DFFFFh 068000h-06FFFFh

15 64/32 0C0000h-0CFFFFh 060000h-067FFFh

14 64/32 0B0000h-0BFFFFh 058000h-05FFFFh

13 64/32 0A0000h-0AFFFFh 050000h-057FFFh

12 64/32 090000h-09FFFFh 048000h-04FFFFh

11 64/32 080000h-08FFFFh 040000h-047FFFh

10 64/32 070000h-07FFFFh 038000h-03FFFFh

9 64/32 060000h-06FFFFh 030000h-037FFFh

8 64/32 050000h-05FFFFh 028000h-02FFFFh

7 64/32 040000h-04FFFFh 020000h-027FFFh

6 64/32 030000h-03FFFFh 018000h-01FFFFh

5 64/32 020000h-02FFFFh 010000h-017FFFh

4 64/32 010000h-01FFFFh 008000h-00FFFFh

3 32/16 008000h-00FFFFh 004000h-007FFFh

2 8/4 006000h-007FFFh 003000h-003FFFh

1 8/4 004000h-005FFFh 002000h-002FFFh

0 16/8 000000h-003FFFh 000000h-001FFFh

43/56

Common Flash Interface (CFI) M29W320DT, M29W320DB

Appendix B Common Flash Interface (CFI)

The Common Flash Interface is a JEDEC approved, standardized data structure that can be
read from the Flash memory device. It allows a system software to query the device to
determine various electrical and timing parameters, density information and functions
supported by the memory. The system can interface easily with the device, enabling the
software to upgrade itself when necessary.

When the CFI Query Command is issued the device enters CFI Query mode and the data
structure is read from the memory. Ta bl e 2 1 , Ta bl e 2 2 , Ta bl e 2 3 , Ta bl e 2 4 , Tab le 2 5 and

Ta bl e 2 6 show the addresses used to retrieve the data. The CFI data structure also contains

a security area where a 64 bit unique security number is written (see Ta bl e 2 6 , Security
Code area). This area can be accessed only in Read mode by the final user. It is impossible
to change the security number after it has been written by Numonyx. Issue a Read
command to return to Read mode.

Table 21. Query Structure Overview

Address

x16 x8

Sub-section Name Description

(1)

10h 20h CFI Query Identification String Command set ID and algorithm data offset

1Bh 36h System Interface Information Device timing & voltage information

27h 4Eh Device Geometry Definition Flash device layout

40h 80h Primary Algorithm-specific Extended Query table

61h C2h Security Code Area 64 bit unique device number

1. Query data are always presented on the lowest order data outputs.

Table 22. CFI Query Identification String

Address

x16 x8

10h 20h 0051h “Q”

11h 22h 0052h Query Unique ASCII String "QRY" "R"

12h 24h 0059h "Y"

13h 26h 0002h

14h 28h 0000h

15h 2Ah 0040h

16h 2Ch 0000h

17h 2Eh 0000h

18h 30h 0000h

Data Description Value

Primary Algorithm Command Set and Control Interface ID code 16 bit
ID code defining a specific algorithm

Address for Primary Algorithm extended Query table (see

Alternate Vendor Command Set and Control Interface ID Code
second vendor - specified algorithm supported

(1)

Additional information specific to the Primary
Algorithm (optional)

AMD Compatible

Ta bl e 2 4 ) P = 40h

NA

19h 32h 0000h

1Ah 34h 0000h

1. Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

44/56

Address for Alternate Algorithm extended Query table NA

M29W320DT, M29W320DB Common Flash Interface (CFI)

Table 23. CFI Query System Interface Information

Address

Data Description Value

x16 x8

Logic Supply Minimum Program/Erase voltage

V

CC

1Bh 36h 0027h

bit 7 to 4BCD value in volts
bit 3 to 0BCD value in 100 mV

V

Logic Supply Maximum Program/Erase voltage

CC

1Ch 38h 0036h

bit 7 to 4BCD value in volts
bit 3 to 0BCD value in 100 mV

VPP [Programming] Supply Minimum Program/Erase voltage

1Dh 3Ah 00B5h

bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV

VPP [Programming] Supply Maximum Program/Erase voltage

1Eh 3Ch 00C5h

bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV

1Fh 3Eh 0004h Typical timeout per single byte/word program = 2n µs 16µs

n

20h 40h 0000h Typical timeout for minimum size write buffer program = 2

n

21h 42h 000Ah Typical timeout per individual block erase = 2

22h 44h 0000h Typical timeout for full chip erase = 2

n

ms NA

23h 46h 0005h Maximum timeout for byte/word program = 2

24h 48h 0000h Maximum timeout for write buffer program = 2

25h 4Ah 0004h Maximum timeout per individual block erase = 2

n

26h 4Ch 0000h Maximum timeout for chip erase = 2

times typical NA

ms 1s

n

times typical 512µs

n

times typical NA

n

times typical 16s

µs NA

2.7V

3.6V

11.5V

12.5V

Table 24. Device Geometry Definition

Address

Data Description Value

x16 x8

27h 4Eh 0016h Device Size = 2

28h
29h

2Ah
2Bh

50h
52h

54h
56h

0002h
0000h

0000h
0000h

Flash Device Interface Code description

Maximum number of bytes in multi-byte program or page = 2

Number of Erase Block Regions within the device.

2Ch 58h 0004h

It specifies the number of regions within the device containing
contiguous Erase Blocks of the same size.

2Dh

2Eh

2Fh
30h

5Ah

5Ch

5Eh

60h

0000h
0000h

0040h
0000h

Region 1 Information
Number of identical size erase block = 0000h+1

Region 1 Information
Block size in Region 1 = 0040h * 256 byte

n

in number of bytes 4 MByte

x8, x16

Async.

n

NA

4

1

16 Kbyte

45/56

Common Flash Interface (CFI) M29W320DT, M29W320DB

Table 24. Device Geometry Definition (continued)

Address

Data Description Value

x16 x8

31h
32h

33h
34h

35h
36h

37h
38h

39h
3Ah

3Bh

3Ch

Table 25. Primary Algorithm-Specific Extended Query Table

62h
64h

66h
68h

6Ah
6Ch

6Eh

70h

72h
74h

76h
78h

0001h
0000h

0020h
0000h

0000h
0000h

0080h
0000h

003Eh
0000h

0000h
0001h

Region 2 Information
Number of identical size erase block = 0001h+1

Region 2 Information
Block size in Region 2 = 0020h * 256 byte

Region 3 Information
Number of identical size erase block = 0000h+1

Region 3 Information
Block size in Region 3 = 0080h * 256 byte

Region 4 Information
Number of identical-size erase block = 003Eh+1

Region 4 Information
Block size in Region 4 = 0100h * 256 byte

Address

Data Description Value

x16 x8

40h 80h 0050h

41h 82h 0052h "R"

Primary Algorithm extended Query table unique ASCII string “PRI”

42h 84h 0049h "I"

43h 86h 0031h Major version number, ASCII "1"

44h 88h 0030h Minor version number, ASCII "0"

2

8 Kbyte

1

32 Kbyte

63

64 Kbyte

"P"

Address Sensitive Unlock (bits 1 to 0)

45h 8Ah 0000h

00 = required, 01= not required
Silicon Revision Number (bits 7 to 2)

46h 8Ch 0002h

47h 8Eh 0001h

48h 90h 0001h

49h 92h 0004h

Erase Suspend
00 = not supported, 01 = Read only, 02 = Read and Write

Block Protection
00 = not supported, x = number of blocks in per group

Temporary Block Unprotect
00 = not supported, 01 = supported

Block Protect /Unprotect
04 = M29W400B

4Ah 94h 0000h Simultaneous Operations, 00 = not supported No

4Bh 96h 0000h Burst Mode, 00 = not supported, 01 = supported No

4Ch 98h 0000h

Page Mode, 00 = not supported, 01 = 4 page word, 02 = 8 page
word

46/56

Ye s

2

1

Ye s

4

No

M29W320DT, M29W320DB Common Flash Interface (CFI)

Table 25. Primary Algorithm-Specific Extended Query Table (continued)

Address

Data Description Value

x16 x8

V

Supply Minimum Program/Erase voltage

PP

4Dh 9Ah 00B5h

4Eh 9Ch 00C5h

bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV

VPP Supply Minimum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV

11.5V

12.5V

4Fh 9Eh 000xh

Table 26. Security Code Area

Address

Data Description

x16 x8

61h C3h, C2h XXXX

62h C5h, C4h XXXX

63h C7h, C6h XXXX

64h C9h, C8h XXXX

Top/Bottom Boot Block Flag
02h = Bottom Boot device, 03h = Top Boot device

64 bit: unique device number

–

47/56

Block Protection M29W320DT, M29W320DB

Appendix C Block Protection

Block protection can be used to prevent any operation from modifying the data stored in the
Flash. Each Block can be protected individually. Once protected, Program and Erase
operations on the block fail to change the data.

There are three techniques that can be used to control Block Protection, these are the
Programmer technique, the In-System technique and Temporary Unprotection. Temporary
Unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP
described in the Signal Descriptions section.

Unlike the Command Interface of the Program/Erase Controller, the techniques for
protecting and unprotecting blocks change between different Flash memory suppliers. For
example, the techniques for AMD parts will not work on Numonyx parts. Care should be
taken when changing drivers for one part to work on another.

C.1 Programmer Technique

The Programmer technique uses high (VID) voltage levels on some of the bus pins. These
cannot be achieved using a standard microprocessor bus, therefore the technique is
recommended only for use in Programming Equipment.

; this is

To protect a block follow the flowchart in Figure 16: Programmer Equipment Block Protect

Flowchart. To unprotect the whole chip it is necessary to protect all of the blocks first, then

all blocks can be unprotected at the same time. To unprotect the chip follow Figure 17:

Programmer Equipment Chip Unprotect Flowchart. Table 27: Programmer Technique Bus
Operations, BYTE = V

The timing on these flowcharts is critical. Care should be taken to ensure that, where a
pause is specified, it is followed as closely as possible. Do not abort the procedure before
reaching the end. Chip Unprotect can take several seconds and a user message should be
provided to show that the operation is progressing.

or VIL, gives a summary of each operation.

IH

C.2 In-System Technique

The In-System technique requires a high voltage level on the Reset/Blocks Temporary
Unprotect pin, RP
components on the microprocessor bus, therefore this technique is suitable for use after the
Flash has been fitted to the system.

To protect a block follow the flowchart in Figure 18: In-System Equipment Block Protect

Flowchart. To unprotect the whole chip it is necessary to protect all of the blocks first, then

all the blocks can be unprotected at the same time. To unprotect the chip follow Figure

Figure 19: In-System Equipment Chip Unprotect Flowchart.

The timing on these flowcharts is critical. Care should be taken to ensure that, where a
pause is specified, it is followed as closely as possible. Do not allow the microprocessor to
service interrupts that will upset the timing and do not abort the procedure before reaching
the end. Chip Unprotect can take several seconds and a user message should be provided
to show that the operation is progressing.

. This can be achieved without violating the maximum ratings of the

48/56

M29W320DT, M29W320DB Block Protection

Table 27. Programmer Technique Bus Operations, BYTE = VIHor V

Operation E G W

Block Protect V

Chip Unprotect V

Block Protection
Verify

Block Unprotection
Verify

Address Inputs

A0-A20

ILVIDVIL

IDVIDVIL

Pulse

Pulse

A9 = VID, A12-A20 Block Address

Others = X

A9 = V

, A12 = VIH, A15 = VIH

ID

Others = X

A0 = VIL, A1 = VIH, A6 = VIL, A9 = VID,

V

V

IL

V

IL

IH

A12-A20 Block Address

Others = X

A0 = VIL, A1 = VIH, A6 = VIH,

V

V

IL

V

IL

IH

A9 = VID, A12-A20 Block Address

Others = X

IL

Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

X

X

Pass = XX01h

Retry = XX00h

Retry = XX01h

Pass = XX00h

49/56

Block Protection M29W320DT, M29W320DB

Figure 16. Programmer Equipment Block Protect Flowchart

START

ADDRESS = BLOCK ADDRESS

W = V

IH

n = 0

G, A9 = VID,

E = V

IL

Wait 4µs

W = V

IL

Wait 100µs

W = V

IH

Verify Protect Set-upEnd

E, G = VIH,

A0, A6 = VIL,

A1 = V

IH

E = V

IL

Wait 4µs

G = V

IL

Wait 60ns

Read DATA

DATA

=

01h

YES

A9 = V

IH

E, G = V

IH

PASS

NO

++n

= 25

A9 = V

E, G = V

NO

YES

IH

IH

50/56

FAIL

AI03469

M29W320DT, M29W320DB Block Protection

Figure 17. Programmer Equipment Chip Unprotect Flowchart

START

PROTECT ALL BLOCKS

CURRENT BLOCK = 0

ADDRESS = CURRENT BLOCK ADDRESS

n = 0

A6, A12, A15 = V

E, G, A9 = V

Wait 4µs

W = V

Wait 10ms

W = V

E, G = V

A0 = VIL, A1, A6 = V

E = V

Wait 4µs

IH

ID

IL

IH

IH

IL

(1)

IH

Verify Unprotect Set-upEnd

G = V

IL

Wait 60ns

Read DATA

=

00h

YESNO

DATA

++n

NO

= 1000

YES

A9 = V

IH

E, G = V

IH

FAIL PASS

51/56

CURRENT BLOCK

LAST

BLOCK

YES

A9 = V

IH

E, G = V

IH

INCREMENT

NO

AI03470

Block Protection M29W320DT, M29W320DB

Figure 18. In-System Equipment Block Protect Flowchart

START

n = 0

RP = V

ID

Verify Protect Set-upEnd

ADDRESS = BLOCK ADDRESS

ADDRESS = BLOCK ADDRESS

ADDRESS = BLOCK ADDRESS

ADDRESS = BLOCK ADDRESS

WRITE 60h

A0 = VIL, A1 = VIH, A6 = V

WRITE 60h

A0 = VIL, A1 = VIH, A6 = V

Wait 100µs

WRITE 40h

A0 = VIL, A1 = VIH, A6 = V

Wait 4µs

READ DATA

A0 = VIL, A1 = VIH, A6 = V

DATA

RP = V

=

01h

NO

YES

IH

IL

IL

IL

IL

++n

= 25

NO

ISSUE READ/RESET

COMMAND

PASS

52/56

YES

RP = V

IH

ISSUE READ/RESET

COMMAND

FAIL

AI03471

M29W320DT, M29W320DB Block Protection

Figure 19. In-System Equipment Chip Unprotect Flowchart

START

PROTECT ALL BLOCKS

n = 0

CURRENT BLOCK = 0

RP = V

ID

WRITE 60h

ANY ADDRESS WITH

A0 = VIL, A1 = VIH, A6 = V

WRITE 60h

ANY ADDRESS WITH

A0 = VIL, A1 = VIH, A6 = V

Wait 10ms

IH

IH

Verify Unprotect Set-upEnd

ADDRESS = CURRENT BLOCK ADDRESS

++n

NO

= 1000

YES

RP = V

IH

ISSUE READ/RESET

COMMAND

FAIL

ADDRESS = CURRENT BLOCK ADDRESS

A0 = VIL, A1 = VIH, A6 = V

A0 = VIL, A1 = VIH, A6 = V

WRITE 40h

Wait 4µs

READ DATA

DATA

=

00h

IH

IH

YESNO

INCREMENT

CURRENT BLOCK

LAST

BLOCK

RP = V

ISSUE READ/RESET

COMMAND

PASS

NO

YES

IH

AI03472

53/56

Revision history M29W320DT, M29W320DB

10 Revision history

Table 28. Document revision history

Date Revision Changes

March-2001 -01 First Issue (Brief Data)

08-Jun-2001 -02 Document expanded to full Product Preview

22-Jun-2001 -03

27-Jul-2001 -04

05-Oct-2001 -05

07-Feb-2002 -06 TFBGA package changed from 48 ball to 63 ball

05-Apr-2002 -07

19-Nov-2002 7.1

26-May-2003 7.2

Minor text corrections to Read/Reset and Read CFI commands and
Status Register Error and Toggle Bits.

Document type: from Product Preview to Preliminary Data
TFBGA connections and Block Addresses (x16) diagrams

clarification
Write Protect and Block Unprotect clarification
CFI Primary Algorithm table, Block Protection change

Added Block Protection Appendix
“Write Protect/V

consistent with abbreviation. Changes to the V

Figure 13 and Ta bl e 1 5 . IPP added to Ta b le 11 and I

” pin renamed to “VPP/Write Protect” to be

PP

/WP pin description,

PP

CC3

clarified.
Modified description of VPP/WP operation in Unlock Bypass
Command section. Added V

/WP decoupling capacitor to Figure

PP

Figure 1.

Clarified Read/Reset operation during Erase Suspend.

Description of Ready/Busy signal clarified (and Figure 12 modified)
Clarified allowable commands during block erase
Clarified the mode the device returns to in the CFI Read Query

command section

Erase Suspend Latency Time (typical and maximum) added to
Program, Erase Times and Program, Erase Endurance Cycles table.

Typical values added for Icc1 and Icc2 in DC characteristics table.
Logic Diagram and Data Toggle Flowchart corrected.
Revision numbering modified: a minor revision will be indicated by

incrementing the digit after the dot, and a major revision, by
incrementing the digit before the dot (revision version 07 equals 7.0).
Document promoted to full datasheet.

Data Retention added to Table 6: Program, Erase Times and

Program, Erase Endurance Cycles, and Typical after 100k W/E

Cycles column removed. TSOP48 package mechanical updated.
Lead-free package options E and F added to Table 18: Ordering

Information Scheme.

16-Aug-2005 8.0 TFBGA48 package added throughout document.

54/56

M29W320DT, M29W320DB Revision history

Table 28. Document revision history (continued)

Date Revision Changes

Document title modified.
TFBGA63 package removed. ECOPACK text added.

signal updated in Figure 12: Reset/Block Temporary Unprotect

13-Jun-2006 9

26-Mar-2008 10 Applied Numonyx branding.

RB

AC Waveforms. t
Unprotect AC Characteristics.

In Table 7: Status Register Bits, DQ7 changed to DQ7
Program during Erase Suspend and Program Error.

updated in Table 15: Reset/Block Temporary

PLYH

for Program,

55/56

M29W320DT, M29W320DB

Please Read Carefully:

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR

IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT

AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY

WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF

NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,

MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility

Numonyx may make changes to specifications and product descriptions at any time, without notice.

Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,

by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves

these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by

visiting Numonyx's website at http://www.numonyx.com.

Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.

*Other names and brands may be claimed as the property of others.

Copyright © 11/5/7, Numonyx, B.V., All Rights Reserved.

applications.

56/56