Numonyx M29W320DT, M29W320DB Technical data
32 Mbit (4Mbx8 or 2Mbx16, Non-uniform Parameter Blocks,
Feature summary
■ Supply Voltage
–V
–V
■ Access time: 70, 90ns
■ Programming time
– 10µs per Byte/Word typical
■ 67 memory blocks
– 1 Boot Block (Top or Bottom Location)
– 2 Parameter and 64 Main Blocks
■ Program/Erase controller
– Embedded Byte/Word Program algorithms
■ Erase Suspend and Resume modes
– Read and Program another Block during
■ Unlock Bypass Program command
– Faster Production/Batch Programming
■ V
PP
■ Temporary Block Unprotection mode
■ Common Flash Interface
– 64 bit Security code
■ Low power consumption
– Standby and Automatic Standby
■ 100,000 Program/Erase cycles per block
■ Electronic Signature
– Manufacturer Code: 0020h
– Top Device Code M29W320DT: 22CAh
– Bottom Device Code M29W320DB: 22CBh
■ ECOPACK
2.7V to 3.6V for Program, Erase and
CC =
Read
=12V for Fast Program (optional)
PP
Erase Suspend
/WP pin for Fast Program and Write Protect
®
packages available
M29W320DT
M29W320DB
Boot Block), 3V Supply Flash memory
TSOP48 (N)
12 x 20mm
FBGA
TFBGA48 (ZE)
March 2008 Rev 10 1/56
www.numonyx.com
1
Contents M29W320DT, M29W320DB
Contents
1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 Address Inputs (A0-A20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2 Data Inputs/Outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 Data Inputs/Outputs (DQ8-DQ14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4 Data Input/Output or Address Input (DQ15A–1) . . . . . . . . . . . . . . . . . . . 12
2.5 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.6 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.7 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.8 V
2.9 Reset/Block Temporary Unprotect (RP
Write Protect (V
PP/
WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PP/
) . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.10 Ready/Busy Output (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.11 Byte/Word Organization Select (BYTE) . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.12 V
2.13 V
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
CC
Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SS
3 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5 Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6 Special bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6.1 Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6.2 Block Protect and Chip Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4 Command Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2 Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3 Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.4 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/56
M29W320DT, M29W320DB Contents
4.5 Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.6 Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.7 Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.8 Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.9 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.10 Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.11 Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.12 Block Protect and Chip Unprotect commands . . . . . . . . . . . . . . . . . . . . . 21
5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1 Data Polling Bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.2 Toggle Bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3 Error Bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.4 Erase Timer Bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.5 Alternative Toggle Bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Appendix A Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Appendix B Common Flash Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Appendix C Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
C.1 Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
C.2 In-System Technique. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3/56
List of tables M29W320DT, M29W320DB
List of tables
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2. Bus Operations, BYTE = V
Table 3. Bus Operations, BYTE = V
Table 4. Commands, 16-bit mode, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 5. Commands, 8-bit mode, BYTE = V
Table 6. Program, Erase Times and Program, Erase Endurance Cycles. . . . . . . . . . . . . . . . . . . . . 24
Table 7. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 8. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 9. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 10. Device Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 11. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 12. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 13. Write AC Characteristics, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 14. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 15. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 16. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Package Mechanical Data. . . . . . . 37
Table 17. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Package Mechanical Data . . . . . . . . . . 38
Table 18. Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 19. Top Boot Block Addresses, M29W320DT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 20. Bottom Boot Block Addresses, M29W320DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 21. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 22. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 23. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 24. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 25. Primary Algorithm-Specific Extended Query Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 26. Security Code Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 27. Programmer Technique Bus Operations, BYTE = V
Table 28. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
IL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
IH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
IL
or V
IH
IL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4/56
M29W320DT, M29W320DB List of figures
List of figures
Figure 1. Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. TFBGA48 Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. Block Addresses (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. Block Addresses (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 7. Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 8. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 9. Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 10. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 11. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 12. Reset/Block Temporary Unprotect AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 13. Accelerated Program Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 14. TSOP48 Lead Plastic Thin Small Outline, 12x20 Mm, Top View Package Outline . . . . . . 37
Figure 15. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Bottom View Package Outline . . . . . . . 38
Figure 16. Programmer Equipment Block Protect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 17. Programmer Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 18. In-System Equipment Block Protect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 19. In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5/56
Summary description M29W320DT, M29W320DB
1 Summary description
The M29W320D is a 32 Mbit (4Mb x8 or 2Mb x16) non-volatile memory that can be read,
erased and reprogrammed. These operations can be performed using a single low voltage
(2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode where it can be
read in the same way as a ROM or EPROM.
The memory is divided into blocks that can be erased independently so it is possible to
preserve valid data while old data is erased. Each block can be protected independently to
prevent accidental Program or Erase commands from modifying the memory. Program and
Erase commands are written to the Command Interface of the memory. An on-chip
Program/Erase Controller simplifies the process of programming or erasing the memory by
taking care of all of the special operations that are required to update the memory contents.
The end of a program or erase operation can be detected and any error conditions
identified. The command set required to control the memory is consistent with JEDEC
standards.
The blocks in the memory are asymmetrically arranged, see Figure 4 and Figure 5, Ta b l e 1 9
and Ta bl e 2 0 . The first or last 64 Kbytes have been divided into four additional blocks. The
16 Kbyte Boot Block can be used for small initialization code to start the microprocessor, the
two 8 Kbyte Parameter Blocks can be used for parameter storage and the remaining 32
Kbyte is a small Main Block where the application may be stored.
Chip Enable, Output Enable and Write Enable signals control the bus operation of the
memory. They allow simple connection to most microprocessors, often without additional
logic.
The memory is offered in TSOP48 (12 x 20mm), and TFBGA48 (6x8mm, 0.8mm pitch)
packages. In order to meet environmental requirements, Numonyx offers the M29W320D in
ECOPACK
Interconnect is marked on the package and on the inner box label, in compliance with
JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also
marked on the inner box label.
The memory is supplied with all the bits erased (set to 1).
®
packages. ECOPACK packages are Lead-free. The category of second Level
6/56
M29W320DT, M29W320DB Summary description
Figure 1. Logic Diagram
VPP/WP
V
CC
21
15
A0-A20
W
E
M29W320DT
M29W320DB
G
RP
BYTE
V
SS
Table 1. Signal Names
A0-A20 Address Inputs
DQ0-DQ7 Data Inputs/Outputs
DQ8-DQ14 Data Inputs/Outputs
DQ15A–1 Data Input/Output or Address Input
E
Chip Enable
DQ0-DQ14
DQ15A–1
RB
AI90189B
G
W
RP
RB
BYTE
V
CC
V
/WP VPP/Write Protect
PP
V
SS
Output Enable
Write Enable
Reset/Block Temporary Unprotect
Ready/Busy Output
Byte/Word Organization Select
Supply Voltage
Ground
NC Not Connected Internally
7/56
Summary description M29W320DT, M29W320DB
Figure 2. TSOP Connections
A15
1
48
A14
A13
A12
A11
A10 DQ14
A9
A8
A19
A20
W
RP
NC
12
M29W320DT
M29W320DB
13
37
36
VPP/WP
RB
A18
A17
A7
A6
A5
A4
A3
A2
24 25
A1
AI90190
A16
BYTE
V
SS
DQ15A–1
DQ7
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
V
SS
E
A0
8/56
M29W320DT, M29W320DB Summary description
Figure 3. TFBGA48 Connections (Top view through package)
654321
A
B
C
D
E
F
G
H
A3
A4
A2
A1
A0
E
G
V
SS
A7
A17
A6
A5 A20
DQ0
DQ8
DQ9
DQ1
RB
V
PP
A18
DQ2
DQ10
DQ11
DQ3
/
WP
W
RP
NC
A19
DQ5
DQ12
V
CC
DQ4
A9
A8
A10
A11
DQ7
DQ14
DQ13
DQ6
A13
A12
A14
A15
A16
BYTE
DQ15
A–1
V
SS
AI08084
9/56
Summary description M29W320DT, M29W320DB
Figure 4. Block Addresses (x8)
M29W320DT
Top Boot Block Addresses (x8)
Bottom Boot Block Addresses (x8)
M29W320DB
3FFFFFh
3FC000h
3FBFFFh
3FA000h
3F9FFFh
3F8000h
3F7FFFh
3F0000h
3EFFFFh
3E0000h
01FFFFh
010000h
00FFFFh
000000h
16 KByte
8 KByte
8 KByte
32 KByte
64 KByte
Total of 63
64 KByte Blocks
64 KByte
64 KByte
3FFFFFh
3F0000h
3EFFFFh
3E0000h
01FFFFh
010000h
00FFFFh
008000h
007FFFh
006000h
005FFFh
004000h
003FFFh
000000h
64 KByte
64 KByte
64 KByte
32 KByte
8 KByte
8 KByte
16 KByte
1. Also see Appendix A: Block Addresses, Table 19 and Table 20 for a full listing of the Block Addresses.
Total of 63
64 KByte Blocks
AI90192
10/56
M29W320DT, M29W320DB Summary description
Figure 5. Block Addresses (x16)
Top Boot Block Addresses (x16)
M29W320DT
Bottom Boot Block Addresses (x16)
M29W320DB
1FFFFFh
1FE000h
1FDFFFh
1FD000h
1FCFFFh
1FC000h
1FBFFFh
1F8000h
1F7FFFh
1F0000h
00FFFFh
008000h
007FFFh
000000h
8 KWord
4 KWord
4 KWord
16 KWord
32 KWord
Total of 63
32 KWord Blocks
32 KWord
32 KWord
1FFFFFh
1F8000h
1F7FFFh
1F0000h
00FFFFh
008000h
007FFFh
004000h
003FFFh
003000h
002FFFh
002000h
001FFFh
000000h
32 KWord
32 KWord
Total of 63
32 KWord Blocks
32 KWord
16 KWord
4 KWord
4 KWord
8 KWord
AI90193
1. Also see Appendix Appendix A: Block Addresses, Table 19 and Table 20 for a full listing of the Block Addresses.
11/56
Signal descriptions M29W320DT, M29W320DB
2 Signal descriptions
See Figure 1: Logic Diagram, and Table 1: Signal Names, for a brief overview of the signals
connected to this device.
2.1 Address Inputs (A0-A20)
The Address Inputs select the cells in the memory array to access during Bus Read
operations. During Bus Write operations they control the commands sent to the Command
Interface of the internal state machine.
2.2 Data Inputs/Outputs (DQ0-DQ7)
The Data I/O outputs the data stored at the selected address during a Bus Read operation.
During Bus Write operations they represent the commands sent to the Command Interface
of the internal state machine.
2.3 Data Inputs/Outputs (DQ8-DQ14)
The Data I/O outputs the data stored at the selected address during a Bus Read operation
when BYTE
impedance. During Bus Write operations the Command Register does not use these bits.
When reading the Status Register these bits should be ignored.
is High, VIH. When BYTE is Low, VIL, these pins are not used and are high
2.4 Data Input/Output or Address Input (DQ15A–1)
When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14).
When BYTE
LSB of the Word on the other addresses, DQ15A–1 High will select the MSB. Throughout
the text consider references to the Data Input/Output to include this pin when BYTE
and references to the Address Inputs to include this pin when BYTE
stated explicitly otherwise.
is Low, VIL, this pin behaves as an address pin; DQ15A–1 Low will select the
is Low except when
2.5 Chip Enable (E)
The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to
be performed. When Chip Enable is High, V
, all other pins are ignored.
IH
2.6 Output Enable (G)
The Output Enable, G, controls the Bus Read operation of the memory.
is High
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M29W320DT, M29W320DB Signal descriptions
2.7 Write Enable (W)
The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface.
2.8 V
The VPP/Write Protect pin provides two functions. The VPP function allows the memory to
use an external high voltage power supply to reduce the time required for Unlock Bypass
Program operations. The Write Protect function provides a hardware method of protecting
the 16 Kbyte Boot Block. The V
When V
and Erase operations in this block are ignored while V
When V
of the 16 Kbyte boot block. Program and Erase operations can now modify the data in the 16
Kbyte Boot Block unless the block is protected using Block Protection.
When V
Bypass mode. When V
During Unlock Bypass Program operations the memory draws I
programming circuits. See the description of the Unlock Bypass command in the Command
Interface section. The transitions from V
t
Never raise V
memory may be left in an indeterminate state.
A 0.1µF capacitor should be connected between the V
Ground pin to decouple the current surges from the power supply. The PCB track widths
must be sufficient to carry the currents required during Unlock Bypass Program, I
Write Protect (VPP/WP)
PP/
/Write Protect is Low, VIL, the memory protects the 16 Kbyte Boot Block; Program
PP
/Write Protect is High, VIH, the memory reverts to the previous protection status
PP
/Write Protect is raised to V
PP
, see Figure 13.
VHVPP
/Write Protect to VPP from any mode except Read mode, otherwise the
PP
/Write Protect returns to VIH or VIL normal operation resumes.
PP
/Write Protect pin must not be left floating or unconnected.
PP
/Write Protect is Low.
PP
the memory automatically enters the Unlock
PP
from the pin to supply the
PP
to VPP and from VPP to VIH must be slower than
IH
/Write Protect pin and the VSS
PP
.
PP
2.9 Reset/Block Temporary Unprotect (RP)
The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the
memory or to temporarily unprotect all Blocks that have been protected.
Note that if V
even if RP is at V
A Hardware Reset is achieved by holding Reset/Block Temporary Unprotect Low, V
least t
PLPX
ready for Bus Read and Bus Write operations after t
See the Ready/Busy Output section, Tab le 1 5 and Figure 12, for more details.
Holding RP
and Erase operations on all blocks will be possible. The transition from V
slower than t
/WP is at VIL, then the 16 KByte outermost boot block will remain protect
PP
.
ID
. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be
PHEL
at VID will temporarily unprotect the protected Blocks in the memory. Program
.
PHPHH
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or t
, whichever occurs last.
RHEL
to VID must be
IH
, for at
IL
Signal descriptions M29W320DT, M29W320DB
2.10 Ready/Busy Output (RB)
The Ready/Busy pin is an open-drain output that can be used to identify when the device is
performing a Program or Erase operation. During Program or Erase operations Ready/Busy
is Low, V
Erase Suspend mode.
. Ready/Busy is high-impedance during Read mode, Auto Select mode and
OL
Note that if V
even if RP is at V
/WP is at VIL, then the 16 KByte outermost boot block will remain protect
PP
.
ID
After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy
becomes high-impedance. See Tab l e 1 5 and Figure 12.
The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the
memories is busy.
2.11 Byte/Word Organization Select (BYTE)
The Byte/Word Organization Select pin is used to switch between the x8 and x16 Bus
modes of the memory. When Byte/Word Organization Select is Low, V
x8 mode, when it is High, V
, the memory is in x16 mode.
IH
2.12 VCC Supply Voltage
VCC provides the power supply for all operations (Read, Program and Erase).
The Command Interface is disabled when the V
Voltage, V
. This prevents Bus Write operations from accidentally damaging the data
LKO
during power up, power down and power surges. If the Program/Erase Controller is
programming or erasing during this time then the operation aborts and the memory contents
being altered will be invalid.
Supply Voltage is less than the Lockout
CC
, the memory is in
IL
A 0.1µF capacitor should be connected between the V
Ground pin to decouple the current surges from the power supply. The PCB track widths
must be sufficient to carry the currents required during Program and Erase operations, I
2.13 VSS Ground
VSS is the reference for all voltage measurements.
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Supply Voltage pin and the VSS
CC
CC3
.
M29W320DT, M29W320DB Bus operations
3 Bus operations
There are five standard bus operations that control the device. These are Bus Read, Bus
Write, Output Disable, Standby and Automatic Standby. See Ta bl e 2 and Tab le 3 , Bus
operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write
Enable are ignored by the memory and do not affect bus operations.
3.1 Bus Read
Bus Read operations read from the memory cells, or specific registers in the Command
Interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs, applying a Low signal, V
Enable High, V
AC Waveforms, and Table 12: Read AC Characteristics, for details of when the output
becomes valid.
3.2 Bus Write
Bus Write operations write to the Command Interface. A valid Bus Write operation begins by
setting the desired address on the Address Inputs. The Address Inputs are latched by the
Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs
last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of
Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, V
during the whole Bus Write operation. See Figure 10 and Figure 11, Write AC waveforms,
and Ta bl e 1 3 and Tab le 1 4, Write AC Characteristics, for details of the timing requirements.
. The Data Inputs/Outputs will output the value, see Figure 9: Read Mode
IH
, to Chip Enable and Output Enable and keeping Write
IL
IH
,
3.3 Output Disable
The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH.
3.4 Standby
When Chip Enable is High, VIH, the memory enters Standby mode and the Data
Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to
the Standby Supply Current, I
Standby current level see Table 11: DC Characteristics.
During program or erase operations the memory will continue to use the Program/Erase
Supply Current, I
, for Program or Erase operations until the operation completes.
CC3
3.5 Automatic Standby
If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 300ns or
more the memory enters Automatic Standby where the internal Supply Current is reduced to
the Standby Supply Current, I
Read operation is in progress.
, Chip Enable should be held within V
CC2
. The Data Inputs/Outputs will still output data if a Bus
CC2
15/56
± 0.2V. For the
CC
Bus operations M29W320DT, M29W320DB
3.6 Special bus operations
Additional bus operations can be performed to read the Electronic Signature and also to
apply and remove Block Protection. These bus operations are intended for use by
programming equipment and are not usually used in applications. They require V
applied to some pins.
3.6.1 Electronic Signature
The memory has two codes, the manufacturer code and the device code, that can be read
to identify the memory. These codes can be read by applying the signals listed in Ta bl e 2
and Ta bl e 3 , Bus Operations.
3.6.2 Block Protect and Chip Unprotect
Each block can be separately protected against accidental Program or Erase. The whole
chip can be unprotected to allow the data inside the blocks to be changed.
Block Protect and Chip Unprotect operations are described in Appendix C: Block Protection.
Table 2. Bus Operations, BYTE = V
Operation E G W
(1)
IL
Address Inputs
DQ15A–1, A0-A20
Data Inputs/Outputs
DQ14-DQ8 DQ7-DQ0
to be
ID
Bus Read V
Bus Write V
Output Disable X V
Standby V
Read Manufacturer
Code
V
Read Device Code V
1. X = VIL or VIH.
Table 3. Bus Operations, BYTE = V
V
IL
V
IL
IH
V
IL
V
IL
VIHCell Address Hi-Z Data Output
IL
VILCommand Address Hi-Z Data Input
IH
VIHX Hi-Z Hi-Z
IH
X X X Hi-Z Hi-Z
V
IL
IL
IH
V
IH
Operation E G W
Bus Read V
Bus Write V
Output Disable X V
Standby V
Read Manufacturer
Code
V
Read Device Code V
1. X = VIL or VIH.
V
IL
V
IL
IH
V
IL
V
IL
VIHCell Address Data Output
IL
VILCommand Address Data Input
IH
VIHXHi-Z
IH
XXX Hi-Z
V
IL
IL
IH
V
IH
A0 = VIL, A1 = VIL, A9 = VID,
Others VIL or V
IH
A0 = VIH, A1 = VIL,
A9 = V
(1)
IH
, Others VIL or V
ID
Address Inputs
A0-A20
A0 = VIL, A1 = VIL, A9 = VID,
Others VIL or V
IH
A0 = VIH, A1 = VIL, A9 = VID,
Others V
IL
or V
IH
Hi-Z 20h
IH
Hi-Z
CAh (M29W320DT)
CBh (M29W320DB)
Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
0020h
22CAh (M29W320DT)
22CBh (M29W320DB)
16/56
M29W320DT, M29W320DB Command Interface
4 Command Interface
All Bus Write operations to the memory are interpreted by the Command Interface.
Commands consist of one or more sequential Bus Write operations. Failure to observe a
valid sequence of Bus Write operations will result in the memory returning to Read mode.
The long command sequences are imposed to maximize data security.
The address used for the commands changes depending on whether the memory is in 16bit or 8-bit mode. See either Ta b le 4 , or Tab le 5 , depending on the configuration that is being
used, for a summary of the commands.
4.1 Read/Reset command
The Read/Reset command returns the memory to its Read mode where it behaves like a
ROM or EPROM, unless otherwise stated. It also resets the errors in the Status Register.
Either one or three Bus Write operations can be used to issue the Read/Reset command.
The Read/Reset Command can be issued, between Bus Write cycles before the start of a
program or erase operation, to return the device to read mode. Once the program or erase
operation has started the Read/Reset command is no longer accepted. The Read/Reset
command will not abort an Erase operation when issued while in Erase Suspend.
4.2 Auto Select command
The Auto Select command is used to read the Manufacturer Code, the Device Code and the
Block Protection Status. Three consecutive Bus Write operations are required to issue the
Auto Select command. Once the Auto Select command is issued the memory remains in
Auto Select mode until a Read/Reset command is issued. Read CFI Query and Read/Reset
commands are accepted in Auto Select mode, all other commands are ignored.
From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation
with A0 = V
Manufacturer Code for Numonyx is 0020h.
The Device Code can be read using a Bus Read operation with A0 = V
other address bits may be set to either V
22CAh and for the M29W320DB is 22CBh.
The Block Protection Status of each block can be read using a Bus Read operation with A0
= V
, A1 = VIH, and A12-A20 specifying the address of the block. The other address bits
IL
may be set to either V
Data Inputs/Outputs DQ0-DQ7, otherwise 00h is output.
and A1 = VIL. The other address bits may be set to either VIL or VIH. The
IL
or VIH. If the addressed block is protected then 01h is output on
IL
and A1 = VIL. The
or VIH. The Device Code for the M29W320DT is
IL
IH
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