Numonyx M29W040B Technical data

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Low Voltage Single Supply Flash Memory

■ SINGLE 2.7 to 3.6V SUPPLY VOLTAGE for

PROGRAM, ERASE and READ OPE RATI ONS

■ ACCESS TIME: 55ns

■ PROGRAMMING TIME

– 10µs per Byte typical

■ 8 UNIFORM 64 Kbytes MEMORY BLOCKS

■ PROGRAM/ERASE CONTROLLER

– Embedded Byte Program algorithm – Embedded Multi-Block/Chip Erase algorithm – Status Register Polling and Toggle Bits

■ ERASE SUSPEND and RESUME MODES

– Read and Program another Block during

Erase Suspend

■ UNLOCK BYPASS PROGRAM COMMAND

– Faster Production/Batch Programming

■ LOW POWER CONSUMPTION

– Standby and Automatic Standby

■ 100,000 PROGRAM/ERASE CYCLES per

BLOCK

■ 20 YEARS DATA RETENTION

– Defectivity below 1 ppm/year

■ ELECTRONIC SIGNATURE

– Manufacturer Code : 20h – Device Code: E3h

■ ECOPACK

PACKAGES AVAILABLE

M29W040B

4 Mbit (512Kb x8, Uniform Block)

PLCC32 (K)

TSOP32 (NZ)

8 x 14mm

Figure 1. Logic Diagram

A0-A18

TSOP32 (N)

8 x 20mm

DQ0-DQ7

M29W040B

AI02953

1/20September 2005

M29W040B

Figure 2. PLCC Connections

A16

A7 A6 A5 A4 A3 A2 A1 A0

DQ0

A12

DQ1

A18

A15

M29W040B

DQ2

DQ3

DQ4

DQ5

A17

DQ6

A14 A13 A8 A9 A11 G A10 E DQ7

AI02951

Figure 3. TSOP Connections

A11 G

A8 A13 A14 A17

A18 A16 A15 A12

A4 A3

M29W040B

16 17

25 24

AI02952

A10 E DQ7 DQ6 DQ5 DQ4 DQ3 V

DQ2 DQ1 DQ0 A0 A1 A2

Table 1. Signal Names

A0-A18 Address Inputs DQ0-DQ7 Data Inputs/Outputs E G W V V

Chip Enable Output Enable Write Enable Supply Voltage Ground

SUMMARY DESCRIPTION

The M29W040B is a 4 Mbit ( 512Kb x 8) non-v olatile memory that c an be read, erased and r eprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. On power-up the memory default s to its Read mode where it can be read in the same way as a ROM or EPROM. The M29W040B is fully backward compatible with the M29W040.

The memory is divided into blocks that can be erased independently s o i t is po ss ible to preserve valid data while old data is erased. Each block can be protected independen tly to prevent accidental

Program or Erase com mands from modifying the memory. Program and Erase co mmands are written to the Command Int erface of th e memory . An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation ca n be detected and any error conditions ide nti fie d. T he co mma nd set required to control the memory is consistent with JEDEC standards.

Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic.

The memory is offered in TSOP32 (8 x 20mm), TSOP32 (8 x 14mm) and PLC C32 packag es and it is supplied with all the bits erased (set to ‘1’).

In order to meet environme ntal requirements, ST offers the M29W040B in ECOPACK

packages.

ECOPACK packages are Lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDE C Stand ard JESD 97. The m aximum ratings related to soldering conditions are also marked on the inner box label.

ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

2/20

M29W040B

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

BIAS

STG

(2)

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may

cause permanent damage to the device. Thes e are str ess ratin gs only and oper at ion of the device at thes e or any ot her condi tio ns above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect dev ice reliability. Refer also to the S TMicroelectronics SURE Progr am and other relevant quality documents.

2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.

Ambient Operating Temperature (Temperature Range Option 1) 0 to 70 °C Ambient Operating Temperature (Temperature Range Option 6) –40 to 85 °C Temperature Under Bias –50 to 125 °C Storage Temperature –65 to 150 °C

Input or Output Voltage –0.6 to 4 V Supply Voltage –0.6 to 4 V

Identification Voltage –0.6 to 13.5 V

Table 3. Uniform Block Addresses, M29W040B

7 64 70000h-7FFFFh 6 64 60000h-6FFFFh 5 64 50000h-5FFFFh 4 64 40000h-4FFFFh 3 64 30000h-3FFFFh 2 64 20000h-2FFFFh 1 64 10000h-1FFFFh 0 64 00000h-0FFFFh

Size

(Kbytes)

Address Range

(1)

Chip Enable (E

). The Chip Enable, E, activates

the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, V

Output Enable (G

, all other pins are ignored.

). The Output Enable , G, con-

trols the Bus Read operation of the memory.

Write Enable (W

). The Write Enable, W, controls

the Bus Write operation of the memory’s Command Interface.

Supply Voltage. The VCC Supply Voltage

supplies the power for all operations (Read, Program, Erase etc.).

The Command Interface is disabled when the V

Supply Voltage is le ss than the Lockout Vo ltage, V

. This prevents Bus Write operations from ac-

SIGNAL DESCRIPTIONS

See Figure 1, Logic Diag ra m, an d T ab le 1 , Signal Names, for a brief overview of the signals connected to this device.

Address Inputs (A0-A18). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands

LKO

cidentally damaging the data during power-up, power-down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid.

A 0.1µF capacitor sh ould be connected between the V

Supply Voltage pin and the VSS Ground

pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, I

Ground. The VSS Ground is the reference for

CC3

all voltage measurements.

sent to the Command Interface of the internal state machine.

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M29W040B

BUS OPERATIONS

There are five standard bus operations that control the device. These are Bus Read, Bus Writ e, Output Disable, Standby and Automatic Standby. See Table 4, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip En able or Write Enable are ignored by the m emo ry and do not affect bus operations.

Bus Read. Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low s ig nal, V

, to Chip Enable

and Output Enable and keeping Write Enable High, V

. The Data Inputs/Outputs will ou tpu t the

value, see the Figure 8, Read Mode AC Waveforms, and Table 11, Read AC Characteristics, for details of when the output becomes valid.

Bus Write. Bus Write operations write to the Command Interface. A v alid Bus Write operati on begins by setting the desired address on the Address Inputs. The Ad dress Inputs are latched b y the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs ar e latched by the Com mand Interface on the rising ed ge of Chip Enab le or Write Enable, whichever occurs first. Output Enable must remain High, V

, during the whole Bus

Write operation . See Figures 9 and 10 Write AC Waveforms, and Tables 12 and 13, Write AC Characteristics, for details of the timing requirements.

Output Disable. The Data Inputs /Outputs are in the high impedance state when Output Enable is High, V

Standby. When Chip Enable is High, V

, the memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-impedance state. To reduce the Su pply Current to the Standby Supply Current, I be held within V

± 0.2V. For the Standby current

, Chip Enable should

CC2

level see Table 10, DC Characteristics. During program or eras e operations the memory

will continue to use the Program/Erase Supply Current, I

, for Program or Erase operations un-

CC3

til the operation completes. Automatic Standby. If CMOS levels (V

± 0.2V)

are used to drive the bus and the bus is inactive for 150ns or more the memory enters Automatic Standby where the interna l Supply Current is reduced to the Standby Supply Current, I

CC2

. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress.

Special Bus Operations

Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus operations are intended for us e by progr ammin g equip ment and are not usually used in applications. They require V

to be applied to some pins.

Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can b e read b y apply ing the sig nals listed in Table 4, Bus Operations.

Block Protection and Blocks Unprotection. Each block can be separately protected against accidental Program or Erase. Protected blocks can be unprotected to allow data to be changed. Block Protection and Blocks Unprotection operations must only be performed on programming equip ment. For further informa tion refer to Application Note AN1122, Applying Protectio n and Unpr otection to M29 Series Flash.

Table 4. Bus Operations

Operation E G W Address Inputs

Bus Read Bus Write Output Disable Standby Read Manufacturer

Code

Read Device Code

Note: X = VIL or VIH.

4/20

XVIHV

X X X Hi-Z

Data

Inputs/Outputs

V V

Cell Address Data Output

Command Address Data Input

X Hi-Z

A0 = VIL, A1 = VIL, A9 = VID,

Others VIL or V A0 = VIL, A1 = VIL, A9 = VID,

Others VIL or V

20h

E3h

M29W040B

COMMAND INTERFACE

All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operation s will result in the memory return ing to Read mode. The long command sequences are imposed to maximize data security.

The commands are summarized in Table 5, Commands. Refer to Table 5 in conjunction with the text descriptions below.

Read/Reset Command. The Read/Reset command returns the memory to its Read mode where it behaves lik e a ROM or EPROM. I t also resets the errors in the Status Register. Either one or three Bus Write o perations can be us ed to issue the Read/Reset command.

If the Read/Reset command is issued during a Block Erase operation or following a Programming or Erase error then the memory will take upto 10

µs

to abort. During the abort period no valid data can be read from the memory. Issu ing a Read/Reset command during a Block Erase operation will leave invalid data in the memory.

Auto Select Command. The Auto Select command is used to read t he Manu facturer Code, the Device Code and the Block Protection Status. Three consecutive Bus Write operations are required to issue the Auto Sel ect command. Once the Auto Select comman d is issued the memory remains in Auto Sele ct mode until another command is issued.

From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = V may be set to either V

and A1 = VIL. The other address bits

or VIH. The Manufacturer

Code for STMicroelectronics is 20h. The Device Code can be read using a Bu s Read

operation with A0 = V address bits may be s et to either V

and A1 = VIL. The other

or VIH. The

Device Code for the M29W040B is E3h. The Block Protectio n Statu s of ea ch block c an be

read using a Bus Read ope ration with A0 = V A1 = V

, and A16, A17 and A18 specifying the ad-

dress of the block. The ot her add re ss bi ts may be set to either V

or VIH. If the address ed block is

protected then 01h is ou tput on the Data Inputs/ Outputs, otherwise 00h is output.

Program Command. The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller.

If the address falls in a protect ed block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given.

During the program operation th e memory will ig nore all commands. It is no t possib le to is sue any command to abort or pause the operation. Typical program times are given in Table 6. Bus Read operations during the p rogram operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details.

After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Statu s Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.

Note that the Program command cannot change a bit set at ‘0’ back t o ‘1’. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from ‘0’ to ‘1’.

Unlock Bypass Command. The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory. When the access time to the device is long (as with some EPROM programmers) considerable time saving can be made by using these commands. Three Bu s Write operations are r equired to issue the Unlock Bypass command.

Once the Unlock Bypass c ommand has been issued the memory will only accept the Unlock Bypass Program com mand and the Unlock B ypass Reset command. The memory can be read as if in Read mode.

Unlock Bypass Program Command. The Unlock Bypass Program command can be used to program one address in memory at a time. The command requires t wo Bus Write oper ations, the final write operati on lat ches the a ddress and d ata in the internal state machine and starts the Program/Erase Controller.

The Program operation us ing the Unlock Bypass

Program command behaves identically to the Program operation using the Program command. A protected block cannot be progra mme d; the op eration cannot be aborted and the Status Register is read. Errors must be reset using th e Read/Reset command, which leav es the device in Unlock Bypass Mode. See the Program command for details on the behavior.

Unlock Bypass Reset Command. The Unlock Bypass Reset comm and can b e used to return to Read/Reset mode from Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command.

5/20

M29W040B

Table 5. Commands

Bus Write Operations

Command

Read/Reset

Auto Select 3 555 AA 2AA 55 555 90 Program 4 555 AA 2AA 55 555 A0 PA PD Unlock Bypass 3 555 AA 2AA 55 555 20 Unlock Bypass

Program Unlock Bypass Reset 2 X 90 X 00 Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30 Erase Suspend 1 X B0 Erase Resume 1 X 30

Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal.

The Command Interface only uses address bits A0-A10 to verify the commands , t he upper address bits are Don’t Care.

Read/Reset. After a Read/Reset c ommand, read the memory as normal until anoth er command is issued. Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Statu s. Program, Unlock Bypass Pr o gr am, Chip Erase, Block Erase. After these commands read the Status Register until the Program/Erase

Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional Bus Write Operations until the Timeout Bit is set.

Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands. Unlock Bypass Reset. After the Unlock By pass Reset command read the memory as normal until another command is issued. Erase Suspend. After the Erase Suspend co mmand read non-erasing memory blocks as nor mal, issue Auto Select and P rogram commands

on non-erasing blocks as normal. Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/

Erase Controller completes and the memory returns to Read Mode.

1X F0 3555 AA2AA 55 X F0

2 X A0 PA PD

1st 2nd 3rd 4th 5th 6th

Length

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Chip Erase Command. The Chip Erase com-

mand can be used to erase the entire chip. Six Bus Write operations are required to issue the Chip Erase Command and start the Program/Erase Controller.

If any blocks are protected then these are ignored and all the other blocks are erased. If all of the blocks are protected the Chip Erase operation appears to start but will terminate within about 100µs, leaving the data unc hanged . No er ror con dition is given when protected blocks are ignored.

During the erase operation the memory will ignore all commands. It is not possible to issue any command to abort the operation. Typical chip erase

6/20

times are given in Table 6. All Bus Read operations during the Chip E rase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details.

After the Chip Erase o per at ion has c om ple ted the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Statu s Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode.

The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ‘1’. All previous data is lost.

M29W040B

Block Erase Command. The Block Erase com-

mand can be used to erase a l ist of one or more blocks. Six Bus W rite operations are required to select the first block in the list. Each additional block in the list can be select ed by repeating the sixth Bus Write operation using the address of the additional block. The Bloc k Er as e op erati on st ar ts the Program/Erase Controller about 50µs after the last Bus Write operation. Once the Program/Erase Controller starts it is not possible to select any more blocks. Each additional block must therefore be selected within 50µs of the last block. The 50µs timer restarts when an additional block is selected. The Status Register can be read after the sixth Bus Write operation. See the Status Register for details on how to identify if the Program/Erase Controller has started the Block Erase operation.

If any selected blocks are protected then these are ignored and all the other selected blocks are erased. If all of the sel ected blocks are pr otected the Block Erase operation appears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored.

During the Block Eras e o perat ion the memory will ignore all comman ds except the Erase Suspend and Read/Reset commands . Typical block erase times are given in Table 6. All Bus Read operations during the B lock Erase op eration will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details.

After the Block Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Statu s Regis-

ter. A Read/Reset command must be issued to reset the error condition and return to Read mode.

The Block Erase Comma nd sets all of the bits in the unprotected selected blocks to ‘1’. All previous data in the selected blocks is lost.

Erase Suspend Command. The Erase S u sp en d Command may be used to tempor arily suspend a Block Erase operation a nd return the memory to Read mode. The command requires one Bus Write operation.

The Program/Erase Control ler will sus pend with in 15µs of the Erase Suspend Command being issued. Once the Program/Erase Controller has stopped the memory will be set to Read mode and the Erase will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additiona l block (before the Program/Erase Controller starts) then the Erase is suspende d i mme di atel y and will start immediately when the Eras e Resume Command is issued. It will not be possib le to select an y further blocks for erasure after the Erase Resume.

During Erase Suspend i t is possible to Read and Program cells in blocks that are not being erased; both Read and Program operations behave as normal on these bloc ks. Re adi ng fro m b lock s t hat are being erased will output the Status Register. It is also possible to enter the Auto Select mode: the memory wil l behav e as in t he Auto Select mo de on all blocks until a Read/Reset command returns the memory to Erase Suspend mode.

Erase Resume Command. The Erase Resume command must be used to restart the Program/ Erase Controller from Erase Suspend. An erase can be suspended and resumed more than once.

Table 6. Program, Erase Times and Program, Erase Endurance Cycles

= 0 to 70°C or –40 to 85°C)

Parameter Min

Chip Erase (All bits in the memory set to ‘0’) 2.5 2.5 sec Chip Erase 6 6 35 se c Block Erase (64 Kbytes) 0.8 0.8 6 sec Program 10 10 200 µs Chip Program 5.5 5.5 30 sec Program/Erase Cycles (per Block) 100,000 cycles

Note: 1. TA = 25°C, VCC = 3.3V.

Typ

(1)

Typical after

100k W/E Cycles

(1)

Max Unit

7/20

M29W040B

STATUS REGISTER

Bus Read operations from any address always read the Status Register during Program and Erase operations. It is also read during Erase Suspend when an address within a block being erased is accessed.

The bits in the Status R egi st er are s umm ar iz ed in Table 7, Status Register Bits.

Data Polling Bit (DQ7). The Data Polling Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has respond ed to an Erase Suspend. The Data Polling Bit is output on DQ7 whe n the Status Register is read.

During Program operations the Data Polling Bit outputs the complement of the bit being programmed to DQ7. After successful completion of the Program operation the memory returns to Read mode and Bus Read operations from the address just programm ed output DQ7, not its complement.

During Erase operations the Data Polli ng Bit outputs ‘0’, the complement of the erased state of DQ7. After su ccess ful co mpl etion of t he Er ase o peration the memory returns to Read mode.

In Erase Suspend mode the Data Polli ng Bit will output a ‘1’ during a Bus Rea d operation withi n a block being erased. The Data Polling Bit will change from a ‘0’ to a ‘1’ when the Program/Erase Controller has suspended the Erase operation.

Figure 3, Data Polling Flowc hart, gives an exam ple of how to use the Data Po lling Bit. A Valid Address is the address being programmed or an address within the block being erased.

Toggle Bit (DQ6). The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The To ggle Bit is output on DQ6 when the Status Register is read.

During Program and Er ase oper ations the Togg le Bit changes from ‘0’ to ‘1 ’ to ‘0’, etc., with succes sive Bus Read operations at any address. After successful completion of the operation the memory returns to Read mode.

During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has suspended the Erase operation.

Figure 4, Data To ggle Flowchart, gives an example of how to use the Data Toggle Bit.

Error Bit (DQ5). The Error Bit can be used to identify errors detected by the Program/Erase Controller. The Error Bit is set to ‘1’ when a Program, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error Bit is set a Read/Reset command mus t be issu ed before other comma nds are issued. The Error bit is output on DQ5 when the Status Register is read.

Note that the Program command cannot change a bit set at ‘0’ back to ‘1’ and attempting to do so may or may not set DQ5 at ‘1’. I n both cases, a su ccessive Bus Read operation will show the bit is still ‘0’. One of the Erase comma nds m ust b e use d to s et all the bits in a block or in the whole memory from ‘0’ to ‘1’.

Table 7. Status Register Bits

Operation Address DQ7 DQ6 DQ5 DQ3 DQ2

Program Any Address DQ7 Program During Erase

Suspend Program Error Any Address DQ7 Chip Erase Any Address 0 Togg le 0 1 Toggle

Block Erase before timeout

Block Erase

Erase Suspend

Erase Error

Note: Unspecified data bits should be ignored.

8/20

Any Address DQ7

Erasing Block 0 Toggle 0 0 Toggle

Non-Erasing Block 0 Toggle 0 0 No Toggle

Erasing Block 0 Toggle 0 1 Toggle

Non-Erasing Block 0 Toggle 0 1 No Toggle

Erasing Block 1 No Toggle 0 – Toggle

Non-Erasing Block Data read as normal Good Block Address 0 Toggle 1 1 No Toggle Faulty Block Address 0 Toggle 1 1 Toggle

Toggle 0 – –

Toggle 1 – –

M29W040B

Figure 4. Data Polling Flowchart

START

READ DQ5 & DQ7

at VALID ADDRESS

DQ7

DATA

DQ5

READ DQ7

at VALID ADDRESS

DQ7

DATA

FAIL PASS

= 1

YES

AI03598

Figure 5. Data Toggle Flowchart

START

READ

DQ5 & DQ6

READ DQ6

DQ6

TOGGLE

DQ5

= 1

READ DQ6

TWICE

DQ6

TOGGLE

FAIL PASS

YES

AI01370B

Erase Timer Bi t (DQ3). The Erase Ti mer Bit c an be used to identify the start of Program/Erase Controller operation during a Block Erase command. Once the Program/Erase Controller starts erasing the Erase Timer Bit is set to ‘1’. Before the Program/Erase Contro ller starts the Erase Timer Bit is set to ‘0’ a nd additiona l blocks t o be eras ed may be written to the Command Interface. The Erase Timer Bit is output on DQ3 when the Status Register is read.

Alternative Toggle Bit (DQ2). The Alternative Toggle Bit can be u sed to monitor the Program/ Erase controller d uring Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is read.

During Chip Erase and Block Erase operations the Toggle Bit changes from ‘0 ’ to ‘1’ to ‘0’, etc., wi th successive Bus Rea d operations from ad dresses

within the blocks being erased. Once the operation completes the memory returns to Read mode.

During Erase Suspend the Alternative Toggle Bit changes from ‘0’ to ‘1’ to ‘0’, etc. with successive Bus Read operations from addresses within the blocks being erased . Bus Read operations to addresses within blocks not b ei ng e rase d wi ll output the memory cell data as if in Read mode.

After an Erase o per at ion th at ca us es th e Er ror B it to be set the Alternative Toggle Bit can be used to identify which block or blocks have caused the error. The Alternative Toggle Bit changes from ‘0’ to ‘1’ to ‘0’, etc. with successive Bus Read Operations from addresses with in blocks that have not erased correctly. Th e Alternative Toggle B it does not change if the addressed block has erased correctly.

9/20

M29W040B

Table 8. AC Measurement Conditions

Parameter

55 70 90 / 120

Supply Voltage

Load Capacitance (C

)

3.0 to 3.6V 2.7 to 3.6V 2.7 to 3.6V 30pF 30pF 100pF

Input Rise and Fall Times ≤ 10ns ≤ 10ns ≤ 10ns Input Pulse Voltages 0 to 3V 0 to 3V 0 to 3V Input and Output Timing Ref. Voltages 1.5V 1.5V 1.5V

M29W040B

Figure 6. AC Testing Input Output Waveform

1.5V

AI01417

Figure 7. AC Testing Load Circuit

0.8V

1N914

3.3kΩ

DEVICE UNDER

TEST

CL = 30pF or 100pF

CL includes JIG capacitance

Table 9. Capacitance (T

= 25 °C, f = 1 MHz)

Symbol Parameter Test Condition Min Max Unit

OUT

= 0V

6pF

12 pF

OUT

Note: Sampled only, not 100% tested.

Input Capacitanc e Output Capacitance

OUT

AI02762

10/20

Table 10. DC Characteristics

= 0 to 70°C or –40 to 85°C)

Symbol Parameter Test Condition Min

Input Leakage Current

CC1

CC2

CC3

V V V

LKO

Note: 1. Sampled only, not 100% tested.

Output Leakage Curr en t

Supply Current (Read ) Supply Current (Stan dby)

(1)

Supply Current (Program /Eras e)

Input Low Voltage –0.5 0.8 V

Input High Voltage

Output Low Voltage

Output High Voltage

Identification Voltage 11.5 12.5 V

Identification Current

Program/Erase Lockout Supply

(1)

Voltage

2. T

= 25°C, VCC = 3.3V.

0V ≤ V

≤ V

0V ≤ V

= VIL, G = VIH, f = 6MHz

= VCC ± 0.2V

OUT

≤ V

Program/Erase

Controller active

= 1.8mA

= –100µA VCC – 0.4

A9 = V

0.7V

M29W040B

(2)

Typ.

410mA

30 100 µA

1.8 2.3 V

Max Unit

±1 µA ±1 µA

20 mA

VCC + 0.3

0.45 V

100 µA

11/20

M29W040B

Table 11. Read AC Characteristics

= 0 to 70°C or –40 to 85°C)

Symbol Alt Parameter Test Condition

AVQV

ELQX

AVAV

Address Valid to Next Add res s Valid

(1)

Address Valid to Output Valid

ACC

Chip Enable Low to Output

Transition

= VIL,

G = V

= VIL,

G = V

= V

M29W040B

Unit

55 70 90 / 120

Min 55 70 90 ns

Max 55 70 90 ns

Min000ns

ELQV

(1)

GLQX

GLQV

(1)

EHQZ

GHQZ

EHQX

GHQX

AXQX

Note: 1. Sampled only, not 100% tested.

(1)

Chip Enable Low to Output Valid

Output Enable Low to Output

OLZ

Transition

Output Enable Low to Output Valid

Chip Enable High to Output Hi-Z

Output Enable High to Output Hi-Z

Chip Enable, Output Enable or

Address Transition to Output

Transition

Figure 8. Read Mode AC Waveforms

A0-A18

tAVQV tAXQX

tAVAV VALID

E G

= V

= V = V

= V

Max 55 70 90 ns

Min000ns

Max 30 30 35 ns

Max 20 25 30 ns

Min000ns

12/20

DQ0-DQ7

tELQV

tELQX tEHQZ

tGLQX tGHQX

tGLQV

tGHQZ

VALID

tEHQX

AI02903

Table 12. Write AC Characteristics, Write Enable Controlled

= 0 to 70°C or –40 to 85°C)

Symbol Alt Parameter

AVAV

ELWL

WLWH

DVWH

WHDX

WHEH

WHWL

AVWL

WLAX

GHWL

WHGL

VCHEL

WPH

OEH

VCS

Address Valid to Next Address Valid Min 55 70 90 ns Chip Enable Low to Write Enable Low Min 0 0 0 ns Write Enable Low to Write Enable High Min 40 45 45 ns Input Valid to Write Enable High Min 25 30 45 ns Write Enable High to Input Transition Min 0 0 0 ns Write Enable High to Chip Enable High Min 0 0 0 ns Write Enable High to Write Enable Low Min 30 30 30 ns Address Valid to Write Enable Low Min 0 0 0 ns Write Enable Low to Address Transition Min 40 45 45 ns Output Enable High to Write Enable Low Min 0 0 0 ns Write Enable High to Output Enable Low Min 0 0 0 ns VCC High to Chip Enable Low

M29W040B

Unit

55 70 90 / 120

Min505050µs

Figure 9. Write AC Waveforms, Write Enable Controlled

tAVAV

A0-A18

DQ0-DQ7

tAVWL

tELWL

tVCHEL

VALID

tWLWHtGHWL

tDVWH

tWLAX

tWHEH

tWHGL

tWHWL

tWHDX

VALID

AI02908

13/20

M29W040B

Table 13. Write AC Characteristics, Chip Enable Controlled

= 0 to 70°C or –40 to 85°C)

Symbol Alt Parameter

AVAV

WLEL

ELEH

DVEH

EHDX

EHWH

EHEL

AVEL

ELAX

GHEL

EHGL

VCHWL

t t t t

CPH

OEH

VCS

Address Valid to Next Address Valid Min 55 70 90 ns Write Enable Low to Chip Enable Low Min 0 0 0 ns Chip Enable Low to Chip Enable High Min 40 45 45 n s

Input Valid to Chip Enable High Min 25 30 45 ns

Chip Enable High to Input Transition Min 0 0 0 ns

Chip Enable High to Write Enable High Min 0 0 0 ns Chip Enable High to Chip Enable Low Min 30 30 30 ns Address Valid to Chip Enable Low Min 0 0 0 ns

Chip Enable Low to Address Transition Min 40 45 45 ns

Output Enable High Chip Enable Low Min 0 0 0 ns Chip Enable High to Output Enable Low Min 0 0 0 ns VCC High to Write Enable Low

M29W040B Unit

55 70 90 / 120

Min505050µs

Figure 10. Write AC Waveforms, Chip Enable Controlled

tAVAV

A0-A18

DQ0-DQ7

tAVEL

tWLEL

tVCHWL

VALID

tELEHtGHEL

tDVEH

tELAX

tEHWH

tEHGL

tEHEL

tEHDX

VALID

AI02909

14/20

Table 14. Ordering Information Scheme

Example: M29W040B 55 N 1 T

Device Type

M29

Operating Voltage

W = VCC = 2.7 to 3.6V

Device Function

040B = 4 Mbit (512Kb x8), Uniform Block

Speed

55 = 55 ns 70 = 70 ns 90 = 90 ns 120 = 120 ns

Package

K = PLCC32 N = TSOP32: 8 x 20 mm NZ = TSOP32: 8 x 14 mm

M29W040B

Temperature Range

1 = 0 to 70 °C 6 = –40 to 85 °C

Option

Blank = Standard Packing T = Tape & Reel Packing E = ECOPACK Package, Standard Packing F = ECOPACK Package, Tape & Reel Packing

Note: The last two characters of th e ordering cod e may be r eplaced by a letter code for preprogr ammed parts, otherwise devices are shipped from the factory with the memory content bits erased to ‘1’.

For a list of availa ble opt ion s (Spe ed, Pac k age , et c... ) or for fu r ther i nfo rm ati on o n a ny aspec t o f th is de vice, please contact the ST Sales Office nearest to you.

15/20

M29W040B

Table 15. PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Mechanical Data

Symbol

Typ Min Max Typ Min Max

A 3.18 3.56 0.125 0.140 A1 1.53 2.41 0.060 0.095 A2 0.38 – 0.015 –

B 0.33 0.53 0.013 0.021 B1 0.66 0.81 0.026 0.032

CP 0.10 0.004

D 12.32 12.57 0.485 0.495 D1 11.35 11.51 0.447 0.453 D2 4.78 5.66 0.188 0.223 D3 7.62 – – 0.300 – –

E 14.86 15.11 0.585 0.595 E1 13.89 14.05 0.547 0.553 E2 6.05 6.93 0.238 0.273 E310.16– –0.400– –

e 1.27 – – 0.050 – –

F 0.00 0.13 0.000 0.005 N32 32 R 0.89 – – 0.035 – –

millimeters inches

Figure 11. PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Outline

Note: Drawing is not to scale.

1 N

D2 D2

E1 E

0.51 (.020)

1.14 (.045)

A1 A2

PLCC-A

16/20

M29W040B

Table 16. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Mechanical Data

Symbol

Typ Min Max Typ Min Max

A1.200.0472

A1 0.05 0.15 0.0020 0.0059 A2 0.95 1.05 0.0374 0.0413

B 0.15 0.27 0.0059 0.0106 C 0.10 0.21 0.0039 0.0083 D 19.80 20.20 0.7795 0.7953

D1 18.30 18.50 0.7205 0.7283

E 7.90 8.10 0.3110 0.3189

e 0.50 – – 0.0197 – –

L 0.50 0.70 0.0197 0.0276

α 0° 5° 0° 5° N32 32

CP 0.10 0.0039

millimeters inches

Figure 12. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Outline

N/2

DIE

TSOP-a

Note: Drawing is not to scale.

LA1 α

17/20

M29W040B

Table 17. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 14mm, Package Mechanical Data

Symbol

Typ Min Max Typ Min Max

A1.200.0472

A1 0.05 0.15 0.0020 0.0059 A2 0.95 1.05 0.0374 0.0413

B 0.17 0.27 0.0067 0.0106 C 0.10 0.21 0.0039 0.0083 D 13.80 14.20 0.5433 0.5591

D1 12.30 12.50 0.4843 0.4921

E 7.90 8.10 0.3110 0.3189

e 0.50 – – 0.0197 – –

L 0.50 0.70 0.0197 0.0276

α 0° 5° 0° 5° N32 32

CP 0.10 0.0039

millimeters inches

Figure 13. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 14mm, Package Outline

Note: Drawing is not to scale.

1 N

N/2

DIE

TSOP-a

LA1 α

18/20

Table 18. Revision History

Date Rev. Revision Details

July 1999 -01 First Issue

Typ. specification added (Table 10)

21-Sep-1999 -02

09-Mar-2000 -03

22-Apr-2002 -04 PLCC32 package mechanical data modified

19-Sep-2005 5.0

CC1

Typ. specification added (Table 10)

CC2

Document type: from Preliminary Data to Data Sheet Status Register bit DQ5 clarification Data Polling Flowchart diagram change (Figure 4) Data Toggle Flowchart diagram change (Figure 5)

Table 14. Order in g Infor m atio n Scheme: standard package ad de d and ECO PACK version added for both standard package and Tape & Reel packing.

M29W040B

19/20

M29W040B

Information furnished is be lieved to be a ccur ate and reli able. Howe ver, STMicroele ctronic s assu mes no r esponsib ilit y for th e consequences of use of such information nor for any infrin gement of patent s or other rights of third parties which ma y result from it s use. No license is granted

by implication or otherwi se under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without not ice. This pub licat ion su persed es and repl aces all in format ion previou sly su pplie d. STMicroele c tronic s prod ucts a re no t

authorized for use as critical compone nts in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners

STMicroelectronics group of companies

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www.st.com

20/20

Numonyx M29W040B Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

Figure 1. Logic Diagram

Figure 2. PLCC Connections

Figure 3. TSOP Connections

Table 1. Signal Names

SUMMARY DESCRIPTION

Table 3. Uniform Block Addresses, M29W040B

SIGNAL DESCRIPTIONS

Address Inputs (A0-A18). The Address Inputs select the cells in the memory array to access dur­ing Bus Read operations. During Bus Write opera­tions they control the commands sent to the Command Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ7). The Data In­puts/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands

BUS OPERATIONS

Bus Read. Bus Read operations read from the memory cells, or specific registers in the Com­mand Interface. A valid Bus Read operation in­volves setting the desired address on the Address Inputs, applying a Low s ig nal, V

Output Disable. The Data Inputs /Outputs are in the high impedance state when Output Enable is High, V

Standby. When Chip Enable is High, V

til the operation completes. Automatic Standby. If CMOS levels (V

Special Bus Operations

Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can b e read b y apply ing the sig nals listed in Table 4, Bus Operations.

Table 4. Bus Operations

COMMAND INTERFACE

Read/Reset Command. The Read/Reset com­mand returns the memory to its Read mode where it behaves lik e a ROM or EPROM. I t also resets the errors in the Status Register. Either one or three Bus Write o perations can be us ed to issue the Read/Reset command.

Program Command. The Program command can be used to program a value to one address in the memory array at a time. The command re­quires four Bus Write operations, the final write op­eration latches the address and data in the internal state machine and starts the Program/Erase Con­troller.

Unlock Bypass Reset Command. The Unlock Bypass Reset comm and can b e used to return to Read/Reset mode from Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command.

Table 5. Commands

on non-erasing blocks as normal. Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/

Chip Erase Command. The Chip Erase com-

Block Erase Command. The Block Erase com-

Erase Suspend Command. The Erase S u sp en d Command may be used to tempor arily suspend a Block Erase operation a nd return the memory to Read mode. The command requires one Bus Write operation.

Erase Resume Command. The Erase Resume command must be used to restart the Program/ Erase Controller from Erase Suspend. An erase can be suspended and resumed more than once.

STATUS REGISTER

Data Polling Bit (DQ7). The Data Polling Bit can be used to identify whether the Program/Erase Controller has successfully completed its opera­tion or if it has respond ed to an Erase Suspend. The Data Polling Bit is output on DQ7 whe n the Status Register is read.

Toggle Bit (DQ6). The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has re­sponded to an Erase Suspend. The To ggle Bit is output on DQ6 when the Status Register is read.

Table 7. Status Register Bits

Figure 4. Data Polling Flowchart

Figure 5. Data Toggle Flowchart

Alternative Toggle Bit (DQ2). The Alternative Toggle Bit can be u sed to monitor the Program/ Erase controller d uring Erase operations. The Al­ternative Toggle Bit is output on DQ2 when the Status Register is read.

Table 8. AC Measurement Conditions

Figure 6. AC Testing Input Output Waveform

Figure 7. AC Testing Load Circuit

Figure 8. Read Mode AC Waveforms

Figure 9. Write AC Waveforms, Write Enable Controlled

Figure 10. Write AC Waveforms, Chip Enable Controlled

Table 14. Ordering Information Scheme

Table 15. PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Mechanical Data

Figure 11. PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Outline

Table 16. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Mechanical Data

Figure 12. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Outline

Table 17. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 14mm, Package Mechanical Data

Figure 13. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 14mm, Package Outline

Table 18. Revision History

Address Inputs (A0-A18). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands

Bus Read. Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low s ig nal, V

Read/Reset Command. The Read/Reset command returns the memory to its Read mode where it behaves lik e a ROM or EPROM. I t also resets the errors in the Status Register. Either one or three Bus Write o perations can be us ed to issue the Read/Reset command.

Program Command. The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller.

Data Polling Bit (DQ7). The Data Polling Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has respond ed to an Erase Suspend. The Data Polling Bit is output on DQ7 whe n the Status Register is read.

Toggle Bit (DQ6). The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The To ggle Bit is output on DQ6 when the Status Register is read.

Alternative Toggle Bit (DQ2). The Alternative Toggle Bit can be u sed to monitor the Program/ Erase controller d uring Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is read.