Numonyx M29W040B Technical data

Low Voltage Single Supply Flash Memory

■ SINGLE 2.7 to 3.6V SUPPLY VOLTAGE for

PROGRAM, ERASE and READ OPE RATI ONS

■ ACCESS TIME: 55ns

■ PROGRAMMING TIME

– 10µs per Byte typical

■ 8 UNIFORM 64 Kbytes MEMORY BLOCKS

■ PROGRAM/ERASE CONTROLLER

– Embedded Byte Program algorithm – Embedded Multi-Block/Chip Erase algorithm – Status Register Polling and Toggle Bits

■ ERASE SUSPEND and RESUME MODES

– Read and Program another Block during

Erase Suspend

■ UNLOCK BYPASS PROGRAM COMMAND

– Faster Production/Batch Programming

■ LOW POWER CONSUMPTION

– Standby and Automatic Standby

■ 100,000 PROGRAM/ERASE CYCLES per

BLOCK

■ 20 YEARS DATA RETENTION

– Defectivity below 1 ppm/year

■ ELECTRONIC SIGNATURE

– Manufacturer Code : 20h – Device Code: E3h

■ ECOPACK

PACKAGES AVAILABLE

M29W040B

4 Mbit (512Kb x8, Uniform Block)

PLCC32 (K)

TSOP32 (NZ)

8 x 14mm

Figure 1. Logic Diagram

A0-A18

TSOP32 (N)

8 x 20mm

DQ0-DQ7

M29W040B

AI02953

1/20September 2005

M29W040B

Figure 2. PLCC Connections

A16

A7 A6 A5 A4 A3 A2 A1 A0

DQ0

A12

DQ1

A18

A15

M29W040B

DQ2

DQ3

DQ4

DQ5

A17

DQ6

A14 A13 A8 A9 A11 G A10 E DQ7

AI02951

Figure 3. TSOP Connections

A11 G

A8 A13 A14 A17

A18 A16 A15 A12

A4 A3

M29W040B

16 17

25 24

AI02952

A10 E DQ7 DQ6 DQ5 DQ4 DQ3 V

DQ2 DQ1 DQ0 A0 A1 A2

Table 1. Signal Names

A0-A18 Address Inputs DQ0-DQ7 Data Inputs/Outputs E G W V V

Chip Enable Output Enable Write Enable Supply Voltage Ground

SUMMARY DESCRIPTION

The M29W040B is a 4 Mbit ( 512Kb x 8) non-v olatile memory that c an be read, erased and r eprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. On power-up the memory default s to its Read mode where it can be read in the same way as a ROM or EPROM. The M29W040B is fully backward compatible with the M29W040.

The memory is divided into blocks that can be erased independently s o i t is po ss ible to preserve valid data while old data is erased. Each block can be protected independen tly to prevent accidental

Program or Erase com mands from modifying the memory. Program and Erase co mmands are written to the Command Int erface of th e memory . An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation ca n be detected and any error conditions ide nti fie d. T he co mma nd set required to control the memory is consistent with JEDEC standards.

Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic.

The memory is offered in TSOP32 (8 x 20mm), TSOP32 (8 x 14mm) and PLC C32 packag es and it is supplied with all the bits erased (set to ‘1’).

In order to meet environme ntal requirements, ST offers the M29W040B in ECOPACK

packages.

ECOPACK packages are Lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDE C Stand ard JESD 97. The m aximum ratings related to soldering conditions are also marked on the inner box label.

ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

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M29W040B

Table 2. Absolute Maximum Ratings

Symbol Parameter Value Unit

BIAS

STG

(2)

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may

cause permanent damage to the device. Thes e are str ess ratin gs only and oper at ion of the device at thes e or any ot her condi tio ns above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect dev ice reliability. Refer also to the S TMicroelectronics SURE Progr am and other relevant quality documents.

2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.

Ambient Operating Temperature (Temperature Range Option 1) 0 to 70 °C Ambient Operating Temperature (Temperature Range Option 6) –40 to 85 °C Temperature Under Bias –50 to 125 °C Storage Temperature –65 to 150 °C

Input or Output Voltage –0.6 to 4 V Supply Voltage –0.6 to 4 V

Identification Voltage –0.6 to 13.5 V

Table 3. Uniform Block Addresses, M29W040B

7 64 70000h-7FFFFh 6 64 60000h-6FFFFh 5 64 50000h-5FFFFh 4 64 40000h-4FFFFh 3 64 30000h-3FFFFh 2 64 20000h-2FFFFh 1 64 10000h-1FFFFh 0 64 00000h-0FFFFh

Size

(Kbytes)

Address Range

(1)

Chip Enable (E

). The Chip Enable, E, activates

the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, V

Output Enable (G

, all other pins are ignored.

). The Output Enable , G, con-

trols the Bus Read operation of the memory.

Write Enable (W

). The Write Enable, W, controls

the Bus Write operation of the memory’s Command Interface.

Supply Voltage. The VCC Supply Voltage

supplies the power for all operations (Read, Program, Erase etc.).

The Command Interface is disabled when the V

Supply Voltage is le ss than the Lockout Vo ltage, V

. This prevents Bus Write operations from ac-

SIGNAL DESCRIPTIONS

See Figure 1, Logic Diag ra m, an d T ab le 1 , Signal Names, for a brief overview of the signals connected to this device.

Address Inputs (A0-A18). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands

LKO

cidentally damaging the data during power-up, power-down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid.

A 0.1µF capacitor sh ould be connected between the V

Supply Voltage pin and the VSS Ground

pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, I

Ground. The VSS Ground is the reference for

CC3

all voltage measurements.

sent to the Command Interface of the internal state machine.

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M29W040B

BUS OPERATIONS

There are five standard bus operations that control the device. These are Bus Read, Bus Writ e, Output Disable, Standby and Automatic Standby. See Table 4, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip En able or Write Enable are ignored by the m emo ry and do not affect bus operations.

Bus Read. Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low s ig nal, V

, to Chip Enable

and Output Enable and keeping Write Enable High, V

. The Data Inputs/Outputs will ou tpu t the

value, see the Figure 8, Read Mode AC Waveforms, and Table 11, Read AC Characteristics, for details of when the output becomes valid.

Bus Write. Bus Write operations write to the Command Interface. A v alid Bus Write operati on begins by setting the desired address on the Address Inputs. The Ad dress Inputs are latched b y the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs ar e latched by the Com mand Interface on the rising ed ge of Chip Enab le or Write Enable, whichever occurs first. Output Enable must remain High, V

, during the whole Bus

Write operation . See Figures 9 and 10 Write AC Waveforms, and Tables 12 and 13, Write AC Characteristics, for details of the timing requirements.

Output Disable. The Data Inputs /Outputs are in the high impedance state when Output Enable is High, V

Standby. When Chip Enable is High, V

, the memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-impedance state. To reduce the Su pply Current to the Standby Supply Current, I be held within V

± 0.2V. For the Standby current

, Chip Enable should

CC2

level see Table 10, DC Characteristics. During program or eras e operations the memory

will continue to use the Program/Erase Supply Current, I

, for Program or Erase operations un-

CC3

til the operation completes. Automatic Standby. If CMOS levels (V

± 0.2V)

are used to drive the bus and the bus is inactive for 150ns or more the memory enters Automatic Standby where the interna l Supply Current is reduced to the Standby Supply Current, I

CC2

. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress.

Special Bus Operations

Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus operations are intended for us e by progr ammin g equip ment and are not usually used in applications. They require V

to be applied to some pins.

Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can b e read b y apply ing the sig nals listed in Table 4, Bus Operations.

Block Protection and Blocks Unprotection. Each block can be separately protected against accidental Program or Erase. Protected blocks can be unprotected to allow data to be changed. Block Protection and Blocks Unprotection operations must only be performed on programming equip ment. For further informa tion refer to Application Note AN1122, Applying Protectio n and Unpr otection to M29 Series Flash.

Table 4. Bus Operations

Operation E G W Address Inputs

Bus Read Bus Write Output Disable Standby Read Manufacturer

Code

Read Device Code

Note: X = VIL or VIH.

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XVIHV

X X X Hi-Z

Data

Inputs/Outputs

V V

Cell Address Data Output

Command Address Data Input

X Hi-Z

A0 = VIL, A1 = VIL, A9 = VID,

Others VIL or V A0 = VIL, A1 = VIL, A9 = VID,

Others VIL or V

20h

E3h

M29W040B

COMMAND INTERFACE

All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operation s will result in the memory return ing to Read mode. The long command sequences are imposed to maximize data security.

The commands are summarized in Table 5, Commands. Refer to Table 5 in conjunction with the text descriptions below.

Read/Reset Command. The Read/Reset command returns the memory to its Read mode where it behaves lik e a ROM or EPROM. I t also resets the errors in the Status Register. Either one or three Bus Write o perations can be us ed to issue the Read/Reset command.

If the Read/Reset command is issued during a Block Erase operation or following a Programming or Erase error then the memory will take upto 10

µs

to abort. During the abort period no valid data can be read from the memory. Issu ing a Read/Reset command during a Block Erase operation will leave invalid data in the memory.

Auto Select Command. The Auto Select command is used to read t he Manu facturer Code, the Device Code and the Block Protection Status. Three consecutive Bus Write operations are required to issue the Auto Sel ect command. Once the Auto Select comman d is issued the memory remains in Auto Sele ct mode until another command is issued.

From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = V may be set to either V

and A1 = VIL. The other address bits

or VIH. The Manufacturer

Code for STMicroelectronics is 20h. The Device Code can be read using a Bu s Read

operation with A0 = V address bits may be s et to either V

and A1 = VIL. The other

or VIH. The

Device Code for the M29W040B is E3h. The Block Protectio n Statu s of ea ch block c an be

read using a Bus Read ope ration with A0 = V A1 = V

, and A16, A17 and A18 specifying the ad-

dress of the block. The ot her add re ss bi ts may be set to either V

or VIH. If the address ed block is

protected then 01h is ou tput on the Data Inputs/ Outputs, otherwise 00h is output.

Program Command. The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller.

If the address falls in a protect ed block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given.

During the program operation th e memory will ig nore all commands. It is no t possib le to is sue any command to abort or pause the operation. Typical program times are given in Table 6. Bus Read operations during the p rogram operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details.

After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Statu s Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.

Note that the Program command cannot change a bit set at ‘0’ back t o ‘1’. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from ‘0’ to ‘1’.

Unlock Bypass Command. The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory. When the access time to the device is long (as with some EPROM programmers) considerable time saving can be made by using these commands. Three Bu s Write operations are r equired to issue the Unlock Bypass command.

Once the Unlock Bypass c ommand has been issued the memory will only accept the Unlock Bypass Program com mand and the Unlock B ypass Reset command. The memory can be read as if in Read mode.

Unlock Bypass Program Command. The Unlock Bypass Program command can be used to program one address in memory at a time. The command requires t wo Bus Write oper ations, the final write operati on lat ches the a ddress and d ata in the internal state machine and starts the Program/Erase Controller.

The Program operation us ing the Unlock Bypass

Program command behaves identically to the Program operation using the Program command. A protected block cannot be progra mme d; the op eration cannot be aborted and the Status Register is read. Errors must be reset using th e Read/Reset command, which leav es the device in Unlock Bypass Mode. See the Program command for details on the behavior.

Unlock Bypass Reset Command. The Unlock Bypass Reset comm and can b e used to return to Read/Reset mode from Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command.

5/20

M29W040B

Table 5. Commands

Bus Write Operations

Command

Read/Reset

Auto Select 3 555 AA 2AA 55 555 90 Program 4 555 AA 2AA 55 555 A0 PA PD Unlock Bypass 3 555 AA 2AA 55 555 20 Unlock Bypass

Program Unlock Bypass Reset 2 X 90 X 00 Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30 Erase Suspend 1 X B0 Erase Resume 1 X 30

Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal.

The Command Interface only uses address bits A0-A10 to verify the commands , t he upper address bits are Don’t Care.

Read/Reset. After a Read/Reset c ommand, read the memory as normal until anoth er command is issued. Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Statu s. Program, Unlock Bypass Pr o gr am, Chip Erase, Block Erase. After these commands read the Status Register until the Program/Erase

Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional Bus Write Operations until the Timeout Bit is set.

Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands. Unlock Bypass Reset. After the Unlock By pass Reset command read the memory as normal until another command is issued. Erase Suspend. After the Erase Suspend co mmand read non-erasing memory blocks as nor mal, issue Auto Select and P rogram commands

on non-erasing blocks as normal. Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/

Erase Controller completes and the memory returns to Read Mode.

1X F0 3555 AA2AA 55 X F0

2 X A0 PA PD

1st 2nd 3rd 4th 5th 6th

Length

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Chip Erase Command. The Chip Erase com-

mand can be used to erase the entire chip. Six Bus Write operations are required to issue the Chip Erase Command and start the Program/Erase Controller.

If any blocks are protected then these are ignored and all the other blocks are erased. If all of the blocks are protected the Chip Erase operation appears to start but will terminate within about 100µs, leaving the data unc hanged . No er ror con dition is given when protected blocks are ignored.

During the erase operation the memory will ignore all commands. It is not possible to issue any command to abort the operation. Typical chip erase

6/20

times are given in Table 6. All Bus Read operations during the Chip E rase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details.

After the Chip Erase o per at ion has c om ple ted the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Statu s Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode.

The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ‘1’. All previous data is lost.

+ 14 hidden pages

Numonyx M29W040B Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

Figure 1. Logic Diagram

Figure 2. PLCC Connections

Figure 3. TSOP Connections

Table 1. Signal Names

SUMMARY DESCRIPTION

Table 3. Uniform Block Addresses, M29W040B

SIGNAL DESCRIPTIONS

Address Inputs (A0-A18). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands

BUS OPERATIONS

Bus Read. Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low s ig nal, V

Output Disable. The Data Inputs /Outputs are in the high impedance state when Output Enable is High, V

Standby. When Chip Enable is High, V

til the operation completes. Automatic Standby. If CMOS levels (V

Special Bus Operations

Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can b e read b y apply ing the sig nals listed in Table 4, Bus Operations.

Table 4. Bus Operations

COMMAND INTERFACE

Read/Reset Command. The Read/Reset command returns the memory to its Read mode where it behaves lik e a ROM or EPROM. I t also resets the errors in the Status Register. Either one or three Bus Write o perations can be us ed to issue the Read/Reset command.

Program Command. The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller.

Unlock Bypass Program Command. The Unlock Bypass Program command can be used to program one address in memory at a time. The command requires t wo Bus Write oper ations, the final write operati on lat ches the a ddress and d ata in the internal state machine and starts the Program/Erase Controller.

Unlock Bypass Reset Command. The Unlock Bypass Reset comm and can b e used to return to Read/Reset mode from Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command.

Table 5. Commands

on non-erasing blocks as normal. Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/

Chip Erase Command. The Chip Erase com-

Numonyx M29W040B Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

Figure 1. Logic Diagram

Figure 2. PLCC Connections

Figure 3. TSOP Connections

Table 1. Signal Names

SUMMARY DESCRIPTION

Table 3. Uniform Block Addresses, M29W040B

SIGNAL DESCRIPTIONS

Address Inputs (A0-A18). The Address Inputs select the cells in the memory array to access dur­ing Bus Read operations. During Bus Write opera­tions they control the commands sent to the Command Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ7). The Data In­puts/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands

BUS OPERATIONS

Bus Read. Bus Read operations read from the memory cells, or specific registers in the Com­mand Interface. A valid Bus Read operation in­volves setting the desired address on the Address Inputs, applying a Low s ig nal, V

Output Disable. The Data Inputs /Outputs are in the high impedance state when Output Enable is High, V

Standby. When Chip Enable is High, V

til the operation completes. Automatic Standby. If CMOS levels (V

Special Bus Operations

Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can b e read b y apply ing the sig nals listed in Table 4, Bus Operations.

Table 4. Bus Operations

COMMAND INTERFACE

Read/Reset Command. The Read/Reset com­mand returns the memory to its Read mode where it behaves lik e a ROM or EPROM. I t also resets the errors in the Status Register. Either one or three Bus Write o perations can be us ed to issue the Read/Reset command.

Program Command. The Program command can be used to program a value to one address in the memory array at a time. The command re­quires four Bus Write operations, the final write op­eration latches the address and data in the internal state machine and starts the Program/Erase Con­troller.

Unlock Bypass Reset Command. The Unlock Bypass Reset comm and can b e used to return to Read/Reset mode from Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command.

Table 5. Commands

on non-erasing blocks as normal. Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/

Chip Erase Command. The Chip Erase com-

Address Inputs (A0-A18). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine.

Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands

Bus Read. Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low s ig nal, V

Read/Reset Command. The Read/Reset command returns the memory to its Read mode where it behaves lik e a ROM or EPROM. I t also resets the errors in the Status Register. Either one or three Bus Write o perations can be us ed to issue the Read/Reset command.

Program Command. The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller.