Numonyx M29DW323DT, M29DW323DB Technical data
32 Mbit (4Mb x8 or 2Mb x16, Dual Bank 8:24, Boot Block)
FEATURES SUMMARY
■ SUPPLY VOLTAGE
–V
–V
■ ACCESS TIME: 70ns
■ PROGRAMMING TIME
– 10µs per Byte/Word typical
– Double Word/ Quadruple Byte Program
■ MEMORY BLOCKS
– Dual Bank Memory Array: 8Mbit+24Mbit
– Parameter Blocks (Top or Bottom
■ DUAL OPERATIONS
– Read in one bank while Program or Erase
■ ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
■ UNLOCK BYPASS PROGRAM COMMAND
– Faster Production/Batch Programming
■ V
PP
WRITE PROTECT
■ TEMPORARY BLOCK UNPROTECTION
MODE
■ COMMON FLASH INTERFACE
– 64 bit Security Code
■ EXTENDED MEMORY BLOCK
– Extra block used as security block or to
■ LOW POWER CONSUMPTION
– Standby and Automatic Standby
■ 100,000 PROGRAM/ERASE CYCLES per
BLOCK
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Top Device Code M29DW323DT: 225Eh
– Bottom Device Code M29DW323DB:
2.7V to 3.6V for Program, Erase
CC =
and Read
=12V for Fast Program (optional)
PP
Location)
in other
Erase Suspend
/WP PIN for FAST PROGRAM and
store additional information
225Fh
M29DW323DT
M29DW323DB
3V Supply Flash Memory
Figure 1. Packages
TSOP48 (N)
12 x 20mm
FBGA
TFBGA48 (ZE)
6 x 8mm
1/51March 2008
M29DW323DT, M29DW323DB
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
TABLE OF CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. TFBGA48 Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Block Addresses (x8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Block Addresses (x16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Data Inputs/Outputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Data Input/Output or Address Input (DQ15A–1).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chip Enable (E
Output Enable (G
Write Enable (W
V
Write Protect (V
PP/
Reset/Block Temporary Unprotect (RP
Ready/Busy Output (RB
Byte/Word Organization Select (BYTE
V
Supply Voltage (2.7V to 3.6V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
CC
Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
V
SS
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PP/
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Block Protect and Chip Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3. Bus Operations, BYTE
Table 4. Bus Operations, BYTE
= VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
= VIH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Read/Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Auto Select Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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M29DW323DT, M29DW323DB
Read CFI Query Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Fast Program Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Quadruple Byte Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Double Word Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Unlock Bypass Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Unlock Bypass Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Unlock Bypass Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Chip Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Enter Extended Block Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Exit Extended Block Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Block Protect and Chip Unprotect Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5. Commands, 16-bit mode, BYTE
Table 6. Commands, 8-bit mode, BYTE
Table 7. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 19
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 7. Data Polling Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 8. Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
= VIH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
= VIL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 9. Dual Operations Allowed In the Other Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 10. Dual Operations Allowed In Same Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 11. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 12. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 9. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 10.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 13. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 14. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 11.Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 15. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Figure 12.Write AC Waveforms, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 16. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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M29DW323DT, M29DW323DB
Figure 13.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 17. Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 14.Toggle and Alternative Toggle Bits Mechanism, Chip Enable Controlled . . . . . . . . . . . . 29
Figure 15.Toggle and Alternative Toggle Bits Mechanism, Output Enable Controlled . . . . . . . . . . 29
Table 18. Toggle and Alternative Toggle Bits AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 16.Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 19. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 17.Accelerated Program Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 18.TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Bottom View Package Outline . . 31
Table 20. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Package Mechanical Data . . . . . 31
Figure 19.TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Bottom View Package Outline. . . . . . 32
Table 21. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Package Mechanical Data. . . . . . . . . 32
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 22. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
APPENDIX A.BLOCK ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 23. Top Boot Block Addresses, M29DW323DT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 24. Bottom Boot Block Addresses, M29DW323DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
APPENDIX B.COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 25. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Table 26. CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Table 27. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 28. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Table 29. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 30. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
APPENDIX C.EXTENDED MEMORY BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Factory Locked Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Customer Lockable Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 31. Extended Block Address and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
APPENDIX D.BLOCK PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 32. Programmer Technique Bus Operations, BYTE
= VIH or V
IL . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 20.Programmer Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 21.Programmer Equipment Chip Unprotect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 22.In-System Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 23.In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
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Table 33. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
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M29DW323DT, M29DW323DB
SUMMARY DESCRIPTION
The M29DW323D is a 32 Mbit (4Mb x8 or 2Mb
x16) non-volatile memory that can be read, erased
and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V)
supply. On power-up the memory defaults to its
Read mode.
The device features an asymmetrical block architecture. The M29DW323D has an array of 8 parameter and 63 main blocks and is divided into two
Banks, A and B, providing Dual Bank operations.
While programming or erasing in Bank A, read operations are possible in Bank B and vice versa.
Only one bank at a time is allowed to be in program or erase mode. The bank architecture is
summarized in Table 2. M29DW323DT locates the
Parameter Blocks at the top of the memory address space while the M29DW323DB locates the
Parameter Blocks starting from the bottom.
M29DW323D has an extra 32 KWord (x16 mode)
or 64 KByte (x8 mode) block, the Extended Block,
that can be accessed using a dedicated command. The Extended Block can be protected and
so is useful for storing security information. How-
Figure 2. Logic Diagram Table 1. Signal Names
VPP/WP
V
CC
A0-A20
RP
21
W
M29DW323DT
E
M29DW323DB
G
V
SS
15
DQ0-DQ14
DQ15A–1
BYTE
RB
AI05523
ever the protection is irreversible, once protected
the protection cannot be undone.
Each block can be erased independently so it is
possible to preserve valid data while old data is
erased. The blocks can be protected to prevent
accidental Program or Erase commands from
modifying the memory. Program and Erase commands are written to the Command Interface of
the memory. An on-chip Program/Erase Controller
simplifies the process of programming or erasing
the memory by taking care of all of the special operations that are required to update the memory
contents. The end of a program or erase operation
can be detected and any error conditions identified. The command set required to control the
memory is consistent with JEDEC standards.
Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory.
They allow simple connection to most microprocessors, often without additional logic.
The memory is offered in TSOP48 (12x20mm), and
TFBGA48 (6x8mm, 0.8mm pitch) packages. The
memory is supplied with all the bits erased (set to
’1’).
A0-A20 Address Inputs
DQ0-DQ7 Data Inputs/Outputs
DQ8-DQ14 Data Inputs/Outputs
DQ15A–1 Data Input/Output or Address Input
E
G
W
RP
RB
BYTE
V
CC
VPP/WP
V
SS
NC Not Connected Internally
Chip Enable
Output Enable
Write Enable
Reset/Block Temporary Unprotect
Ready/Busy Output
Byte/Word Organization Select
Supply Voltage
VPP/Write Protect
Ground
6/51
Figure 3. TSOP Connections
M29DW323DT, M29DW323DB
1
A15
48
A14
A13
A12
A11
A10 DQ14
A9
A8
A19
A20
W
RP
NC
M29DW323DT
M29DW323DB
12
13
37
36
VPP/WP
RB
A18
A17
A7
A6
A5
A4
A3
A2
A1
24 25
A16
BYTE
V
SS
DQ15A–1
DQ7
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
V
SS
E
A0
AI05524
7/51
M29DW323DT, M29DW323DB
Figure 4. TFBGA48 Connections (Top view through package)
RB
A
B
C
A3
A7
A17
A6
V
PP
A18
A4
A2
W
/
WP
RP
A10
NC
654321
A13
A9
A8
A12
A14
D
E
F
G
H
A1
A5 A20
DQ0
A0
E
G
V
SS
DQ8
DQ9
DQ1
DQ10
DQ11
DQ2
DQ3
A19
DQ5
DQ12
V
CC
DQ4
A11
DQ7
DQ14
DQ13
DQ6
A15
A16
BYTE
DQ15
A–1
V
SS
Table 2. Bank Architecture
Bank Bank Size
A 8 Mbit 8 8KByte/ 4 KWord 15 64KByte/ 32 KWord
B 24 Mbit - 48 64KByte/ 32 KWord
Parameter Blocks Main Blocks
No. of Blocks Block Size No. of Blocks Block Size
AI08084
8/51
Figure 5. Block Addresses (x8)
M29DW323DT, M29DW323DB
Top Boot Block (x8)
Address lines A20-A0, DQ15A-1
000000h
00FFFFh
Bank B
2F0000h
2FFFFFh
300000h
30FFFFh
3E0000h
Bank A
Note 1. Used as Extended Block Addresses in Extended Block mode.
Note: Also see APPENDIX A., Table 23. and Table 24. for a full listing of the Block Addresses.
3EFFFFh
3F0000h
3F1FFFh
3FE000h
3FFFFFh
64 KByte or
32 KWord
64 KByte or
32 KWord
64 KByte or
32 KWord
64 KByte or
32 KWord
8 KByte or
4 KWord
8 KByte or
4 KWord
Total of 48
Main Blocks
Total of 15
Main Blocks
Total of 8
Parameter
(1)
Blocks
Bank A
Bank B
Address lines A20-A0, DQ15A-1
000000h
001FFFh
00E000h
00FFFFh
010000h
01FFFFh
0F0000h
0FFFFFh
100000h
10FFFFh
3F0000h
3FFFFFh
Bottom Boot Block (x8)
8 KByte or
4 KWord
8 KByte or
4 KWord
64 KByte or
32 KWord
64 KByte or
32 KWord
64 KByte or
32 KWord
64 KByte or
32 KWord
Total of 8
Parameter
(1)
Blocks
Total of 15
Main Blocks
Total of 48
Main Blocks
AI05556
9/51
M29DW323DT, M29DW323DB
Figure 6. Block Addresses (x16)
Top Boot Block (x16)
Address lines A20-A0
000000h
007FFFh
Bank B
178000h
17FFFFh
180000h
187FFFh
1F0000h
Bank A
Note 1. Used as Extended Block Addresses in Extended Block mode.
Note: Also see APPENDIX A., Table 23. and Table 24. for a full listing of the Block Addresses.
1F7FFFh
1F8000h
1F8FFFh
1FF000h
1FFFFFh
64 KByte or
32 KWord
64 KByte or
32 KWord
64 KByte or
32 KWord
64 KByte or
32 KWord
8 KByte or
4 KWord
8 KByte or
4 KWord
Total of 48
Main Blocks
Total of 15
Main Blocks
Total of 8
Parameter
(1)
Blocks
Bank A
Bank B
000000h
000FFFh
007000h
007FFFh
008000h
00FFFFh
078000h
07FFFFh
080000h
087FFFh
1F8000h
1FFFFFh
Bottom Boot Block (x16)
Address lines A20-A0
8 KByte or
4 KWord
8 KByte or
4 KWord
64 KByte or
32 KWord
64 KByte or
32 KWord
64 KByte or
32 KWord
64 KByte or
32 KWord
Total of 8
Parameter
(1)
Blocks
Total of 15
Main Blocks
Total of 48
Main Blocks
AI05555
10/51
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram, and Table
1., Signal Names, for a brief overview of the sig-
nals connected to this device.
Address Inputs (A0-A20). The Address Inputs
select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the
Command Interface of the Program/Erase Controller.
Data Inputs/Outputs (DQ0-DQ7). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation. During Bus Write
operations they represent the commands sent to
the Command Interface of the Program/Erase
Controller.
Data Inputs/Outputs (DQ8-DQ14). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation when BYTE
. When BYTE is Low, VIL, these pins are not
V
IH
used and are high impedance. During Bus Write
operations the Command Register does not use
these bits. When reading the Status Register
these bits should be ignored.
Data Input/Output or Address Input (DQ15A–1).
When BYTE
is High, VIH, this pin behaves as a
Data Input/Output pin (as DQ8-DQ14). When
is Low, VIL, this pin behaves as an address
BYTE
pin; DQ15A–1 Low will select the LSB of the addressed Word, DQ15A–1 High will select the MSB.
Throughout the text consider references to the
Data Input/Output to include this pin when BYTE
High and references to the Address Inputs to include this pin when BYTE
is Low except when
stated explicitly otherwise.
Chip Enable (E
). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is
High, V
Output Enable (G
, all other pins are ignored.
IH
). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W
). The Write Enable, W, controls
the Bus Write operation of the memory’s Command Interface.
Write Protect (VPP/WP). The VPP/Write
V
PP/
pin provides two functions. The VPP func-
Protect
tion allows the memory to use an external high
voltage power supply to reduce the time required
for Program operations. This is achieved by bypassing the unlock cycles and/or using the Double Word or Quadruple Byte Program commands.
The Write Protect function provides a hardware
method of protecting the two outermost boot
blocks.
When V
protects the two outermost boot blocks; Program
/Write Protect is Low, VIL, the memory
PP
is High,
M29DW323DT, M29DW323DB
and Erase operations in these blocks are ignored
while V
at V
When V
reverts to the previous protection status of the two
outermost boot blocks. Program and Erase operations can now modify the data in these blocks unless the blocks are protected using Block
Protection.
When V
ory automatically enters the Unlock Bypass mode.
When V
mal operation resumes. During Unlock Bypass
Program operations the memory draws I
the pin to supply the programming circuits. See the
description of the Unlock Bypass command in the
Command Interface section. The transitions from
V
than t
Never raise V
mode except Read mode, otherwise the memory
may be left in an indeterminate state.
The V
or unconnected or the device may become unreliable. A 0.1µF capacitor should be connected between the V
Ground pin to decouple the current surges from
the power supply. The PCB track widths must be
sufficient to carry the currents required during
Unlock Bypass Program, I
is
Reset/Block Temporary Unprotect (RP
Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that have been
protected.
Note that if V
most boot blocks will remain protected even if RP
is at V
A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V
t
PLPX
goes High, V
Read and Bus Write operations after t
t
RHEL
Output section, Table 19. and Figure 16., Reset/
Block Temporary Unprotect AC Waveforms, for
more details.
Holding RP
protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from V
t
PHPHH
Ready/Busy Output (RB
is an open-drain output that can be used to identify
when the device is performing a Program or Erase
/Write Protect is Low, even when RP is
PP
.
ID
/Write Protect is High, VIH, the memory
PP
/Write Protect is raised to V
PP
/Write Protect returns to VIH or VIL nor-
PP
to VPP and from VPP to VIH must be slower
IH
, see Figure 17.
VHVPP
/Write Protect pin must not be left floating
PP
.
ID
/Write Protect to VPP from any
PP
/Write Protect pin and the V
PP
.
PP
/WP is at VIL, then the two outer-
PP
. After Reset/Block Temporary Unprotect
, the memory will be ready for Bus
IH
, whichever occurs last. See the Ready/Busy
at VID will temporarily unprotect the
to VID must be slower than
.
IH
). The Ready/Busy pin
the mem-
PP
from
PP
). The
, for at least
IL
PHEL
SS
or
11/51
M29DW323DT, M29DW323DB
operation. During Program or Erase operations
Ready/Busy is Low, V
pedance during Read mode, Auto Select mode
. Ready/Busy is high-im-
OL
and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write
operations cannot begin until Ready/Busy becomes high-impedance. See Table 19. and Figure
16., Reset/Block Temporary Unprotect AC Waveforms.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Byte/Word Organization Select (BYTE
). The
Byte/Word Organization Select pin is used to
switch between the x8 and x16 Bus modes of the
memory. When Byte/Word Organization Select is
Low, V
High, V
, the memory is in x8 mode, when it is
IL
, the memory is in x16 mode.
IH
V
Supply Voltage (2.7V to 3.6V). VCC pro-
CC
vides the power supply for all operations (Read,
Program and Erase).
The Command Interface is disabled when the V
Supply Voltage is less than the Lockout Voltage,
. This prevents Bus Write operations from ac-
V
LKO
cidentally damaging the data during power up,
CC
power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memory contents being altered will be invalid.
A 0.1µF capacitor should be connected between
Supply Voltage pin and the VSS Ground
the V
CC
pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during Program and
Erase operations, I
Ground. VSS is the reference for all voltage
V
SS
measurements. The device features two V
which must be both connected to the system
CC3
.
pins
SS
ground.
12/51
BUS OPERATIONS
There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby.
The Dual Bank architecture of the M29DW323 allows read/write operations in Bank A, while read
operations are being executed in Bank B or vice
versa. Write operations are only allowed in one
bank at a time.
See Tables 3 and 4, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory
and do not affect bus operations.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs, applying a Low signal, V
and Output Enable and keeping Write Enable
High, V
value, see Figure 11., Read Mode AC Waveforms,
. The Data Inputs/Outputs will output the
IH
and Table 15., Read AC Characteristics, for details of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Address Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output Enable must remain High, V
Write operation. See Figures 12 and 13, Write AC
Waveforms, and Tables 16 and 17, Write AC
Characteristics, for details of the timing requirements.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, V
.
IH
Standby. When Chip Enable is High, V
memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-imped-
, to Chip Enable
IL
, during the whole Bus
IH
IH
, the
M29DW323DT, M29DW323DB
ance state. To reduce the Supply Current to the
Standby Supply Current, I
be held within V
level see Table 14., DC Characteristics.
± 0.2V. For the Standby current
CC
During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, I
til the operation completes.
, for Program or Erase operations un-
CC3
Automatic Standby. If CMOS levels (V
are used to drive the bus and the bus is inactive for
300ns or more the memory enters Automatic
Standby where the internal Supply Current is reduced to the Standby Supply Current, I
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications.
They require V
to be applied to some pins.
ID
Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 3 and 4, Bus Operations.
Block Protect and Chip Unprotect.
blocks can be protected against accidental Program or Erase. The Protection Groups are shown
in APPENDIX A., Tables 23 and 24, Block Ad-
dresses. The whole chip can be unprotected to allow the data inside the blocks to be changed.
The V
the two outermost boot blocks. When V
Protect
protected and remain protected regardless of the
/Write Protect pin can be used to protect
PP
is at V
the two outermost boot blocks are
IL
Block Protection Status or the Reset/Block Temporary Unprotect pin status.
Block Protect and Chip Unprotect operations are
described in APPENDIX D.
, Chip Enable should
CC2
CC
Groups of
± 0.2V)
. The
CC2
/Write
PP
13/51
M29DW323DT, M29DW323DB
Table 3. Bus Operations, BYTE = V
Operation E G W
Bus Read
Bus Write
Output Disable X
Standby
Read Manufacturer
Code
Read Device Code
Extended Memory
Block Verify Code
Note: X = VIL or VIH.
V
ILVIL
V
ILVIH
V
IH
V
X X X Hi-Z Hi-Z
IH
V
VILV
IL
V
VILV
IL
VILV
V
IL
Table 4. Bus Operations, BYTE = V
Operation E
Bus Read
Bus Write
Output Disable X
Standby
Read Manufacturer
Code
Read Device Code
Extended Memory
Block Verify Code
Note: X = VIL or VIH.
G W
V
V
IL
IL
V
V
IL
IH
V
IHVIH
V
X X X Hi-Z
IH
V
V
IL
IL
V
V
IL
IL
V
V
IL
IL
IL
Address Inputs
DQ15A–1, A0-A20
V
Cell Address Hi-Z Data Output
IH
V
Command Address Hi-Z Data Input
IL
V
X Hi-Z Hi-Z
IH
A0 = VIL, A1 = VIL, A9 = VID,
IH
Others V
A0 = VIH, A1 = VIL,
IH
A9 = V
A0 = VIH, A1 = VIH, A6 = VIL,
IH
A9 = V
IH
or V
IL
IH
, Others VIL or V
ID
, Others VIL or V
ID
IH
IH
Address Inputs
A0-A20
V
Cell Address Data Output
IH
V
Command Address Data Input
IL
Data Inputs/Outputs
DQ14-DQ8 DQ7-DQ0
Hi-Z 20h
Hi-Z
Hi-Z
5Eh (M29DW323DT)
5Fh (M29DW323DB)
01h (not factory locked)
Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
X Hi-Z
A0 = VIL, A1 = VIL, A9 = VID,
V
IH
Others V
A0 = VIH, A1 = VIL, A9 = VID,
V
IH
Others V
A0 = VIH, A1 = VIH, A6 = VIL,
V
IH
A9 = V
or V
IL
IH
or V
IL
IH
, Others VIL or V
ID
225Eh (M29DW323DT)
225Fh (M29DW323DB)
81h (factory locked)
IH
01h (not factory locked)
81h (factory locked)
0020h
14/51
COMMAND INTERFACE
All Bus Write operations to the memory are interpreted by the Command Interface. Commands
consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus
Write operations will result in the memory returning to Read mode. The long command sequences
are imposed to maximize data security.
The address used for the commands changes depending on whether the memory is in 16-bit or 8bit mode. See either Table 5, or 6, depending on
the configuration that is being used, for a summary
of the commands.
Read/Reset Command
The Read/Reset command returns the memory to
its Read mode. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset
command.
The Read/Reset command can be issued, between Bus Write cycles before the start of a program or erase operation, to return the device to
read mode. If the Read/Reset command is issued
during the time-out of a Block erase operation then
the memory will take up to 10µs to abort. During
the abort period no valid data can be read from the
memory. The Read/Reset command will not abort
an Erase operation when issued while in Erase
Suspend.
Auto Select Command
The Auto Select command is used to read the
Manufacturer Code, the Device Code, the Block
Protection Status and the Extended Memory Block
Verify Code. It can be addressed to either Bank.
Three consecutive Bus Write operations are required to issue the Auto Select command. The final Write cycle must be addressed to one of the
Banks. Once the Auto Select command is issued
Bus Read operations to the Bank where the command was issued output the Auto Select data. Bus
Read operations to the other Bank will output the
contents of the memory array. The memory remains in Auto Select mode until a Read/Reset or
CFI Query command is issued.
In Auto Select mode the Manufacturer Code can
be read using a Bus Read operation with A0 = V
and A1 = VIL and A19-A20 = Bank Address. The
other address bits may be set to either V
The Device Code can be read using a Bus Read
operation with A0 = V
= Bank Address. The other address bits may be
set to either V
IL
and A1 = VIL and A19-A20
IH
or VIH.
The Block Protection Status of each block can be
read using a Bus Read operation with A0 = V
A1 = V
specifying the address of the block inside the
, A19-A20 = Bank Address and A12-A18
IH
or VIH.
IL
M29DW323DT, M29DW323DB
Bank. The other address bits may be set to either
or VIH. If the addressed block is protected then
V
IL
01h is output on Data Inputs/Outputs DQ0-DQ7,
otherwise 00h is output.
Read CFI Query Command
The Read CFI Query Command is used to read
data from the Common Flash Interface (CFI)
Memory Area. This command is valid when the device is in the Read Array mode, or when the device
is in Auto Select mode.
One Bus Write cycle is required to issue the Read
CFI Query Command. Once the command is issued subsequent Bus Read operations read from
the Common Flash Interface Memory Area.
The Read/Reset command must be issued to return the device to the previous mode (the Read Array mode or Auto Select mode). A second Read/
Reset command would be needed if the device is
to be put in the Read Array mode from Auto Select
mode.
See APPENDIX B., Tables 25, 26, 27, 28, 29 and
30 for details on the information contained in the
Common Flash Interface (CFI) memory area.
Program Command
The Program command can be used to program a
value to one address in the memory array at a
time. The command requires four Bus Write operations, the final write operation latches the address and data, and starts the Program/Erase
Controller.
If the address falls in a protected block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.
During the program operation the memory will ignore all commands. It is not possible to issue any
command to abort or pause the operation. After
programming has started, Bus Read operations in
the Bank being programmed output the Status
Register content, while Bus Read operations to
the other Bank output the contents of the memory
array. See the section on the Status Register for
more details. Typical program times are given in
Table 7.
IL
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs Bus
Read operations to the Bank where the command
was issued will continue to output the Status Register. A Read/Reset command must be issued to
reset the error condition and return to Read mode.
Note that the Program command cannot change a
,
IL
bit set at ’0’ back to ’1’. One of the Erase Commands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.
15/51
M29DW323DT, M29DW323DB
Fast Program Commands
There are two Fast Program commands available
to improve the programming throughput, by writing
several adjacent words or bytes in parallel. The
Quadruple Byte Program command is available for
x8 operations, while the Double Word Program
command is available for x16 operations.
Only one bank can be programmed at any one
time. The other bank must be in Read mode or
Erase Suspend.
Fast Program commands should not be attempted
when V
because applying a 12V V
WP
WP is not at VPP. Care must be taken
PP/
pin will temporarily unprotect any protected
voltage to the VPP/
PP
block.
After programming has started, Bus Read opera-
tions in the Bank being programmed output the
Status Register content, while Bus Read operations to the other Bank output the contents of the
memory array.
After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs Bus
Read operations to the Bank where the command
was issued will continue to output the Status Register. A Read/Reset command must be issued to
reset the error condition and return to Read mode.
Note that the Fast Program commands cannot
change a bit set at ’0’ back to ’1’. One of the Erase
Commands must be used to set all the bits in a
block or in the whole memory from ’0’ to ’1’.
Typical Program times are given in Table
7., Program, Erase Times and Program, Erase
Endurance Cycles.
Quadruple Byte Program Command. The Quadruple Byte Program command is used to write a
page of four adjacent Bytes in parallel. The four
bytes must differ only for addresses A0, DQ15A-1.
Five bus write cycles are necessary to issue the
Quadruple Byte Program command.
■ The first bus cycle sets up the Quadruple Byte
Program Command.
■ The second bus cycle latches the Address and
the Data of the first byte to be written.
■ The third bus cycle latches the Address and
the Data of the second byte to be written.
■ The fourth bus cycle latches the Address and
the Data of the third byte to be written.
■ The fifth bus cycle latches the Address and the
Data of the fourth byte to be written and starts
the Program/Erase Controller.
Double Word Program Command. The Double
Word Program command is used to write a page
of two adjacent words in parallel. The two words
must differ only for the address A0.
Three bus write cycles are necessary to issue the
Double Word Program command.
■ The first bus cycle sets up the Double Word
Program Command.
■ The second bus cycle latches the Address and
the Data of the first word to be written.
■ The third bus cycle latches the Address and
the Data of the second word to be written and
starts the Program/Erase Controller.
Unlock Bypass Command
The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to
program the memory faster than with the standard
program commands. When the cycle time to the
device is long, considerable time saving can be
made by using these commands. Three Bus Write
operations are required to issue the Unlock Bypass command.
Once the Unlock Bypass command has been issued the bank enters Unlock Bypass mode. When
in Unlock Bypass mode, only the Unlock Bypass
Program and Unlock Bypass Reset commands
are valid. The Unlock Bypass Program command
can be issued to program addresses within the
bank, and the Unlock Bypass Reset command to
return the bank to Read mode. In Unlock Bypass
mode the memory can be read as if in Read mode.
When V
the memory automatically enters the Unlock By-
is applied to the VPP/Write Protect pin
PP
pass mode and the Unlock Bypass Program command can be issued immediately. Care must be
taken because applying a 12V V
VPP/WP
pin will temporarily unprotect any protect-
voltage to the
PP
ed block.
Unlock Bypass Program Command
The Unlock Bypass Program command can be
used to program one address in the memory array
at a time. The command requires two Bus Write
operations, the final write operation latches the address and data, and starts the Program/Erase
Controller.
The Program operation using the Unlock Bypass
Program command behaves identically to the Program operation using the Program command. The
operation cannot be aborted, a Bus Read operation to the Bank where the command was issued
outputs the Status Register. See the Program
command for details on the behavior.
Unlock Bypass Reset Command
The Unlock Bypass Reset command can be used
to return to Read/Reset mode from Unlock Bypass
Mode. Two Bus Write operations are required to
issue the Unlock Bypass Reset command. Read/
Reset command does not exit from Unlock Bypass
Mode.
16/51
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