Numonyx M29DW323DT, M29DW323DB Technical data

32 Mbit (4Mb x8 or 2Mb x16, Dual Bank 8:24, Boot Block)

FEATURES SUMMARY

■ SUPPLY VOLTAGE

–V

–V

■ ACCESS TIME: 70ns

■ PROGRAMMING TIME

– 10µs per Byte/Word typical
– Double Word/ Quadruple Byte Program

■ MEMORY BLOCKS

– Dual Bank Memory Array: 8Mbit+24Mbit
– Parameter Blocks (Top or Bottom

■ DUAL OPERATIONS

– Read in one bank while Program or Erase

■ ERASE SUSPEND and RESUME MODES

– Read and Program another Block during

■ UNLOCK BYPASS PROGRAM COMMAND

– Faster Production/Batch Programming

■ V

PP

WRITE PROTECT

■ TEMPORARY BLOCK UNPROTECTION

MODE

■ COMMON FLASH INTERFACE

– 64 bit Security Code

■ EXTENDED MEMORY BLOCK

– Extra block used as security block or to

■ LOW POWER CONSUMPTION

– Standby and Automatic Standby

■ 100,000 PROGRAM/ERASE CYCLES per

BLOCK

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 0020h
– Top Device Code M29DW323DT: 225Eh
– Bottom Device Code M29DW323DB:

2.7V to 3.6V for Program, Erase

CC =

and Read

=12V for Fast Program (optional)

PP

Location)

in other

Erase Suspend

/WP PIN for FAST PROGRAM and

store additional information

225Fh

M29DW323DT

M29DW323DB

3V Supply Flash Memory

Figure 1. Packages

TSOP48 (N)

12 x 20mm

FBGA

TFBGA48 (ZE)

6 x 8mm

1/51March 2008

M29DW323DT, M29DW323DB

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

TABLE OF CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4. TFBGA48 Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 2. Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 5. Block Addresses (x8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 6. Block Addresses (x16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Data Inputs/Outputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Data Input/Output or Address Input (DQ15A–1).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Chip Enable (E
Output Enable (G
Write Enable (W
V

Write Protect (V

PP/

Reset/Block Temporary Unprotect (RP
Ready/Busy Output (RB
Byte/Word Organization Select (BYTE
V

Supply Voltage (2.7V to 3.6V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

CC

Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

V

SS

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

PP/

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Block Protect and Chip Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 3. Bus Operations, BYTE
Table 4. Bus Operations, BYTE

= VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

= VIH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Read/Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Auto Select Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2/51

M29DW323DT, M29DW323DB

Read CFI Query Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Fast Program Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Quadruple Byte Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Double Word Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Unlock Bypass Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Unlock Bypass Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Unlock Bypass Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Chip Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Enter Extended Block Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Exit Extended Block Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Block Protect and Chip Unprotect Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 5. Commands, 16-bit mode, BYTE
Table 6. Commands, 8-bit mode, BYTE

Table 7. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 19

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 8. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 7. Data Polling Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 8. Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

= VIH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

= VIL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 9. Dual Operations Allowed In the Other Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 10. Dual Operations Allowed In Same Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 11. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 12. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 9. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 10.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 13. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 14. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 11.Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 15. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 12.Write AC Waveforms, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 16. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

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M29DW323DT, M29DW323DB

Figure 13.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 17. Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 14.Toggle and Alternative Toggle Bits Mechanism, Chip Enable Controlled . . . . . . . . . . . . 29

Figure 15.Toggle and Alternative Toggle Bits Mechanism, Output Enable Controlled . . . . . . . . . . 29

Table 18. Toggle and Alternative Toggle Bits AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 16.Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 19. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 17.Accelerated Program Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 18.TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Bottom View Package Outline . . 31

Table 20. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Package Mechanical Data . . . . . 31

Figure 19.TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Bottom View Package Outline. . . . . . 32

Table 21. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Package Mechanical Data. . . . . . . . . 32

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 22. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

APPENDIX A.BLOCK ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 23. Top Boot Block Addresses, M29DW323DT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 24. Bottom Boot Block Addresses, M29DW323DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

APPENDIX B.COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 25. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 26. CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 27. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 28. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Table 29. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 30. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

APPENDIX C.EXTENDED MEMORY BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Factory Locked Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Customer Lockable Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 31. Extended Block Address and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

APPENDIX D.BLOCK PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 32. Programmer Technique Bus Operations, BYTE

= VIH or V

IL . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 20.Programmer Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 21.Programmer Equipment Chip Unprotect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 22.In-System Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 23.In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

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M29DW323DT, M29DW323DB

Table 33. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

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M29DW323DT, M29DW323DB

SUMMARY DESCRIPTION

The M29DW323D is a 32 Mbit (4Mb x8 or 2Mb
x16) non-volatile memory that can be read, erased
and reprogrammed. These operations can be per­formed using a single low voltage (2.7 to 3.6V)
supply. On power-up the memory defaults to its
Read mode.

The device features an asymmetrical block archi­tecture. The M29DW323D has an array of 8 pa­rameter and 63 main blocks and is divided into two
Banks, A and B, providing Dual Bank operations.
While programming or erasing in Bank A, read op­erations are possible in Bank B and vice versa.
Only one bank at a time is allowed to be in pro­gram or erase mode. The bank architecture is
summarized in Table 2. M29DW323DT locates the
Parameter Blocks at the top of the memory ad­dress space while the M29DW323DB locates the
Parameter Blocks starting from the bottom.

M29DW323D has an extra 32 KWord (x16 mode)
or 64 KByte (x8 mode) block, the Extended Block,
that can be accessed using a dedicated com­mand. The Extended Block can be protected and
so is useful for storing security information. How-

Figure 2. Logic Diagram Table 1. Signal Names

VPP/WP

V

CC

A0-A20

RP

21

W

M29DW323DT

E

M29DW323DB

G

V

SS

15

DQ0-DQ14

DQ15A–1

BYTE

RB

AI05523

ever the protection is irreversible, once protected
the protection cannot be undone.

Each block can be erased independently so it is
possible to preserve valid data while old data is
erased. The blocks can be protected to prevent
accidental Program or Erase commands from
modifying the memory. Program and Erase com­mands are written to the Command Interface of
the memory. An on-chip Program/Erase Controller
simplifies the process of programming or erasing
the memory by taking care of all of the special op­erations that are required to update the memory
contents. The end of a program or erase operation
can be detected and any error conditions identi­fied. The command set required to control the
memory is consistent with JEDEC standards.

Chip Enable, Output Enable and Write Enable sig­nals control the bus operation of the memory.
They allow simple connection to most micropro­cessors, often without additional logic.

The memory is offered in TSOP48 (12x20mm), and
TFBGA48 (6x8mm, 0.8mm pitch) packages. The
memory is supplied with all the bits erased (set to
’1’).

A0-A20 Address Inputs

DQ0-DQ7 Data Inputs/Outputs

DQ8-DQ14 Data Inputs/Outputs

DQ15A–1 Data Input/Output or Address Input

E

G

W

RP

RB

BYTE

V

CC

VPP/WP

V

SS

NC Not Connected Internally

Chip Enable

Output Enable

Write Enable

Reset/Block Temporary Unprotect

Ready/Busy Output

Byte/Word Organization Select

Supply Voltage

VPP/Write Protect

Ground

6/51

Figure 3. TSOP Connections

M29DW323DT, M29DW323DB

1

A15

48
A14
A13
A12
A11
A10 DQ14

A9

A8
A19
A20

W
RP
NC

M29DW323DT

M29DW323DB

12
13

37
36

VPP/WP

RB

A18
A17

A7
A6
A5
A4
A3
A2
A1

24 25

A16
BYTE
V

SS

DQ15A–1
DQ7

DQ6
DQ13
DQ5
DQ12
DQ4
V

CC

DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
V

SS

E
A0

AI05524

7/51

M29DW323DT, M29DW323DB

Figure 4. TFBGA48 Connections (Top view through package)

RB

A

B

C

A3

A7

A17

A6

V

PP

A18

A4

A2

W

/

WP

RP

A10

NC

654321

A13

A9

A8

A12

A14

D

E

F

G

H

A1

A5 A20

DQ0

A0

E

G

V

SS

DQ8

DQ9

DQ1

DQ10

DQ11

DQ2

DQ3

A19

DQ5

DQ12

V

CC

DQ4

A11

DQ7

DQ14

DQ13

DQ6

A15

A16

BYTE

DQ15

A–1

V

SS

Table 2. Bank Architecture

Bank Bank Size

A 8 Mbit 8 8KByte/ 4 KWord 15 64KByte/ 32 KWord

B 24 Mbit - 48 64KByte/ 32 KWord

Parameter Blocks Main Blocks

No. of Blocks Block Size No. of Blocks Block Size

AI08084

8/51

Figure 5. Block Addresses (x8)

M29DW323DT, M29DW323DB

Top Boot Block (x8)

Address lines A20-A0, DQ15A-1

000000h

00FFFFh

Bank B

2F0000h

2FFFFFh

300000h

30FFFFh

3E0000h

Bank A

Note 1. Used as Extended Block Addresses in Extended Block mode.

Note: Also see APPENDIX A., Table 23. and Table 24. for a full listing of the Block Addresses.

3EFFFFh

3F0000h

3F1FFFh

3FE000h

3FFFFFh

64 KByte or

32 KWord

64 KByte or

32 KWord

64 KByte or

32 KWord

64 KByte or

32 KWord

8 KByte or

4 KWord

8 KByte or

4 KWord

Total of 48
Main Blocks

Total of 15
Main Blocks

Total of 8
Parameter

(1)

Blocks

Bank A

Bank B

Address lines A20-A0, DQ15A-1

000000h

001FFFh

00E000h

00FFFFh

010000h

01FFFFh

0F0000h

0FFFFFh

100000h

10FFFFh

3F0000h

3FFFFFh

Bottom Boot Block (x8)

8 KByte or

4 KWord

8 KByte or

4 KWord

64 KByte or

32 KWord

64 KByte or

32 KWord

64 KByte or

32 KWord

64 KByte or

32 KWord

Total of 8
Parameter

(1)

Blocks

Total of 15
Main Blocks

Total of 48
Main Blocks

AI05556

9/51

M29DW323DT, M29DW323DB

Figure 6. Block Addresses (x16)

Top Boot Block (x16)

Address lines A20-A0

000000h

007FFFh

Bank B

178000h

17FFFFh

180000h

187FFFh

1F0000h

Bank A

Note 1. Used as Extended Block Addresses in Extended Block mode.

Note: Also see APPENDIX A., Table 23. and Table 24. for a full listing of the Block Addresses.

1F7FFFh

1F8000h

1F8FFFh

1FF000h

1FFFFFh

64 KByte or

32 KWord

64 KByte or

32 KWord

64 KByte or

32 KWord

64 KByte or

32 KWord

8 KByte or

4 KWord

8 KByte or

4 KWord

Total of 48
Main Blocks

Total of 15
Main Blocks

Total of 8
Parameter

(1)

Blocks

Bank A

Bank B

000000h

000FFFh

007000h

007FFFh

008000h

00FFFFh

078000h

07FFFFh

080000h

087FFFh

1F8000h

1FFFFFh

Bottom Boot Block (x16)

Address lines A20-A0

8 KByte or

4 KWord

8 KByte or

4 KWord

64 KByte or

32 KWord

64 KByte or

32 KWord

64 KByte or

32 KWord

64 KByte or

32 KWord

Total of 8
Parameter

(1)

Blocks

Total of 15
Main Blocks

Total of 48
Main Blocks

AI05555

10/51

SIGNAL DESCRIPTIONS

See Figure 2., Logic Diagram, and Table

1., Signal Names, for a brief overview of the sig-

nals connected to this device.
Address Inputs (A0-A20). The Address Inputs

select the cells in the memory array to access dur­ing Bus Read operations. During Bus Write opera­tions they control the commands sent to the
Command Interface of the Program/Erase Con­troller.

Data Inputs/Outputs (DQ0-DQ7). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation. During Bus Write
operations they represent the commands sent to
the Command Interface of the Program/Erase
Controller.

Data Inputs/Outputs (DQ8-DQ14). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation when BYTE

. When BYTE is Low, VIL, these pins are not

V

IH

used and are high impedance. During Bus Write
operations the Command Register does not use
these bits. When reading the Status Register
these bits should be ignored.

Data Input/Output or Address Input (DQ15A–1).

When BYTE

is High, VIH, this pin behaves as a

Data Input/Output pin (as DQ8-DQ14). When

is Low, VIL, this pin behaves as an address

BYTE
pin; DQ15A–1 Low will select the LSB of the ad­dressed Word, DQ15A–1 High will select the MSB.
Throughout the text consider references to the
Data Input/Output to include this pin when BYTE
High and references to the Address Inputs to in­clude this pin when BYTE

is Low except when

stated explicitly otherwise.

Chip Enable (E

). The Chip Enable, E, activates

the memory, allowing Bus Read and Bus Write op­erations to be performed. When Chip Enable is
High, V

Output Enable (G

, all other pins are ignored.

IH

). The Output Enable, G, con-

trols the Bus Read operation of the memory.

Write Enable (W

). The Write Enable, W, controls

the Bus Write operation of the memory’s Com­mand Interface.

Write Protect (VPP/WP). The VPP/Write

V

PP/

pin provides two functions. The VPP func-

Protect
tion allows the memory to use an external high
voltage power supply to reduce the time required
for Program operations. This is achieved by by­passing the unlock cycles and/or using the Dou­ble Word or Quadruple Byte Program commands.
The Write Protect function provides a hardware
method of protecting the two outermost boot
blocks.

When V
protects the two outermost boot blocks; Program

/Write Protect is Low, VIL, the memory

PP

is High,

M29DW323DT, M29DW323DB

and Erase operations in these blocks are ignored
while V
at V

When V
reverts to the previous protection status of the two
outermost boot blocks. Program and Erase oper­ations can now modify the data in these blocks un­less the blocks are protected using Block
Protection.

When V
ory automatically enters the Unlock Bypass mode.
When V
mal operation resumes. During Unlock Bypass
Program operations the memory draws I
the pin to supply the programming circuits. See the
description of the Unlock Bypass command in the
Command Interface section. The transitions from
V
than t

Never raise V
mode except Read mode, otherwise the memory
may be left in an indeterminate state.

The V
or unconnected or the device may become unreli­able. A 0.1µF capacitor should be connected be­tween the V
Ground pin to decouple the current surges from
the power supply. The PCB track widths must be
sufficient to carry the currents required during
Unlock Bypass Program, I

is

Reset/Block Temporary Unprotect (RP

Reset/Block Temporary Unprotect pin can be
used to apply a Hardware Reset to the memory or
to temporarily unprotect all Blocks that have been
protected.

Note that if V
most boot blocks will remain protected even if RP
is at V

A Hardware Reset is achieved by holding Reset/
Block Temporary Unprotect Low, V
t

PLPX

goes High, V
Read and Bus Write operations after t
t

RHEL

Output section, Table 19. and Figure 16., Reset/

Block Temporary Unprotect AC Waveforms, for

more details.
Holding RP

protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from V
t

PHPHH

Ready/Busy Output (RB

is an open-drain output that can be used to identify
when the device is performing a Program or Erase

/Write Protect is Low, even when RP is

PP

.

ID

/Write Protect is High, VIH, the memory

PP

/Write Protect is raised to V

PP

/Write Protect returns to VIH or VIL nor-

PP

to VPP and from VPP to VIH must be slower

IH

, see Figure 17.

VHVPP

/Write Protect pin must not be left floating

PP

.

ID

/Write Protect to VPP from any

PP

/Write Protect pin and the V

PP

.

PP

/WP is at VIL, then the two outer-

PP

. After Reset/Block Temporary Unprotect

, the memory will be ready for Bus

IH

, whichever occurs last. See the Ready/Busy

at VID will temporarily unprotect the

to VID must be slower than

.

IH

). The Ready/Busy pin

the mem-

PP

from

PP

). The

, for at least

IL

PHEL

SS

or

11/51

M29DW323DT, M29DW323DB

operation. During Program or Erase operations
Ready/Busy is Low, V
pedance during Read mode, Auto Select mode

. Ready/Busy is high-im-

OL

and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write

operations cannot begin until Ready/Busy be­comes high-impedance. See Table 19. and Figure

16., Reset/Block Temporary Unprotect AC Wave­forms.

The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.

Byte/Word Organization Select (BYTE

). The

Byte/Word Organization Select pin is used to
switch between the x8 and x16 Bus modes of the
memory. When Byte/Word Organization Select is
Low, V
High, V

, the memory is in x8 mode, when it is

IL

, the memory is in x16 mode.

IH

V

Supply Voltage (2.7V to 3.6V). VCC pro-

CC

vides the power supply for all operations (Read,
Program and Erase).

The Command Interface is disabled when the V
Supply Voltage is less than the Lockout Voltage,

. This prevents Bus Write operations from ac-

V

LKO

cidentally damaging the data during power up,

CC

power down and power surges. If the Program/
Erase Controller is programming or erasing during
this time then the operation aborts and the memo­ry contents being altered will be invalid.

A 0.1µF capacitor should be connected between

Supply Voltage pin and the VSS Ground

the V

CC

pin to decouple the current surges from the power
supply. The PCB track widths must be sufficient to
carry the currents required during Program and
Erase operations, I

Ground. VSS is the reference for all voltage

V

SS

measurements. The device features two V
which must be both connected to the system

CC3

.

pins

SS

ground.

12/51

BUS OPERATIONS

There are five standard bus operations that control
the device. These are Bus Read, Bus Write, Out­put Disable, Standby and Automatic Standby.

The Dual Bank architecture of the M29DW323 al­lows read/write operations in Bank A, while read
operations are being executed in Bank B or vice
versa. Write operations are only allowed in one
bank at a time.

See Tables 3 and 4, Bus Operations, for a summa­ry. Typically glitches of less than 5ns on Chip En­able or Write Enable are ignored by the memory
and do not affect bus operations.

Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com­mand Interface. A valid Bus Read operation in­volves setting the desired address on the Address
Inputs, applying a Low signal, V
and Output Enable and keeping Write Enable
High, V
value, see Figure 11., Read Mode AC Waveforms,

. The Data Inputs/Outputs will output the

IH

and Table 15., Read AC Characteristics, for de­tails of when the output becomes valid.

Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by setting the desired address on the Ad­dress Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Com­mand Interface on the rising edge of Chip Enable
or Write Enable, whichever occurs first. Output En­able must remain High, V
Write operation. See Figures 12 and 13, Write AC
Waveforms, and Tables 16 and 17, Write AC
Characteristics, for details of the timing require­ments.

Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, V

.

IH

Standby. When Chip Enable is High, V
memory enters Standby mode and the Data In­puts/Outputs pins are placed in the high-imped-

, to Chip Enable

IL

, during the whole Bus

IH

IH

, the

M29DW323DT, M29DW323DB

ance state. To reduce the Supply Current to the
Standby Supply Current, I
be held within V
level see Table 14., DC Characteristics.

± 0.2V. For the Standby current

CC

During program or erase operations the memory
will continue to use the Program/Erase Supply
Current, I
til the operation completes.

, for Program or Erase operations un-

CC3

Automatic Standby. If CMOS levels (V
are used to drive the bus and the bus is inactive for
300ns or more the memory enters Automatic
Standby where the internal Supply Current is re­duced to the Standby Supply Current, I
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.

Special Bus Operations

Additional bus operations can be performed to
read the Electronic Signature and also to apply
and remove Block Protection. These bus opera­tions are intended for use by programming equip­ment and are not usually used in applications.
They require V

to be applied to some pins.

ID

Electronic Signature. The memory has two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 3 and 4, Bus Operations.

Block Protect and Chip Unprotect.

blocks can be protected against accidental Pro­gram or Erase. The Protection Groups are shown
in APPENDIX A., Tables 23 and 24, Block Ad-
dresses. The whole chip can be unprotected to al­low the data inside the blocks to be changed.

The V
the two outermost boot blocks. When V
Protect
protected and remain protected regardless of the

/Write Protect pin can be used to protect

PP

is at V

the two outermost boot blocks are

IL

Block Protection Status or the Reset/Block Tem­porary Unprotect pin status.

Block Protect and Chip Unprotect operations are
described in APPENDIX D.

, Chip Enable should

CC2

CC

Groups of

± 0.2V)

. The

CC2

/Write

PP

13/51

M29DW323DT, M29DW323DB

Table 3. Bus Operations, BYTE = V

Operation E G W

Bus Read

Bus Write

Output Disable X

Standby

Read Manufacturer
Code

Read Device Code

Extended Memory
Block Verify Code

Note: X = VIL or VIH.

V

ILVIL

V

ILVIH

V

IH

V

X X X Hi-Z Hi-Z

IH

V

VILV

IL

V

VILV

IL

VILV

V

IL

Table 4. Bus Operations, BYTE = V

Operation E

Bus Read

Bus Write

Output Disable X

Standby

Read Manufacturer
Code

Read Device Code

Extended Memory
Block Verify Code

Note: X = VIL or VIH.

G W

V

V

IL

IL

V

V

IL

IH

V

IHVIH

V

X X X Hi-Z

IH

V

V

IL

IL

V

V

IL

IL

V

V

IL

IL

IL

Address Inputs

DQ15A–1, A0-A20

V

Cell Address Hi-Z Data Output

IH

V

Command Address Hi-Z Data Input

IL

V

X Hi-Z Hi-Z

IH

A0 = VIL, A1 = VIL, A9 = VID,

IH

Others V

A0 = VIH, A1 = VIL,

IH

A9 = V

A0 = VIH, A1 = VIH, A6 = VIL,

IH

A9 = V

IH

or V

IL

IH

, Others VIL or V

ID

, Others VIL or V

ID

IH

IH

Address Inputs

A0-A20

V

Cell Address Data Output

IH

V

Command Address Data Input

IL

Data Inputs/Outputs

DQ14-DQ8 DQ7-DQ0

Hi-Z 20h

Hi-Z

Hi-Z

5Eh (M29DW323DT)
5Fh (M29DW323DB)

01h (not factory locked)

Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

X Hi-Z

A0 = VIL, A1 = VIL, A9 = VID,

V

IH

Others V

A0 = VIH, A1 = VIL, A9 = VID,

V

IH

Others V

A0 = VIH, A1 = VIH, A6 = VIL,

V

IH

A9 = V

or V

IL

IH

or V

IL

IH

, Others VIL or V

ID

225Eh (M29DW323DT)
225Fh (M29DW323DB)

81h (factory locked)

IH

01h (not factory locked)

81h (factory locked)

0020h

14/51

COMMAND INTERFACE

All Bus Write operations to the memory are inter­preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper­ations. Failure to observe a valid sequence of Bus
Write operations will result in the memory return­ing to Read mode. The long command sequences
are imposed to maximize data security.

The address used for the commands changes de­pending on whether the memory is in 16-bit or 8­bit mode. See either Table 5, or 6, depending on
the configuration that is being used, for a summary
of the commands.

Read/Reset Command

The Read/Reset command returns the memory to
its Read mode. It also resets the errors in the Sta­tus Register. Either one or three Bus Write opera­tions can be used to issue the Read/Reset
command.

The Read/Reset command can be issued, be­tween Bus Write cycles before the start of a pro­gram or erase operation, to return the device to
read mode. If the Read/Reset command is issued
during the time-out of a Block erase operation then
the memory will take up to 10µs to abort. During
the abort period no valid data can be read from the
memory. The Read/Reset command will not abort
an Erase operation when issued while in Erase
Suspend.

Auto Select Command

The Auto Select command is used to read the
Manufacturer Code, the Device Code, the Block
Protection Status and the Extended Memory Block
Verify Code. It can be addressed to either Bank.
Three consecutive Bus Write operations are re­quired to issue the Auto Select command. The fi­nal Write cycle must be addressed to one of the
Banks. Once the Auto Select command is issued
Bus Read operations to the Bank where the com­mand was issued output the Auto Select data. Bus
Read operations to the other Bank will output the
contents of the memory array. The memory re­mains in Auto Select mode until a Read/Reset or
CFI Query command is issued.

In Auto Select mode the Manufacturer Code can
be read using a Bus Read operation with A0 = V
and A1 = VIL and A19-A20 = Bank Address. The
other address bits may be set to either V

The Device Code can be read using a Bus Read
operation with A0 = V
= Bank Address. The other address bits may be
set to either V

IL

and A1 = VIL and A19-A20

IH

or VIH.

The Block Protection Status of each block can be
read using a Bus Read operation with A0 = V
A1 = V
specifying the address of the block inside the

, A19-A20 = Bank Address and A12-A18

IH

or VIH.

IL

M29DW323DT, M29DW323DB

Bank. The other address bits may be set to either

or VIH. If the addressed block is protected then

V

IL

01h is output on Data Inputs/Outputs DQ0-DQ7,
otherwise 00h is output.

Read CFI Query Command

The Read CFI Query Command is used to read
data from the Common Flash Interface (CFI)
Memory Area. This command is valid when the de­vice is in the Read Array mode, or when the device
is in Auto Select mode.

One Bus Write cycle is required to issue the Read
CFI Query Command. Once the command is is­sued subsequent Bus Read operations read from
the Common Flash Interface Memory Area.

The Read/Reset command must be issued to re­turn the device to the previous mode (the Read Ar­ray mode or Auto Select mode). A second Read/
Reset command would be needed if the device is
to be put in the Read Array mode from Auto Select
mode.

See APPENDIX B., Tables 25, 26, 27, 28, 29 and

30 for details on the information contained in the

Common Flash Interface (CFI) memory area.

Program Command

The Program command can be used to program a
value to one address in the memory array at a
time. The command requires four Bus Write oper­ations, the final write operation latches the ad­dress and data, and starts the Program/Erase
Controller.

If the address falls in a protected block then the
Program command is ignored, the data remains
unchanged. The Status Register is never read and
no error condition is given.

During the program operation the memory will ig­nore all commands. It is not possible to issue any
command to abort or pause the operation. After
programming has started, Bus Read operations in
the Bank being programmed output the Status
Register content, while Bus Read operations to
the other Bank output the contents of the memory
array. See the section on the Status Register for
more details. Typical program times are given in

Table 7.

IL

After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs Bus
Read operations to the Bank where the command
was issued will continue to output the Status Reg­ister. A Read/Reset command must be issued to
reset the error condition and return to Read mode.

Note that the Program command cannot change a

,

IL

bit set at ’0’ back to ’1’. One of the Erase Com­mands must be used to set all the bits in a block or
in the whole memory from ’0’ to ’1’.

15/51

M29DW323DT, M29DW323DB

Fast Program Commands

There are two Fast Program commands available
to improve the programming throughput, by writing
several adjacent words or bytes in parallel. The
Quadruple Byte Program command is available for
x8 operations, while the Double Word Program
command is available for x16 operations.

Only one bank can be programmed at any one
time. The other bank must be in Read mode or
Erase Suspend.

Fast Program commands should not be attempted
when V
because applying a 12V V
WP

WP is not at VPP. Care must be taken

PP/

pin will temporarily unprotect any protected

voltage to the VPP/

PP

block.
After programming has started, Bus Read opera-

tions in the Bank being programmed output the
Status Register content, while Bus Read opera­tions to the other Bank output the contents of the
memory array.

After the program operation has completed the
memory will return to the Read mode, unless an
error has occurred. When an error occurs Bus
Read operations to the Bank where the command
was issued will continue to output the Status Reg­ister. A Read/Reset command must be issued to
reset the error condition and return to Read mode.

Note that the Fast Program commands cannot
change a bit set at ’0’ back to ’1’. One of the Erase
Commands must be used to set all the bits in a
block or in the whole memory from ’0’ to ’1’.

Typical Program times are given in Table

7., Program, Erase Times and Program, Erase
Endurance Cycles.

Quadruple Byte Program Command. The Qua­druple Byte Program command is used to write a
page of four adjacent Bytes in parallel. The four
bytes must differ only for addresses A0, DQ15A-1.
Five bus write cycles are necessary to issue the
Quadruple Byte Program command.

■ The first bus cycle sets up the Quadruple Byte

Program Command.

■ The second bus cycle latches the Address and

the Data of the first byte to be written.

■ The third bus cycle latches the Address and

the Data of the second byte to be written.

■ The fourth bus cycle latches the Address and

the Data of the third byte to be written.

■ The fifth bus cycle latches the Address and the

Data of the fourth byte to be written and starts
the Program/Erase Controller.

Double Word Program Command. The Double
Word Program command is used to write a page
of two adjacent words in parallel. The two words
must differ only for the address A0.

Three bus write cycles are necessary to issue the
Double Word Program command.

■ The first bus cycle sets up the Double Word

Program Command.

■ The second bus cycle latches the Address and

the Data of the first word to be written.

■ The third bus cycle latches the Address and

the Data of the second word to be written and
starts the Program/Erase Controller.

Unlock Bypass Command

The Unlock Bypass command is used in conjunc­tion with the Unlock Bypass Program command to
program the memory faster than with the standard
program commands. When the cycle time to the
device is long, considerable time saving can be
made by using these commands. Three Bus Write
operations are required to issue the Unlock By­pass command.

Once the Unlock Bypass command has been is­sued the bank enters Unlock Bypass mode. When
in Unlock Bypass mode, only the Unlock Bypass
Program and Unlock Bypass Reset commands
are valid. The Unlock Bypass Program command
can be issued to program addresses within the
bank, and the Unlock Bypass Reset command to
return the bank to Read mode. In Unlock Bypass
mode the memory can be read as if in Read mode.

When V
the memory automatically enters the Unlock By-

is applied to the VPP/Write Protect pin

PP

pass mode and the Unlock Bypass Program com­mand can be issued immediately. Care must be
taken because applying a 12V V
VPP/WP

pin will temporarily unprotect any protect-

voltage to the

PP

ed block.

Unlock Bypass Program Command

The Unlock Bypass Program command can be
used to program one address in the memory array
at a time. The command requires two Bus Write
operations, the final write operation latches the ad­dress and data, and starts the Program/Erase
Controller.

The Program operation using the Unlock Bypass
Program command behaves identically to the Pro­gram operation using the Program command. The
operation cannot be aborted, a Bus Read opera­tion to the Bank where the command was issued
outputs the Status Register. See the Program
command for details on the behavior.

Unlock Bypass Reset Command

The Unlock Bypass Reset command can be used
to return to Read/Reset mode from Unlock Bypass
Mode. Two Bus Write operations are required to
issue the Unlock Bypass Reset command. Read/
Reset command does not exit from Unlock Bypass
Mode.

16/51

M29DW323DT, M29DW323DB

Chip Erase Command

The Chip Erase command can be used to erase
the entire chip. Six Bus Write operations are re­quired to issue the Chip Erase Command and start
the Program/Erase Controller.

If any blocks are protected then these are ignored
and all the other blocks are erased. If all of the
blocks are protected the Chip Erase operation ap­pears to start but will terminate within about 100µs,
leaving the data unchanged. No error condition is
given when protected blocks are ignored.

During the erase operation the memory will ignore
all commands, including the Erase Suspend com­mand. It is not possible to issue any command to
abort the operation. Typical chip erase times are
given in Table 7. All Bus Read operations during
the Chip Erase operation will output the Status
Register on the Data Inputs/Outputs. See the sec­tion on the Status Register for more details.

After the Chip Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs the
memory will continue to output the Status Regis­ter. A Read/Reset command must be issued to re­set the error condition and return to Read Mode.

The Chip Erase Command sets all of the bits in un­protected blocks of the memory to ’1’. All previous
data is lost.

Block Erase Command

The Block Erase command can be used to erase
a list of one or more blocks in a Bank. It sets all of
the bits in the unprotected selected blocks to ’1’.
All previous data in the selected blocks is lost.

Six Bus Write operations are required to select the
first block in the list. Each additional block in the
list can be selected by repeating the sixth Bus
Write operation using the address of the additional
block. All blocks must belong to the same Bank; if
a block belonging to the other Bank is given it will
not be erased. The Block Erase operation starts
the Program/Erase Controller after a time-out pe­riod of 50µs after the last Bus Write operation.
Once the Program/Erase Controller starts it is not
possible to select any more blocks. Each addition­al block must therefore be selected within 50µs of
the last block. The 50µs timer restarts when an ad­ditional block is selected. After the sixth Bus Write
operation a Bus Read operation within the same
Bank will output the Status Register. See the Sta­tus Register section for details on how to identify if
the Program/Erase Controller has started the
Block Erase operation.

If any selected blocks are protected then these are
ignored and all the other selected blocks are
erased. If all of the selected blocks are protected
the Block Erase operation appears to start but will

terminate within about 100µs, leaving the data un­changed. No error condition is given when protect­ed blocks are ignored.

During the Block Erase operation the memory will
ignore all commands except the Erase Suspend
command and the Read/Reset command which is
only accepted during the 50µs time-out period.
Typical block erase times are given in Table 7.

After the Erase operation has started all Bus Read
operations to the Bank being erased will output the
Status Register on the Data Inputs/Outputs. See
the section on the Status Register for more details.

After the Block Erase operation has completed the
memory will return to the Read Mode, unless an
error has occurred. When an error occurs Bus
Read operations to the Bank where the command
was issued will continue to output the Status Reg­ister. A Read/Reset command must be issued to
reset the error condition and return to Read mode.

Erase Suspend Command

The Erase Suspend Command may be used to
temporarily suspend a Block Erase operation and
return the memory to Read mode. The command
requires one Bus Write operation.

The Program/Erase Controller will suspend within
the Erase Suspend Latency time of the Erase Sus­pend Command being issued. Once the Program/
Erase Controller has stopped the memory will be
set to Read mode and the Erase will be suspend­ed. If the Erase Suspend command is issued dur­ing the period when the memory is waiting for an
additional block (before the Program/Erase Con­troller starts) then the Erase is suspended immedi­ately and will start immediately when the Erase
Resume Command is issued. It is not possible to
select any further blocks to erase after the Erase
Resume.

During Erase Suspend it is possible to Read and
Program cells in blocks that are not being erased;
both Read and Program operations behave as
normal on these blocks. If any attempt is made to
program in a protected block or in the suspended
block then the Program command is ignored and
the data remains unchanged. The Status Register
is not read and no error condition is given. Read­ing from blocks that are being erased will output
the Status Register.

It is also possible to issue the Auto Select, Read
CFI Query and Unlock Bypass commands during
an Erase Suspend. The Read/Reset command
must be issued to return the device to Read Array
mode before the Resume command will be ac­cepted.

During Erase Suspend a Bus Read operation to
the Extended Block will output the Extended Block
data.

17/51

M29DW323DT, M29DW323DB

Erase Resume Command

The Erase Resume command must be used to re­start the Program/Erase Controller after an Erase
Suspend. The device must be in Read Array mode
before the Resume command will be accepted. An
erase can be suspended and resumed more than
once.

Enter Extended Block Command

The M29DW323D has an extra 64KByte block
(Extended Block) that can only be accessed using
the Enter Extended Block command. Three Bus
write cycles are required to issue the Extended
Block command. Once the command has been is­sued the device enters Extended Block mode
where all Bus Read or Program operations to the
Boot Block addresses access the Extended Block.
The Extended Block (with the same address as
the boot block) cannot be erased, and can be
treated as one-time programmable (OTP) memo­ry. In Extended Block mode the Boot Blocks are
not accessible. In Extended Block mode dual op-

mapped in Bank A. When in Extended Block
mode, Erase Commands in Bank A are not al­lowed.

To exit from the Extended Block mode the Exit Ex­tended Block command must be issued.

The Extended Block can be protected, however
once protected the protection cannot be undone.

Exit Extended Block Command

The Exit Extended Block command is used to exit
from the Extended Block mode and return the de­vice to Read mode. Four Bus Write operations are
required to issue the command.

Block Protect and Chip Unprotect Commands
Groups of blocks can be protected against acci-

dental Program or Erase. The Protection Groups
are shown in APPENDIX A., Tables 23 and 24,
Block Addresses. The whole chip can be unpro­tected to allow the data inside the blocks to be
changed. Block Protect and Chip Unprotect oper­ations are described in APPENDIX D.

erations are possible, with the Extended Block

Table 5. Commands, 16-bit mode, BYTE

Command

Read/Reset

Auto Select 3 555 AA 2AA 55

Program 4 555 AA 2AA 55 555 A0 PA PD

Double Word Program 3 555 50 PA0 PD0 PA1 PD1

Unlock Bypass 3 555 AA 2AA 55 555 20

Unlock Bypass
Program

Unlock Bypass Reset 2 X 90 X 00

Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10

Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30

Erase Suspend 1 BKA B0

Erase Resume 1 BKA 30

Read CFI Query 1 55 98

Enter Extended Block 3 555 AA 2AA 55 555 88

Exit Extended Block 4 555 AA 2AA 55 555 90 X 00

Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block, BKA Bank Address. All values in the table are in

hexadecimal.
The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15 are Don’t
Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH.

1st 2nd 3rd 4th 5th 6th

Length

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

1X F0

3555 AA 2AA 55 X F0

2X A0PAPD

= V

IH

Bus Write Operations

(BKA)

90

555

18/51

M29DW323DT, M29DW323DB

Table 6. Commands, 8-bit mode, BYTE = V

IL

Bus Write Operations

Command

Read/Reset

Auto Select 3 AAA AA 555 55

1st 2nd 3rd 4th 5th 6th

Length

Add Data Add Data Add Data Add Data Add Data Add Data

1X F0

3 AAA AA 555 55 X F0

(BKA)

90

AAA

Program 4 AAA AA 555 55 AAA A0 PA PD

Quadruple Byte Program 5 AAA 55 PA0 PD0 PA1 PD1 PA2 PD2 PA3 PD3

Unlock Bypass 3 AAA AA 555 55 AAA 20

Unlock Bypass Program 2 X A0 PA PD

Unlock Bypass Reset 2 X 90 X 00

Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10

Block Erase 6+ AAA AA 555 55 AAA 80 AAA AA 555 55 BA 30

Erase Suspend 1 BKA B0

Erase Resume 1 BKA 30

Read CFI Query 1 AA 98

Enter Extended Block 3 AAA AA 555 55 AAA 88

Exit Extended Block 4 AAA AA 555 55 AAA 90 X 00

Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal.

The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15 are Don’t
Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH.

Table 7. Program, Erase Times and Program, Erase Endurance Cycles

Parameter Min

Typ

(1, 2)

Chip Erase 40

Block Erase (64 KBytes) 0.8

Erase Suspend Latency Time

Program (Byte or Word) 10

Double Word Program (Byte or Word) 10

Chip Program (Byte by Byte) 40

Chip Program (Word by Word) 20

Chip Program (Quadruple Byte or Double Word) 10

Program/Erase Cycles (per Block) 100,000 cycles

Data Retention 20 years

Note: 1. Typical values measured at room temperature and nominal voltages.

2. Sampled, but not 100% tested.

3. Maximum value measured at worst case conditions for both temperature and VCC after 100,00 program/erase cycles.

4. Maximum value measured at worst case conditions for both temperature and VCC.

Max

200

6

50

200

200

200

100

100

(2)

(3)

(3)

(4)

(4)

(3)

(3)

(3)

(3)

Unit

s

s

µs

µs

µs

s

s

s

19/51

M29DW323DT, M29DW323DB

STATUS REGISTER

The M29DW323D has a Status Register that pro­vides information on the current or previous Pro­gram or Erase operations executed in each bank.
The various bits convey information and errors on
the operation. Bus Read operations from any ad­dress within the Bank, always read the Status
Register during Program and Erase operations. It
is also read during Erase Suspend when an ad­dress within a block being erased is accessed.

The bits in the Status Register are summarized in

Table 8., Status Register Bits.

Data Polling Bit (DQ7). The Data Polling Bit can
be used to identify whether the Program/Erase
Controller has successfully completed its opera­tion or if it has responded to an Erase Suspend.
The Data Polling Bit is output on DQ7 when the
Status Register is read.

During Program operations the Data Polling Bit
outputs the complement of the bit being pro­grammed to DQ7. After successful completion of
the Program operation the memory returns to
Read mode and Bus Read operations from the ad­dress just programmed output DQ7, not its com­plement.

During Erase operations the Data Polling Bit out­puts ’0’, the complement of the erased state of
DQ7. After successful completion of the Erase op­eration the memory returns to Read Mode.

In Erase Suspend mode the Data Polling Bit will
output a ’1’ during a Bus Read operation within a
block being erased. The Data Polling Bit will
change from a ’0’ to a ’1’ when the Program/Erase
Controller has suspended the Erase operation.

Figure 7., Data Polling Flowchart, gives an exam-

ple of how to use the Data Polling Bit. A Valid Ad­dress is the address being programmed or an
address within the block being erased.

Toggle Bit (DQ6). The Toggle Bit can be used to
identify whether the Program/Erase Controller has
successfully completed its operation or if it has re­sponded to an Erase Suspend. The Toggle Bit is
output on DQ6 when the Status Register is read.

During Program and Erase operations the Toggle
Bit changes from ’0’ to ’1’ to ’0’, etc., with succes­sive Bus Read operations at any address. After
successful completion of the operation the memo­ry returns to Read mode.

During Erase Suspend mode the Toggle Bit will
output when addressing a cell within a block being
erased. The Toggle Bit will stop toggling when the
Program/Erase Controller has suspended the
Erase operation.

Figure 8., Toggle Flowchart, gives an example of

how to use the Data Toggle Bit. Figures 14 and 15
describe Toggle Bit timing waveform.

Error Bit (DQ5). The Error Bit can be used to
identify errors detected by the Program/Erase
Controller. The Error Bit is set to ’1’ when a Pro­gram, Block Erase or Chip Erase operation fails to
write the correct data to the memory. If the Error
Bit is set a Read/Reset command must be issued
before other commands are issued. The Error bit
is output on DQ5 when the Status Register is read.

Note that the Program command cannot change a
bit set to ’0’ back to ’1’ and attempting to do so will
set DQ5 to ‘1’. A Bus Read operation to that ad­dress will show the bit is still ‘0’. One of the Erase
commands must be used to set all the bits in a
block or in the whole memory from ’0’ to ’1’.

Erase Timer Bit (DQ3). The Erase Timer Bit can
be used to identify the start of Program/Erase
Controller operation during a Block Erase com­mand. Once the Program/Erase Controller starts
erasing the Erase Timer Bit is set to ’1’. Before the
Program/Erase Controller starts the Erase Timer
Bit is set to ’0’ and additional blocks to be erased
may be written to the Command Interface. The
Erase Timer Bit is output on DQ3 when the Status
Register is read.

Alternative Toggle Bit (DQ2). The Alternative
Toggle Bit can be used to monitor the Program/
Erase controller during Erase operations. The Al­ternative Toggle Bit is output on DQ2 when the
Status Register is read.

During Chip Erase and Block Erase operations the
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations from addresses
within the blocks being erased. A protected block
is treated the same as a block not being erased.
Once the operation completes the memory returns
to Read mode.

During Erase Suspend the Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive
Bus Read operations from addresses within the
blocks being erased. Bus Read operations to ad­dresses within blocks not being erased will output
the memory cell data as if in Read mode.

After an Erase operation that causes the Error Bit
to be set the Alternative Toggle Bit can be used to
identify which block or blocks have caused the er­ror. The Alternative Toggle Bit changes from ’0’ to
’1’ to ’0’, etc. with successive Bus Read Opera­tions from addresses within blocks that have not
erased correctly. The Alternative Toggle Bit does
not change if the addressed block has erased cor­rectly.

Figures 14 and 15 describe Alternative Toggle Bit
timing waveform.

20/51

M29DW323DT, M29DW323DB

Table 8. Status Register Bits

Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB

Program Bank Address DQ7 Toggle 0 – – 0

Program During Erase
Suspend

Bank Address DQ7

Program Error Bank Address DQ7

Chip Erase Any Address 0 Toggle 0 1 Toggle 0

Block Erase before
timeout

Block Erase

Erase Suspend

Erase Error

Note: Unspecified data bits should be ignored.

Erasing Block 0 Toggle 0 0 Toggle 0

Non-Erasing Block 0 Toggle 0 0 No Toggle 0

Erasing Block 0 Toggle 0 1 Toggle 0

Non-Erasing Block 0 Toggle 0 1 No Toggle

Erasing Block 1 No Toggle 0 – Toggle Hi-Z

Non-Erasing Block Data read as normal Hi-Z

Good Block Address 0 Toggle 1 1 No Toggle Hi-Z

Faulty Block Address 0 Toggle 1 1 Toggle Hi-Z

Figure 7. Data Polling Flowchart Figure 8. Toggle Flowchart

Toggle 0 – – 0

Toggle 1 – – Hi-Z

0

START

READ DQ5 & DQ7

at VALID ADDRESS

DQ7

YES

=

DATA

NO

NO

DQ5

= 1

YES

READ DQ7

at VALID ADDRESS

DQ7

YES

=

DATA

NO

FAIL PASS

AI90194

START

READ DQ6

ADDRESS = BA

READ

DQ5 & DQ6

ADDRESS = BA

DQ6

=

TOGGLE

NO

Note: BA = Address of Bank being Programmed or Erased.

YES

DQ5

= 1

YES

READ DQ6

TWICE

ADDRESS = BA

DQ6

=

TOGGLE

YES

FAIL

NO

NO

PASS

AI08929b

21/51

M29DW323DT, M29DW323DB

DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE

The Multiple Bank Architecture of the
M29DW323DT and M29DW323DB gives greater
flexibility for software developers to split the code
and data spaces within the memory array. The
Dual Operations feature simplifies the software
management of the device by allowing code to be
executed from one bank while the other bank is
being programmed or erased.

The Dual Operations feature means that while pro­gramming or erasing in one bank, read operations
are possible in the other bank with zero latency.

Only one bank at a time is allowed to be in pro­gram or erase mode.

Table 9. Dual Operations Allowed In the Other Bank

Status of First

(1)

Bank

Idle Yes

Programming Yes No No No – – No No

Erasing Yes No No No – – No No

Erase Suspended Yes Yes Yes Yes Yes No - Yes

Note: 1. If one bank is involved in a program or erase operation, then the other bank is available for dual operations.

2. Only after an Erase operation in that bank.

3. Only after an Erase Suspend command in that bank.

Read
Array

Read Status

Register

Ye s

Commands allowed in the Other Bank

Read

(6)

Query

(2)

If a read operation is required in a bank, which is
programming or erasing, the program or erase op­eration can be suspended.

Also if the suspended operation was erase then a
program command can be issued to another
block, so the device can have one block in Erase
Suspend mode, one programming and other
banks in read mode.

By using a combination of these features, read op­erations are possible at any moment.

Table 9. and Table 10. show the dual operations

possible in other banks and in the same bank.
Note that only the commonly used commands are
represented in these tables.

(1)

CFI

Yes Yes Yes Yes

Auto

Select

Program Erase

Erase

Suspend

Ye s

Erase

Resume

(2)

Ye s

(3)

Table 10. Dual Operations Allowed In Same Bank

Commands allowed in same bank

(1)

Read

Status

Register

(5)

Ye s

(4)

Read

CFI Query

Ye s Ye s

Auto

Select

Program Erase

(1)

Ye s

No -

Erase

Suspend

(2)

Ye s

(5)

Ye s

Resume

Status of bank

I d l e Ye s Ye s Ye s Ye s Ye s Ye s

Programming No Yes No No – – No -

Erasing No Yes No No – No

Erase Suspended

Note: 1. Not allowed in the Block or Word that is being erased or programmed.

2. Only after an Erase operation in that bank.

3. Only after an Erase Suspend command in that bank.

4. Read Status Register is not a command. The Status Register can be read during a block program or erase operation.

5. The Status Register can be read by addressing the block being erase suspended.

22/51

Read

Array

Ye s

Erase

(3)

Ye s

-

(4)

Ye s

M29DW323DT, M29DW323DB

MAXIMUM RATING

Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per­manent damage to the device. Exposure to Abso­lute Maximum Rating conditions for extended
periods may affect device reliability. These are

Table 11. Absolute Maximum Ratings

Symbol Parameter Min Max Unit

T

BIAS

T

STG

T

LEAD

V

IO

V

CC

V

ID

V

PP

Note: 1. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), and the European directive on Restrictions on

Hazardous Substances (RoHS) 2002/95/EU.

2. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions.

3. Maximum voltage may overshoot to VCC +2V during transition and for less than 20ns during transitions.

4. VPP must not remain at 12V for more than a total of 80hrs.

Temperature Under Bias –50 125 °C

Storage Temperature –65 150 °C

Lead Temperature during Soldering

Input or Output Voltage

(2,3)

Supply Voltage –0.6 4 V

Identification Voltage –0.6 13.5 V

(4)

Program Voltage –0.6 13.5 V

stress ratings only and operation of the device at
these or any other conditions above those indicat­ed in the Operating sections of this specification is
not implied. Refer also to the Numonyx SURE Pro­gram and other relevant quality documents.

–0.6

(1)

+0.6

V

CC

°C

V

23/51

M29DW323DT, M29DW323DB

DC AND AC PARAMETERS

This section summarizes the operating measure­ment conditions, and the DC and AC characteris­tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement

Table 12. Operating and AC Measurement Conditions

Param eter

Supply Voltage

V

CC

Ambient Operating Temperature –40 85 °C

Load Capacitance (C

)

L

Input Rise and Fall Times 10 ns

Input Pulse Voltages

Input and Output Timing Ref. Voltages

Figure 9. AC Measurement I/O Waveform Figure 10. AC Measurement Load Circuit

Conditions summarized in Table 12., Operating

and AC Measurement Conditions. Designers

should check that the operating conditions in their
circuit match the operating conditions when rely­ing on the quoted parameters.

M29DW323D

Unit70ns

Min Max

2.7 3.6 V

30 pF

0 to V

CC

/2

V

CC

V

V

V

V

CC

VCC/2

0V

AI05557

V

PP

CC

DEVICE
UNDER

0.1µF

0.1µF

CL includes JIG capacitance

TEST

Table 13. Device Capacitance

Symbol Parameter Test Condition Min Max Unit

= 0V

C

IN

C

OUT

Note: Sampled only, not 100% tested.

Input Capacitance

Output Capacitance

24/51

V

IN

V

= 0V

OUT

6pF

12 pF

V

CC

Ω

25k

Ω

25k

C

L

AI05558

M29DW323DT, M29DW323DB

Table 14. DC Characteristics

Symbol Parameter Test Condition Min Max Unit

I

Input Leakage Current

LI

I

Output Leakage Current

LO

(2)

I

CC1

I

CC3

Note: 1. Sampled only, not 100% tested.

Supply Current (Read)

I

Supply Current (Standby)

CC2

Supply Current (Program/

(1,2)

Erase)

V

Input Low Voltage –0.5 0.8 V

IL

V

Input High Voltage

IH

Voltage for V

V

PP

Acceleration

Current for V

I

PP

Acceleration

V

Output Low Voltage

OL

V

Output High Voltage

OH

V

Identification Voltage 11.5 12.5 V

ID

Program/Erase Lockout Supply

V

LKO

Voltage

2. In Dual operations the Supply Current will be the sum of I

/WP Program

PP

/WP Program

PP

Program/Erase

Controller active

V

V

≤ V

0V ≤ V

IN

≤ V

0V ≤ V

OUT

E

= VIL, G = VIH,

f = 6MHz

E

= VCC ±0.2V,

= VCC ±0.2V

RP

V

= 2.7V ±10%

CC

= 2.7V ±10%

CC

= 1.8mA

I

OL

I

= –100µA

OH

(read) and I

CC1

CC

CC

V

PP

V

IL

/WP = V

PP

/WP =
or V

IH

PP

(program/erase).

CC3

±1

±1

10 mA

100

20 mA

20 mA

CC

VCC +0.3

0.7V

11.5 12.5 V

15 mA

0.45 V

–0.4

V

CC

1.8 2.3 V

µA

µA

µA

V

V

25/51

M29DW323DT, M29DW323DB

Figure 11. Read Mode AC Waveforms

A0-A20/
A–1

E

G

DQ0-DQ7/
DQ8-DQ15

BYTE

tAVQV tAXQX

tELQV

tELQX tEHQZ

tBHQV

tELBL/tELBH tBLQZ

tAVAV

VALID

tGLQX tGHQX

tGLQV

tGHQZ

VALID

tEHQX

Table 15. Read AC Characteristics

Symbol Alt Parameter Test Condition M29DW323D Unit

E

t

AVAV

t

AVQ V

t

ELQX

t

ELQV

t

GLQX

t

GLQV

t

EHQZ

t

GHQZ

t

EHQX

t

GHQX

t

AXQX

t

ELBL

t

ELBH

t

BLQZ

t

BHQV

Note: 1. Sampled only, not 100% tested.

t

Address Valid to Next Address Valid

RC

t

Address Valid to Output Valid

ACC

(1)

(1)

(1)

t

Chip Enable Low to Output Transition

LZ

t

Chip Enable Low to Output Valid

CE

t

Output Enable Low to Output Transition

OLZ

t

Output Enable Low to Output Valid

OE

t

Chip Enable High to Output Hi-Z

HZ

(1)

t

Output Enable High to Output Hi-Z

DF

Chip Enable, Output Enable or Address

t

OH

Transition to Output Transition

t

ELFL

Chip Enable to BYTE Low or High Max 5 ns

t

ELFH

t

BYTE Low to Output Hi-Z Max 25 ns

FLQZ

t

BYTE High to Output Valid Max 30 ns

FHQV

= VIL,

= V

G

E

= VIL,

= V

G

G

= V

= V

G

= V

E

= V

E

= V

G

E

= V

Min 70 ns

IL

Max 70 ns

IL

Min 0 ns

IL

Max 70 ns

IL

Min 0 ns

IL

Max 30 ns

IL

Max 25 ns

IL

Max 25 ns

IL

Min 0 ns

AI05559

26/51

Figure 12. Write AC Waveforms, Write Enable Controlled

tAVAV

A0-A20/
A–1

E

G

W

DQ0-DQ7/
DQ8-DQ15

V

CC

RB

tAVWL

tELWL

tVCHEL

VALID

tWLWHtGHWL

tDVWH

M29DW323DT, M29DW323DB

tWLAX

tWHEH

tWHGL

tWHWL

tWHDX

VALID

tWHRL

AI05560

Table 16. Write AC Characteristics, Write Enable Controlled

Symbol Alt Parameter M29DW323D Unit

t

AVAV

t

ELWL

t

WLWH

t

DVW H

t

WHDX

t

WHEH

t

WHWL

t

AVW L

t

WLAX

t

GHWL

t

WHGL

(1)

t

WHRL

t

VCHEL

Note: 1. Sampled only, not 100% tested.

t

Address Valid to Next Address Valid Min 70 ns

WC

t

Chip Enable Low to Write Enable Low Min 0 ns

CS

t

Write Enable Low to Write Enable High Min 45 ns

WP

t

Input Valid to Write Enable High Min 45 ns

DS

t

Write Enable High to Input Transition Min 0 ns

DH

t

Write Enable High to Chip Enable High Min 0 ns

CH

t

Write Enable High to Write Enable Low Min 30 ns

WPH

t

Address Valid to Write Enable Low Min 0 ns

AS

t

Write Enable Low to Address Transition Min 45 ns

AH

Output Enable High to Write Enable Low Min 0 ns

t

Write Enable High to Output Enable Low Min 0 ns

OEH

t

Program/Erase Valid to RB Low Max 30 ns

BUSY

t

VCSVCC

High to Chip Enable Low

Min 50 µs

27/51

M29DW323DT, M29DW323DB

Figure 13. Write AC Waveforms, Chip Enable Controlled

tAVAV

A0-A20/
A–1

W

G

E

DQ0-DQ7/
DQ8-DQ15

V

CC

RB

tAVEL

tWLEL

tVCHWL

VALID

tELEHtGHEL

tDVEH

tELAX

tEHWH

tEHGL

tEHEL

tEHDX

VALID

tEHRL

AI05561

Table 17. Write AC Characteristics, Chip Enable Controlled

Symbol Alt Parameter M29DW323D Unit

t

AVAV

t

WLEL

t

ELEH

t

DVEH

t

EHDX

t

EHWH

t

EHEL

t

AVEL

t

ELAX

t

GHEL

t

EHGL

(1)

t

EHRL

t

VCHWL

Note: 1. Sampled only, not 100% tested.

28/51

t

Address Valid to Next Address Valid Min 70 ns

WC

t

Write Enable Low to Chip Enable Low Min 0 ns

WS

t

Chip Enable Low to Chip Enable High Min 45 ns

CP

t

Input Valid to Chip Enable High Min 45 ns

DS

t

Chip Enable High to Input Transition Min 0 ns

DH

t

Chip Enable High to Write Enable High Min 0 ns

WH

t

Chip Enable High to Chip Enable Low Min 30 ns

CPH

t

Address Valid to Chip Enable Low Min 0 ns

AS

t

Chip Enable Low to Address Transition Min 45 ns

AH

Output Enable High Chip Enable Low Min 0 ns

t

Chip Enable High to Output Enable Low Min 0 ns

OEH

t

Program/Erase Valid to RB Low Max 30 ns

BUSY

t

VCSVCC

High to Write Enable Low

Min 50 µs

M29DW323DT, M29DW323DB

Figure 14. Toggle and Alternative Toggle Bits Mechanism, Chip Enable Controlled

A0-A20

E

G

(1)

DQ2

Note: 1. The Toggle bit is output on DQ6.

2. The Alternative Toggle bit is output on DQ2.

Address Outside the Bank

Being Programmed or Erased

(2)

/DQ6

Read Operation outside the Bank

Being Programmed or Erased

Data Data

Address in the Bank

Being Programmed or Erased

tAXEL

tELQV

Alternative Toggle/

Toggle Bit

Read Operation in the Bank

Being Programmed or Erased

tELQV

Alternative Toggle/

Address Outside the Bank

Being Programmed or Erased

Toggle Bit

Read Operation Outside the Bank

Being Programmed or Erased

Figure 15. Toggle and Alternative Toggle Bits Mechanism, Output Enable Controlled

A0-A20

G

E

(1)

DQ2

Address Outside the Bank

Being Programmed or Erased

(2)

/DQ6

Address in the Bank

Being Programmed or Erased

tAXGL

tGLQV

Data Data

Alternative Toggle/

Toggle Bit

tGLQV

Alternative Toggle/

Address Outside the Bank

Being Programmed or Erased

Toggle Bit

AI08914c

Read Operation outside the Bank

Being Programmed or Erased

Note: 1. The Toggle bit is output on DQ6.

2. The Alternative Toggle bit is output on DQ2.

Read Operation in the Bank

Being Programmed or Erased

Read Operation Outside the Bank

Being Programmed or Erased

Table 18. Toggle and Alternative Toggle Bits AC Characteristics

Symbol Alt Parameter M29DW323D Unit

Note: t

t

AXEL

t

AXGL

ELQV

and t

GLQV

Address Transition to Chip Enable Low Min 10 ns

Address Transition to Output Enable Low Min 10 ns

value s are presented in Table 15., Read AC Characteristics.

AI08915c

29/51

M29DW323DT, M29DW323DB

Figure 16. Reset/Block Temporary Unprotect AC Waveforms

E, G

W,

tPHWL, tPHEL, tPHGL

RB

tRHWL, tRHEL, tRHGL

RP

Table 19. Reset/Block Temporary Unprotect AC Characteristics

Symbol Alt Parameter M29DW323D Unit

(1)

t

PHWL

t

PHEL

(1)

t

PHGL

(1)

t

RHWL

(1)

t

RHEL

(1)

t

RHGL

t

PLPX

t

PLYH

(1)

t

PHPHH

(1)

t

VHVPP

Note: 1. Sampled only, not 100% tested.

t

RH

t

RB

t

RP

t

READY

t

VIDR

tPLPX

tPHPHH

tPLYH

AI02931B

RP High to Write Enable Low, Chip Enable Low,
Output Enable Low

RB High to Write Enable Low, Chip Enable Low,
Output Enable Low

Min 50 ns

Min 0 ns

RP Pulse Width Min 500 ns

RP Low to Read Mode Max 50 µs

RP Rise Time to V

ID

VPP Rise and Fall Time

Min 500 ns

Min 250 ns

Figure 17. Accelerated Program Timing Waveforms

V

VPP/WP

30/51

PP

V

or V

IL

IH

tVHVPP

tVHVPP

AI05563

M29DW323DT, M29DW323DB

PACKAGE MECHANICAL

Figure 18. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Bottom View Package Outline

1

48

e

D1

24

E1

B

25

L1

A2

E

DIE

LA1 α

C

CP

Note: Drawing not to scale.

TSOP-G

Table 20. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Package Mechanical Data

Symbol

A 1.200 0.0472

A1 0.100 0.050 0.150 0.0039 0.0020 0.0059

A2 1.000 0.950 1.050 0.0394 0.0374 0.0413

B 0.220 0.170 0.270 0.0087 0.0067 0.0106

C 0.100 0.210 0.0039 0.0083

CP 0.080 0.0031

D1 12.000 11.900 12.100 0.4724 0.4685 0.4764

E 20.000 19.800 20.200 0.7874 0.7795 0.7953

E1 18.400 18.300 18.500 0.7244 0.7205 0.7283

e 0.500 – – 0.0197 – –

L 0.600 0.500 0.700 0.0236 0.0197 0.0276

L1 0.800 0.0315

α 305305

Typ Min Max Typ Min Max

millimeters inches

A

31/51

M29DW323DT, M29DW323DB

Figure 19. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Bottom View Package Outline

D

FD

FE

BALL "A1"

E1E

eb

A

Note: Drawing not to scale.

Table 21. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Package Mechanical Data

Symbol

A 1.200 0.0472

A1 0.260 0.0102

A2 0.900 0.0354

b 0.350 0.450 0.0138 0.0177

D 6.000 5.900 6.100 0.2362 0.2323 0.2402

D1 4.000 – – 0.1575 – –

ddd 0.100 0.0039

E 8.000 7.900 8.100 0.3150 0.3110 0.3189

E1 5.600 – – 0.2205 – –

e 0.800 – – 0.0315 – –

FD 1.000 – – 0.0394 – –

FE 1.200 – – 0.0472 – –

SD 0.400 – – 0.0157 – –

SE 0.400 – – 0.0157 – –

Typ Min Max Typ Min Max

millimeters inches

D1

SD

SE

ddd

e

A2

A1

BGA-Z32

32/51

M29DW323DT, M29DW323DB

PART NUMBERING

Table 22. Ordering Information Scheme

Example: M29DW323DB 70 N 1 T

Device Type

M29

Architecture

D = Dual Operation

Operating Voltage

= 2.7 to 3.6V

W = V

CC

Device Function

323D = 32 Mbit (x8/x16), Boot Block, 1/4-3/4 partitioning

Array Matrix

T = Top Boot
B = Bottom Boot

Speed

70 = 70 ns

Package

N = TSOP48: 12 x 20 mm
ZE = TFBGA48: 6 x 8mm, 0.8mm pitch

Temperature Range

1 = 0 to 70 °C
6 = –40 to 85 °C

Option

Blank = Standard Packing
T = Tape & Reel Packing
E = Lead-free Package, Standard Packing
F = Lead-free Package, Tape & Reel Packing

Note: This product is also available with the Extended Block factory locked. For further details and ordering
information contact your nearest Numonyx sales office.

Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,

please contact the Numonyx Sales Office nearest to you.

33/51

M29DW323DT, M29DW323DB

APPENDIX A. BLOCK ADDRESSES

Table 23. Top Boot Block Addresses, M29DW323DT

Block

Bank

0 64/32 Protection Group 000000h–00FFFFh 000000h–07FFFh

1 64/32

2 64/32 020000h–02FFFFh 010000h–17FFFh

3 64/32 030000h–03FFFFh 018000h–01FFFFh

4 64/32

5 64/32 050000h–05FFFFh 028000h–02FFFFh

6 64/32 060000h–06FFFFh 030000h–037FFFh

7 64/32 070000h–07FFFFh 038000h–03FFFFh

8 64/32

9 64/32 090000h–09FFFFh 048000h–04FFFFh

10 64/32 0A0000h–0AFFFFh 050000h–057FFFh

11 64/32 0B0000h–0BFFFFh 058000h–05FFFFh

12 64/32

13 64/32 0D0000h–0DFFFFh 068000h–06FFFFh

14 64/32 0E0000h–0EFFFFh 070000h–077FFFh

15 64/32 0F0000h–0FFFFFh 078000h–07FFFFh

16 64/32

Bank B

17 64/32 110000h–11FFFFh 088000h–08FFFFh

18 64/32 120000h–12FFFFh 090000h–097FFFh

19 64/32 130000h–13FFFFh 098000h–09FFFFh

20 64/32

21 64/32 150000h–15FFFFh 0A8000h–0AFFFFh

22 64/32 160000h–16FFFFh 0B0000h–0B7FFFh

23 64/32 170000h–17FFFFh 0B8000h–0BFFFFh

24 64/32

25 64/32 190000h–19FFFFh 0C8000h–0CFFFFh

26 64/32 1A0000h–1AFFFFh 0D0000h–0D7FFFh

27 64/32 1B0000h–1BFFFFh 0D8000h–0DFFFFh

28 64/32

29 64/32 1D0000h–1DFFFFh 0E8000h–0EFFFFh

30 64/32 1E0000h–1EFFFFh 0F0000h–0F7FFFh

31 64/32 1F0000h–1FFFFFh 0F8000h–0FFFFFh

(Kbytes/
Kwords)

Protection Block

Group

Protection Group

Protection Group

Protection Group

Protection Group

Protection Group

Protection Group

Protection Group

Protection Group

(x8) (x16)

010000h–01FFFFh 008000h–0FFFFh

040000h–04FFFFh 020000h–027FFFh

080000h–08FFFFh 040000h–047FFFh

0C0000h–0CFFFFh 060000h–067FFFh

100000h–10FFFFh 080000h–087FFFh

140000h–14FFFFh 0A0000h–0A7FFFh

180000h–18FFFFh 0C0000h–0C7FFFh

1C0000h–1CFFFFh 0E0000h–0E7FFFh

34/51

M29DW323DT, M29DW323DB

Block

Bank

32 64/32

33 64/32 210000h–21FFFFh 108000h–10FFFFh

34 64/32 220000h–22FFFFh 110000h–117FFFh

35 64/32 230000h–23FFFFh 118000h–11FFFFh

36 64/32

37 64/32 250000h–25FFFFh 128000h–12FFFFh

38 64/32 260000h–26FFFFh 130000h–137FFFh

39 64/32 270000h–27FFFFh 138000h–13FFFFh

40 64/32

Bank B

41 64/32 290000h–29FFFFh 148000h–14FFFFh

42 64/32 2A0000h–2AFFFFh 150000h–157FFFh

43 64/32 2B0000h–2BFFFFh 158000h–15FFFFh

44 64/32

45 64/32 2D0000h–2DFFFFh 168000h–16FFFFh

46 64/32 2E0000h–2EFFFFh 170000h–177FFFh

47 64/32 2F0000h–2FFFFFh 178000h–17FFFFh

48 64/32

49 64/32 310000h–31FFFFh 188000h–18FFFFh

50 64/32 320000h–32FFFFh 190000h–197FFFh

51 64/32 330000h–33FFFFh 198000h–19FFFFh

52 64/32

53 64/32 350000h–35FFFFh 1A8000h–1AFFFFh

54 64/32 360000h–36FFFFh 1B0000h–1B7FFFh

55 64/32 370000h–37FFFFh 1B8000h–1BFFFFh

Bank A

56 64/32

57 64/32 390000h–39FFFFh 1C8000h–1CFFFFh

58 64/32 3A0000h–3AFFFFh 1D0000h–1D7FFFh

59 64/32 3B0000h–3BFFFFh 1D8000h–1DFFFFh

60 64/32

61 64/32 3D0000h–3DFFFFh 1E8000h–1EFFFFh

62 64/32 3E0000h–3EFFFFh 1F0000h–1F7FFFh

(Kbytes/
Kwords)

Protection Block

Group

Protection Group

Protection Group

Protection Group

Protection Group

Protection Group

Protection Group

Protection Group

Protection Group

(x8) (x16)

200000h–20FFFFh 100000h–107FFFh

240000h–24FFFFh 120000h–127FFFh

280000h–28FFFFh 140000h–147FFFh

2C0000h–2CFFFFh 160000h–167FFFh

300000h–30FFFFh 180000h–187FFFh

340000h–34FFFFh 1A0000h–1A7FFFh

380000h–38FFFFh 1C0000h–1C7FFFh

3C0000h–3CFFFFh 1E0000h–1E7FFFh

35/51

M29DW323DT, M29DW323DB

(Kbytes/
Kwords)

Bank

Block

63 8/4 Protection Group

64 8/4 Protection Group

65 8/4 Protection Group

66 8/4 Protection Group

67 8/4 Protection Group

Bank A

68 8/4 Protection Group

69 8/4 Protection Group

70 8/4 Protection Group

Note: 1. Used as the Extended Block Addresses in Extended Block mode.

Protection Block

Group

3F0000h–3F1FFFh

3F2000h–3F3FFFh

3F4000h–3F5FFFh

3F6000h–3F7FFFh

3F8000h–3F9FFFh

3FA000h–3FBFFFh

3FC000h–3FDFFFh

3FE000h–3FFFFFh

(x8) (x16)

(1)

(1)

(1)

(1)

(1)

(1)

(1)

(1)

1F8000h–1F8FFFh

1F9000h–1F9FFFh

1FA000h–1FAFFFh

1FB000h–1FBFFFh

1FC000h–1FCFFFh

1FD000h–1FDFFFh

1FE000h–1FEFFFh

1FF000h–1FFFFFh

(1)

(1)

(1)

(1)

(1)

(1)

(1)

(1)

36/51

Table 24. Bottom Boot Block Addresses, M29DW323DB

(Kbytes/
Kwords)

Bank

Block

0 8/4 Protection Group

1 8/4 Protection Group

2 8/4 Protection Group

3 8/4 Protection Group

4 8/4 Protection Group

5 8/4 Protection Group

6 8/4 Protection Group

7 8/4 Protection Group

8 64/32

9 64/32 020000h-02FFFFh 010000h–017FFFh

10 64/32 030000h-03FFFFh 018000h–01FFFFh

11 64/32

Bank A

12 64/32 050000h-05FFFFh 028000h–02FFFFh

13 64/32 060000h-06FFFFh 030000h–037FFFh

14 64/32 070000h-07FFFFh 038000h–03FFFFh

15 64/32

16 64/32 090000h-09FFFFh 048000h–04FFFFh

17 64/32 0A0000h-0AFFFFh 050000h–057FFFh

18 64/32 0B0000h-0BFFFFh 058000h–05FFFFh

19 64/32

20 64/32 0D0000h-0DFFFFh 068000h–06FFFFh

21 64/32 0E0000h-0EFFFFh 070000h–077FFFh

22 64/32 0F0000h-0FFFFFh 078000h–07FFFFh

23 64/32

24 64/32 110000h-11FFFFh 088000h–08FFFFh

25 64/32 120000h-12FFFFh 090000h–097FFFh

26 64/32 130000h-13FFFFh 098000h–09FFFFh

27 64/32

Bank B

28 64/32 150000h-15FFFFh 0A8000h–0AFFFFh

29 64/32 160000h-16FFFFh 0B0000h–0B7FFFh

30 64/32 170000h-17FFFFh 0B8000h–0BFFFFh

Protection Block

Group

000000h-001FFFh

002000h-003FFFh

004000h-005FFFh

006000h-007FFFh

008000h-009FFFh

00A000h-00BFFFh

00C000h-00DFFFh

00E000h-00FFFFh

010000h-01FFFFh 008000h–00FFFFh

Protection Group

040000h-04FFFFh 020000h–027FFFh

Protection Group

080000h-08FFFFh 040000h–047FFFh

Protection Group

0C0000h-0CFFFFh 060000h–067FFFh

Protection Group

100000h-10FFFFh 080000h–087FFFh

Protection Group

140000h-14FFFFh 0A0000h–0A7FFFh

Protection Group

M29DW323DT, M29DW323DB

(x8) (x16)

(1)

(1)

(1)

(1)

(1)

(1)

(1)

(1)

000000h–000FFFh

001000h–001FFFh

002000h–002FFFh

003000h–003FFFh

004000h–004FFFh

005000h–005FFFh

006000h–006FFFh

007000h–007FFFh

(1)

(1)

(1)

(1)

(1)

(1)

(1)

(1)

37/51

M29DW323DT, M29DW323DB

Block

Bank

31 64/32

32 64/32 190000h-19FFFFh 0C8000h–0CFFFFh

33 64/32 1A0000h-1AFFFFh 0D0000h–0D7FFFh

34 64/32 1B0000h-1BFFFFh 0D8000h–0DFFFFh

35 64/32

36 64/32 1D0000h-1DFFFFh 0E8000h–0EFFFFh

37 64/32 1E0000h-1EFFFFh 0F0000h–0F7FFFh

38 64/32 1F0000h-1FFFFFh 0F8000h–0FFFFFh

39 64/32

40 64/32 210000h-21FFFFh 108000h–10FFFFh

41 64/32 220000h-22FFFFh 110000h–117FFFh

42 64/32 230000h-23FFFFh 118000h–11FFFFh

43 64/32

44 64/32 250000h-25FFFFh 128000h–12FFFFh

45 64/32 260000h-26FFFFh 130000h–137FFFh

46 64/32 270000h-27FFFFh 138000h–13FFFFh

47 64/32

Bank B

48 64/32 290000h-29FFFFh 148000h–14FFFFh

49 64/32 2A0000h-2AFFFFh 150000h–157FFFh

50 64/32 2B0000h-2BFFFFh 158000h–15FFFFh

51 64/32

52 64/32 2D0000h-2DFFFFh 168000h–16FFFFh

53 64/32 2E0000h-2EFFFFh 170000h–177FFFh

54 64/32 2F0000h-2FFFFFh 178000h–17FFFFh

55 64/32

56 64/32 310000h-31FFFFh 188000h–18FFFFh

57 64/32 320000h-32FFFFh 190000h–197FFFh

58 64/32 330000h-33FFFFh 198000h–19FFFFh

59 64/32

60 64/32 350000h-35FFFFh 1A8000h–1AFFFFh

61 64/32 360000h-36FFFFh 1B0000h–1B7FFFh

62 64/32 370000h-37FFFFh 1B8000h–1BFFFFh

(Kbytes/
Kwords)

Protection Block

Group

Protection Group

Protection Group

Protection Group

Protection Group

Protection Group

Protection Group

Protection Group

Protection Group

(x8) (x16)

180000h-18FFFFh 0C0000h–0C7FFFh

1C0000h-1CFFFFh 0E0000h–0E7FFFh

200000h-20FFFFh 100000h–107FFFh

240000h-24FFFFh 120000h–127FFFh

280000h-28FFFFh 140000h–147FFFh

2C0000h-2CFFFFh 160000h–167FFFh

300000h-30FFFFh 180000h–187FFFh

340000h-34FFFFh 1A0000h–1A7FFFh

38/51

M29DW323DT, M29DW323DB

Block

Bank

63 64/32

64 64/32 390000h-39FFFFh 1C8000h–1CFFFFh

65 64/32 3A0000h-3AFFFFh 1D0000h–1D7FFFh

66 64/32 3B0000h-3BFFFFh 1D8000h–1DFFFFh

67 64/32

Bank B

68 64/32 3D0000h-3DFFFFh 1E8000h–1EFFFFh

69 64/32 3E0000h-3EFFFFh 1F0000h–1F7FFFh

70 64/32 Protection Group 3F0000h-3FFFFFh 1F8000h–1FFFFFh

Note: 1. Used as the Extended Block Addresses in Extended Block mode.

(Kbytes/
Kwords)

Protection Block

Group

380000h-38FFFFh 1C0000h–1C7FFFh

Protection Group

3C0000h-3CFFFFh 1E0000h–1E7FFFh

Protection Group

(x8) (x16)

39/51

M29DW323DT, M29DW323DB

APPENDIX B. COMMON FLASH INTERFACE (CFI)

The Common Flash Interface is a JEDEC ap­proved, standardized data structure that can be
read from the Flash memory device. It allows a
system software to query the device to determine
various electrical and timing parameters, density
information and functions supported by the mem­ory. The system can interface easily with the de­vice, enabling the software to upgrade itself when
necessary.

When the CFI Query Command is issued the de­vice enters CFI Query mode and the data structure

Table 25. Query Structure Overview

Address

x16 x8

10h 20h CFI Query Identification String Command set ID and algorithm data offset

1Bh 36h System Interface Information Device timing & voltage information

27h 4Eh Device Geometry Definition Flash device layout

40h 80h

61h C2h Security Code Area 64 bit unique device number

Note: Query data are always presented on the lowest order data outputs.

Primary Algorithm-specific Extended
Query table

Sub-section Name Description

Table 26. CFI Query Identification String

Address

x16 x8

10h 20h 0051h “Q”

11h 22h 0052h Query Unique ASCII String "QRY" "R"

12h 24h 0059h "Y"

13h 26h 0002h

14h 28h 0000h

15h 2Ah 0040h

16h 2Ch 0000h

17h 2Eh 0000h

18h 30h 0000h

19h 32h 0000h

1Ah 34h 0000h

Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

Data Description Value

Primary Algorithm Command Set and Control Interface ID code 16 bit
ID code defining a specific algorithm

Address for Primary Algorithm extended Query table (see Table 29.) P = 40h

Alternate Vendor Command Set and Control Interface ID Code second
vendor - specified algorithm supported

Address for Alternate Algorithm extended Query table

is read from the memory. Tables 25, 26, 27, 28, 29
and 30 show the addresses used to retrieve the
data.

The CFI data structure also contains a security
area where a 64 bit unique security number is writ­ten (see Table 30., Security Code Area). This area
can be accessed only in Read mode by the final
user. It is impossible to change the security num­ber after it has been written by Numonyx.

Additional information specific to the Primary
Algorithm (optional)

AMD

Compatible

NA

NA

40/51

Table 27. CFI Query System Interface Information

Address

x16 x8

1Bh 36h 0027h

1Ch 38h 0036h

1Dh 3Ah 00B5h

1Eh 3Ch 00C5h

1Fh 3Eh 0004h

20h 40h 0000h

21h 42h 000Ah

22h 44h 0000h

23h 46h 0004h

24h 48h 0000h

25h 4Ah 0003h

26h 4Ch 0000h

Data Description Value

V

Logic Supply Minimum Program/Erase voltage

CC

bit 7 to 4BCD value in volts
bit 3 to 0BCD value in 100 mV

Logic Supply Maximum Program/Erase voltage

V

CC

bit 7 to 4BCD value in volts
bit 3 to 0BCD value in 100 mV

V

[Programming] Supply Minimum Program/Erase voltage

PP

bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV

[Programming] Supply Maximum Program/Erase voltage

V

PP

bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV

Typical timeout per single byte/word program = 2

Typical timeout for minimum size write buffer program = 2

Typical timeout per individual block erase = 2

Typical timeout for full Chip Erase = 2

Maximum timeout for byte/word program = 2

Maximum timeout for write buffer program = 2

Maximum timeout per individual block erase = 2

Maximum timeout for Chip Erase = 2

M29DW323DT, M29DW323DB

n

µs

n

µs

n

ms

n

ms

n

times typical

n

times typical

n

times typical

n

times typical

2.7V

3.6V

11.5V

12.5V

16µs

NA

1s

NA

256 µs

NA

8s

NA

Table 28. Device Geometry Definition

Address

x16 x8

27h 4Eh 0016h

28h
29h

2Ah
2Bh

50h
52h

54h
56h

2Ch 58h 0002h

2Dh
2Eh

2Fh
30h

31h
32h

33h
34h

Note: For the M29DW323DB, Region 1 corresponds to addresses 000000h to 007FFFh and Region 2 to addresses 008000h to 1FFFFFh.

For the M29DW323DT, Region 1 corresponds to addresses 1F8000h to 1FFFFFh and Region 2 to addresses 000000h to 1F7FFFh.

5Ah
5Ch

5Eh
60h

62h
64h

66h
68h

Data Description Value

0002h
0000h

0000h
0000h

0007h
0000h

0020h
0000h

003Eh

0000h

0000h
0001h

Device Size = 2

n

in number of bytes

Flash Device Interface Code description

Maximum number of bytes in multi-byte program or page = 2

Number of Erase Block Regions. It specifies the number of
regions containing contiguous Erase Blocks of the same size.

Region 1 Information
Number of Erase Blocks of identical size = 0007h+1

Region 1 Information
Block size in Region 1 = 0020h * 256 byte

Region 2 Information
Number of Erase Blocks of identical size = 003Eh+1

Region 2 Information
Block size in Region 2 = 0100h * 256 byte

4 MByte

x8, x16
Async.

n

NA

8Kbyte

64Kbyte

2

8

63

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M29DW323DT, M29DW323DB

Table 29. Primary Algorithm-Specific Extended Query Table

Address

x16 x8

40h 80h 0050h

41h 82h 0052h "R"

42h 84h 0049h "I"

43h 86h 0031h Major version number, ASCII "1"

44h 88h 0030h Minor version number, ASCII "0"

45h 8Ah 0000h Address Sensitive Unlock (bits 1 to 0)

46h 8Ch 0002h Erase Suspend

47h 8Eh 0001h Block Protection

48h 90h 0001h Temporary Block Unprotect

49h 92h 0004h Block Protect /Unprotect

4Ah 94h 0030h Simultaneous Operations,

4Bh 96h 0000h Burst Mode, 00 = not supported, 01 = supported No

4Ch 98h 0000h Page Mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word No

4Dh 9Ah 00B5h V

4Eh 9Ch 00C5h V

4Fh 9Eh 000xh Top/Bottom Boot Block Flag

Data Description Value

Primary Algorithm extended Query table unique ASCII string “PRI”

00 = required, 01= not required
Silicon Revision Number (bits 7 to 2)

00 = not supported, 01 = Read only, 02 = Read and Write

00 = not supported, x = number of blocks in per group

00 = not supported, 01 = supported

04 = M29DW323D

x = number of blocks in Bank B

Supply Minimum Program/Erase voltage

PP

bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV

Supply Maximum Program/Erase voltage

PP

bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV

02h = Bottom Boot device, 03h = Top Boot device

"P"

Ye s

2

1

Ye s

04

48

11.5V

12.5V

–

Table 30. Security Code Area

Address

x16 x8

61h C3h, C2h XXXX

62h C5h, C4h XXXX

63h C7h, C6h XXXX

64h C9h, C8h XXXX

42/51

Data Description

64 bit: unique device number

APPENDIX C. EXTENDED MEMORY BLOCK

The M29DW323D has an extra block, the Extend­ed Block, that can be accessed using a dedicated
command.

This Extended Block is 32 KWords in x16 mode
and 64 KBytes in x8 mode. It is used as a security
block (to provide a permanent security identifica­tion number) or to store additional information.

The Extended Block is either Factory Locked or
Customer Lockable, its status is indicated by bit
DQ7. This bit is permanently set to either ‘1’ or ‘0’
at the factory and cannot be changed. When set to
‘1’, it indicates that the device is factory locked and
the Extended Block is protected. When set to ‘0’, it
indicates that the device is customer lockable and
the Extended Block is unprotected. Bit DQ7 being
permanently locked to either ‘1’ or ‘0’ is another
security feature which ensures that a customer
lockable device cannot be used instead of a facto­ry locked one.

Bit DQ7 is the most significant bit in the Extended
Block Verify Code and a specific procedure must
be followed to read it. See “Extended Memory
Block Verify Code

tions, BYTE = V

, respectively, for details of how to read bit

V

IH

DQ7.

” in Tables 3 and 4, Bus Opera-

and Bus Operations, BYTE =

IL

The Extended Block can only be accessed when
the device is in Extended Block mode. For details
of how the Extended Block mode is entered and
exited, refer to the Enter Extended Block Com-

mand and Exit Extended Block Command para-

graphs, and to Tables 5 and 6, “Commands, 16-bit

mode, BYTE = V
BYTE = V

IL

” and “Commands, 8-bit mode,

IH

”, respectively.

Factory Locked Extended Block

In devices where the Extended Block is factory
locked, the Security Identification Number is writ­ten to the Extended Block address space (see Ta-

ble 31., Extended Block Address and Data) in the

factory. The DQ7 bit is set to ‘1’ and the Extended
Block cannot be unprotected.

Customer Lockable Extended Block

A device where the Extended Block is customer
lockable is delivered with the DQ7 bit set to ‘0’ and
the Extended Block unprotected. It is up to the
customer to program and protect the Extended
Block but care must be taken because the protec­tion of the Extended Block is not reversible.

There are two ways of protecting the Extended
Block:

■ Issue the Enter Extended Block command to

■ Issue the Enter Extended Block command to

Once the Extended Block is programmed and pro­tected, the Exit Extended Block command must be
issued to exit the Extended Block mode and return
the device to Read mode.

M29DW323DT, M29DW323DB

place the device in Extended Block mode,
then use the In-System Technique with RP
either at V
In-System Technique and to the

or at V

IH

(refer to APPENDIX D.,

ID

corresponding flowcharts, Figures 22 and 23,
for a detailed explanation of the technique).

place the device in Extended Block mode,
then use the Programmer Technique (refer to

APPENDIX D., Programmer Technique and to

the corresponding flowcharts, Figures 20 and

21, for a detailed explanation of the

technique).

Table 31. Extended Block Address and Data

(1)

Device

M29DW323DT

M29DW323DB

Note: 1. See Tables 23 and 24, Top and Bottom Boot Block Addresses.

3F0000h-3F000Fh 1F8000h-1F8007h

3F0010h-3FFFFFh 1F8008h-1FFFFFh Unavailable

000000h-00000Fh 000000h-000007h

000010h-00FFFFh 000008h-007FFFh Unavailable

Address

x8 x16 Factory Locked Customer Lockable

Security Identification

Number

Security Identification

Number

Data

Determined by

Customer

Determined by

Customer

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M29DW323DT, M29DW323DB

APPENDIX D. BLOCK PROTECTION

Block protection can be used to prevent any oper­ation from modifying the data stored in the memo­ry. The blocks are protected in groups, refer to

APPENDIX A., Tables 23 and 24 for details of the

Protection Groups. Once protected, Program and
Erase operations within the protected group fail to
change the data.

There are three techniques that can be used to
control Block Protection, these are the Program­mer technique, the In-System technique and Tem­porary Unprotection. Temporary Unprotection is
controlled by the Reset/Block Temporary Unpro­tection pin, RP
scriptions section.

Programmer Technique

The Programmer technique uses high (V
age levels on some of the bus pins. These cannot
be achieved using a standard microprocessor bus,
therefore the technique is recommended only for
use in Programming Equipment.

To protect a group of blocks follow the flowchart in

Figure 20., Programmer Equipment Group Protect
Flowchart. To unprotect the whole chip it is neces-

sary to protect all of the groups first, then all
groups can be unprotected at the same time. To
unprotect the chip follow Figure 21., Programmer

Equipment Chip Unprotect Flowchart. Table

32., Programmer Technique Bus Operations,
BYTE = V

ation.
The timing on these flowcharts is critical. Care

should be taken to ensure that, where a pause is

; this is described in the Signal De-

) volt-

ID

or VIL, gives a summary of each oper-

IH

specified, it is followed as closely as possible. Do
not abort the procedure before reaching the end.
Chip Unprotect can take several seconds and a
user message should be provided to show that the
operation is progressing.

In-System Technique

The In-System technique requires a high voltage
level on the Reset/Blocks Temporary Unprotect

(1)

pin, RP

. This can be achieved without violating
the maximum ratings of the components on the mi­croprocessor bus, therefore this technique is suit­able for use after the memory has been fitted to
the system.

To protect a group of blocks follow the flowchart in

Figure 22., In-System Equipment Group Protect
Flowchart. To unprotect the whole chip it is neces-

sary to protect all of the groups first, then all the
groups can be unprotected at the same time. To
unprotect the chip follow Figure 23., In-System

Equipment Chip Unprotect Flowchart.

The timing on these flowcharts is critical. Care
should be taken to ensure that, where a pause is
specified, it is followed as closely as possible. Do
not allow the microprocessor to service interrupts
that will upset the timing and do not abort the pro­cedure before reaching the end. Chip Unprotect
can take several seconds and a user message
should be provided to show that the operation is
progressing.

Note: 1. RP can be either at V

tem Technique to protect the Extended Block.

IH

or at V

when using the In-Sys-

ID

Table 32. Programmer Technique Bus Operations, BYTE = VIH or V

Operation E G W

Block (Group)

(1)

Protect

Chip Unprotect

Block (Group)
Protection Verify

Block (Group)
Unprotection Verify

Note: 1. Block Protection Groups are shown in APPENDIX A., Tables 23 and 24.

44/51

VILVIDVIL Pulse

V

IDVIDVIL

V

ILVIL

V

ILVIL

Pulse

V

IH

V

IH

A0 = VIL, A1 = VIH, A6 = VIL, A9 = VID,

A0 = VIL, A1 = VIH, A6 = VIH, A9 = VID,

Address Inputs

A0-A20

A9 = V

, A12-A20 Block Address

ID

Others = X

A9 = V

, A12 = VIH, A15 = VIH

ID

Others = X

A12-A20 Block Address

Others = X

A12-A20 Block Address

Others = X

IL

Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

X

X

Pass = XX01h

Retry = XX00h

Retry = XX01h

Pass = XX00h

Figure 20. Programmer Equipment Group Protect Flowchart

START

ADDRESS = GROUP ADDRESS

W = V

IH

n = 0

G, A9 = VID,

E = V

IL

Wait 4µs

W = V

IL

Wait 100µs

W = V

IH

E, G = VIH,

A0, A6 = VIL,

A1 = V

IH

E = V

IL

M29DW323DT, M29DW323DB

Wait 4µs

G = V

IL

Verify Protect Set-upEnd

Note: Block Protection Groups are shown in APPENDIX D., Tables 23 and 24.

Wait 60ns

Read DATA

DATA

=

01h

YES

A9 = V

IH

E, G = V

IH

PASS

NO

++n

= 25

A9 = V

E, G = V

FAIL

YES

IH

NO

IH

AI05574

45/51

M29DW323DT, M29DW323DB

Figure 21. Programmer Equipment Chip Unprotect Flowchart

START

PROTECT ALL GROUPS

n = 0

CURRENT GROUP = 0

Verify Unprotect Set-upEnd

00h

(1)

IH

ID

IL

IH

IH

IH

IL

IL

YESNO

=

A6, A12, A15 = V

E, G, A9 = V

Wait 4µs

W = V

Wait 10ms

W = V

E, G = V

ADDRESS = CURRENT GROUP ADDRESS

A0 = VIL, A1, A6 = V

E = V

Wait 4µs

G = V

Wait 60ns

Read DATA

DATA

INCREMENT

CURRENT GROUP

++n

NO

= 1000

YES

A9 = V

IH

E, G = V

IH

FAIL PASS

Note: Block Protection Groups are shown in APPENDIX D., Tables 23 and 24.

46/51

LAST

GROUP

A9 = V

E, G = V

YES

IH

NO

IH

AI05575

Figure 22. In-System Equipment Group Protect Flowchart

START

n = 0

RP = V

ID

WRITE 60h

ADDRESS = GROUP ADDRESS

A0 = VIL, A1 = VIH, A6 = V

WRITE 60h

ADDRESS = GROUP ADDRESS

A0 = VIL, A1 = VIH, A6 = V

Wait 100µs

WRITE 40h

ADDRESS = GROUP ADDRESS

A0 = VIL, A1 = VIH, A6 = V

IL

IL

IL

M29DW323DT, M29DW323DB

Verify Protect Set-upEnd

ADDRESS = GROUP ADDRESS

Note: 1. Block Protection Groups are shown in APPENDIX D., Tables 23 and 24.

2. RP can be either at V

or at V

when using the In-System Technique to protect the Extended Block.

IH

ID

Wait 4µs

READ DATA

A0 = VIL, A1 = VIH, A6 = V

DATA

NO

=

01h

YES

RP = V

IH

ISSUE READ/RESET

COMMAND

PASS

IL

++n

NO

= 25

YES

RP = V

IH

ISSUE READ/RESET

COMMAND

FAIL

AI05576

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M29DW323DT, M29DW323DB

Figure 23. In-System Equipment Chip Unprotect Flowchart

START

PROTECT ALL GROUPS

n = 0

CURRENT GROUP = 0

RP = V

ID

WRITE 60h

ANY ADDRESS WITH

A0 = VIL, A1 = VIH, A6 = V

WRITE 60h

ANY ADDRESS WITH

A0 = VIL, A1 = VIH, A6 = V

Wait 10ms

IH

IH

WRITE 40h

A0 = VIL, A1 = VIH, A6 = V

Wait 4µs

READ DATA

A0 = VIL, A1 = VIH, A6 = V

DATA

=

00h

Verify Unprotect Set-upEnd

++n

NO

= 1000

YES

RP = V

IH

ISSUE READ/RESET

COMMAND

FAIL

ADDRESS = CURRENT GROUP ADDRESS

ADDRESS = CURRENT GROUP ADDRESS

Note: Block Protection Groups are shown in APPENDIX D., Tables 23 and 24.

IH

INCREMENT

CURRENT GROUP

IH

YESNO

NO

LAST

GROUP

YES

RP = V

IH

ISSUE READ/RESET

COMMAND

PASS

AI05577

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M29DW323DT, M29DW323DB

REVISION HISTORY

Table 33. Document Revision History

Date Version Revision Details

20-Sep-2001 -01 First Issue (Target Specification)

26-Oct-2001 -02 Document expanded to full Product Preview

16-Jan-2002 -03 Corrections made in “Primary Algorithm-Specific Extended Query” Table in Appendix-B

Description of Ready/Busy signal clarified (and Figure 16. modified)

19-Apr-2002 -04

24-Apr-2002 -05

19-Jul-2002 -06

08-Apr-2003 6.1

07-May-2003 6.2

25-Jun-2003 7.0

18-Sep-2003 7.1

07-Oct-2003 7.2

07-Nov-2003 7.3

Clarified allowable commands during block erase
Clarified the mode the device returns to in the CFI Read Query command section
tPLYH (time to reset device) re-specified.

Values for addresses 23h and 25h corrected in CFI Query System Interface Information
table in Appendix B

When in Extended Block mode, the block at the boot block address can be used as OTP.
Data Toggle Flow chart corrected. Document promoted from “Product Preview” to
“Preliminary Data”.

Revision numbering modified: a minor revision will be indicated by incrementing the digit
after the dot, and a major revision, by incrementing the digit before the dot (revision version
06 equals 6.0).
Revision History moved to end of document.
TFBGA48, 6 x 8mm, 0.80mm pitch package added. Identification Current I

Table 14., DC Characteristics. Erase Suspend Latency time and Data Retention

parameters and notes added to Table 7., Program, Erase Times and Program, Erase

Endurance Cycles.
APPENDIX C., EXTENDED MEMORY BLOCK, added. Auto Select Command sued to

read the Extended Memory Block. Extended Memory Block Verify Code row added to
Ta bl e s 3 and 4, Bus Operations, BYTE = V
Address modified in Auto Select Command. Chip Erase Address modified in Table 8.,

Status Register Bits. V

22., Ordering Information Scheme.

Table 20., TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Package Mechanical

Data, and Figure 18., TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Bottom View
Package Outline, corrected.

Document promoted from Preliminary Data to full Datasheet status. Packing option added
to Table 22., Ordering Information Scheme.

Status of Ready/Busy signal for Erase Suspend Operation modified in Table 8., Status

Register Bits.

Figures 14 and 15, Toggle and Alternative Toggle Bits Mechanisms added.

Table 18., Toggle and Alternative Toggle Bits AC Characteristics, added.

Note 1 of Table 28., Device Geometry Definition, modified

Figures 14 and 15, Toggle and Alternative Toggle Bits Mechanisms modified and Notes 1
and 2 added.

Table 18., Toggle and Alternative Toggle Bits AC Characteristics modified.
Figure 8. renamed and flowchart modified; Note added.

Status of Ready/Busy signal for Program Error, Chip Erase and Block Erase modified in

Table 8., Status Register Bits.

pin connection to ground clarified. Note added to Table

SS

and Bus Operations, BYTE = VIH. Bank

IL

removed from

ID

49/51

M29DW323DT, M29DW323DB

Date Version Revision Details

minimum value updated in Table 12., Operating and AC Measurement Conditions.

V

CC

and I

V

PP

Architecture option updated in Table 22. Ordering Information Scheme.

19-Dec-2003 7.4

Block Protect/Unprotect code updated in APPENDIX B., Table 29.
Customer Lockable Extended Block mechanism modified in APPENDIX C., Extended
Memory Block.

APPENDIX D., Block Protection updated: Note 1 added in the In-System Technique

section and Note 2 added below Figure 22., In-System Equipment Group Protect
Flowchart.

23-Mar-2004 8.0 Introduction of the STATUS REGISTER chapter clarified.

12-July-2004 9.0 90ns speed class removed from datasheet.

12-Aug-2004 10.0 Section , DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE added.

27-Sep-2004 11.0 TFBGA63 package removed.

10-Dec-2004 12.0

14-Mar-2005 13.0

Status of Ready/Busy signal for Program Error, Chip Erase and Block Erase modified in

Table 8., Status Register Bits.

RB

Fast Program Commands restructured and updated.
Unlock Bypass Command updated.

27-Mar-2008 14.0 Applied Numonyx branding.

test conditions updated in Table 14., DC Characteristics.

PP

updated in Table 8., Status Register Bits.

50/51

M29DW323DT, M29DW323DB

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