Numonyx M25P40 Technical data

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4 Mbit, low voltage, serial Flash memory

Features

■ 4 Mbit of Flash memory

■ 2.3 V to 3.6 V single supply voltage

■ SPI bus compatible serial interface

■ 50 MHz clock rate (maximum)

■ Page Program (up to 256 bytes) in 1.5 ms

(typical)

■ Sector Erase (512 Kbit) in 1 s (typical)

■ Bulk Erase (4 Mbit) in 4.5 s (typical)

■ Deep Power-down mode 1 µA (typical)

■ Hardware Write Protection: protected area size

defined by three non-volatile bits (BP0, BP1 and BP2)

■ Electronic signatures

– JEDEC standard two-byte signature

(2013h)

– RES instruction, one-byte, signature (12h),

for backward compatibility

■ Packages

– ECOPACK® (RoHS compliant)

M25P40

with 50 MHz SPI bus interface

SO8 (MN)

150 mil width

VFQFPN8 (MP)

(MLP8)

December 2007 Rev 15 1/53

www.numonyx.com

Contents M25P40

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.4 Chip Select (S

2.5 Hold (HOLD

2.6 Write Protect (W

2.7 V

2.8 V

supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1 Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.2 Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.3 Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . . 12

4.4 Active Power, Standby Power and Deep Power-down modes . . . . . . . . . 12

4.5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.6 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.7 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.3 Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.4 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.4.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.4.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.4.3 BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2/53

M25P40 Contents

6.4.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.5 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.6 Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

6.7 Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . 27

6.8 Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

6.9 Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.10 Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.11 Deep Power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

6.12 Release from Deep Power-down and Read Electronic Signature (RES) . 33

7 Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

9 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

10 DC and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

11 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

12 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3/53

List of tables M25P40

List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. Protected area sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 3. Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 4. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 5. Read Identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 6. Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 7. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 8. Power-up timing and V

Table 9. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 10. Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 11. Data retention and endurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 12. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 13. DC characteristics (device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 14. DC characteristics (device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 15. Instruction times (device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 16. Instruction times (device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 17. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 18. Which AC characteristics to use? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 19. AC characteristics (25 MHz operation, device grade 3, V Table 20. AC characteristics (50 MHz operation, device grade 6, V Table 21. AC characteristics (40 MHz operation, device grade 6, V Table 22. SO8 narrow – 8 lead plastic Small Outline, 150 mils body width,

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 23. VFQFPN8 (MLP8) 8-lead Very thin Fine pitch Quad Flat Package No lead,

6 × 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 24. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 25. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

min = 2.7 V) . . . . . . . . . . . . . 42

min = 2.7 V) . . . . . . . . . . . . . 43

min = 2.3 V) . . . . . . . . . . . . . 44

4/53

M25P40 List of figures

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. SO and VFQFPN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. Bus Master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 5. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 7. Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 8. Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 9. Read Identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 21

Figure 10. Read Status Register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . 23

Figure 11. Write Status Register (WRSR) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 12. Read Data Bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 26

Figure 13. Read Data Bytes at Higher Speed (FAST_READ) instruction sequence

and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 14. Page Program (PP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 15. Sector Erase (SE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 16. Bulk Erase (BE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 17. Deep Power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 18. Release from Deep Power-down and Read Electronic Signature (RES) instruction

sequence and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 19. Release from Deep Power-down (RES) instruction sequence . . . . . . . . . . . . . . . . . . . . . . 34

Figure 20. Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 21. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 22. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 23. Write Protect setup and hold timing during WRSR when SRWD = 1 . . . . . . . . . . . . . . . . . 45

Figure 24. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 25. Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 26. SO8 narrow – 8 lead plastic Small Outline, 150 mils body width, package outline. . . . . . . 47

Figure 27. VFQFPN8 (MLP8) 8-lead Very thin Fine pitch Quad Flat Package No lead,

6 × 5 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5/53

Description M25P40

1 Description

The M25P40 is a 4 Mbit (512 K × 8) Serial Flash memory, with advanced write protection

mechanisms, accessed by a high speed SPI-compatible bus.

The memory can be programmed 1 to 256 bytes at a time, using the Page Program

instruction.

The memory is organized as 8 sectors, each containing 256 pages. Each page is 256 bytes

wide. Thus, the whole memory can be viewed as consisting of 2048 pages, or 524,288

bytes.

The whole memory can be erased using the Bulk Erase instruction, or a sector at a time,

using the Sector Erase instruction.

In order to meet environmental requirements, Numonyx offers the M25P40 in ECOPACK®

packages. ECOPACK® packages are Lead-free and RoHS compliant.

Figure 1. Logic diagram

HOLD

Table 1. Signal names

Signal name Function Direction

C Serial Clock Input

D Serial Data input Input

Q Serial Data output Output

S Chip Select Input

HOLD

Write Protect Input

Hold Input

Supply voltage

Ground

M25P40

AI04090

6/53

M25P40 Description

Figure 2. SO and VFQFPN connections

M25P40

1 2

3 4

1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally, to VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB.

2. See Section 11: Package mechanical for package dimensions, and how to identify pin-1.

8 7 6 5

AI04091B

HOLDQ C DV

7/53

Signal description M25P40

2 Signal description

2.1 Serial Data output (Q)

This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C).

2.2 Serial Data input (D)

This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C).

2.3 Serial Clock (C)

This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data output (Q) changes after the falling edge of Serial Clock (C).

2.4 Chip Select (S)

When this input signal is High, the device is deselected and Serial Data output (Q) is at high impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress, the device will be in the Standby Power mode (this is not the Deep Power-down mode). Driving Chip Select (S

After Power-up, a falling edge on Chip Select (S instruction.

) Low selects the device, placing it in the Active Power mode.

2.5 Hold (HOLD)

The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device.

During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data input (D) and Serial Clock (C) are Don’t Care.

To start the Hold condition, the device must be selected, with Chip Select (S

2.6 Write Protect (W)

The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP2, BP1 and BP0 bits of the Status Register).

) is required prior to the start of any

) driven Low.

8/53

M25P40 Signal description

2.7 VCC supply voltage

VCC is the supply voltage.

2.8 VSS ground

VSS is the reference for the VCC supply voltage.

9/53

SPI modes M25P40

3 SPI modes

These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes:

● CPOL=0, CPHA=0

● CPOL=1, CPHA=1

For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C).

The difference between the two modes, as shown in Figure 4, is the clock polarity when the bus master is in Stand-by mode and not transferring data:

● C remains at 0 for (CPOL=0, CPHA=0)

● C remains at 1 for (CPOL=1, CPHA=1)

Figure 3. Bus Master and memory devices on the SPI bus

SPI Interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

SPI Bus Master

CS3 CS2 CS1

1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.

SDO

SDI

SCK

Device

HOLD

CQD

RR R

SPI Memory

CQD

SPI Memory

Device

HOLD

CQD

SPI Memory

Device

HOLD

AI12836b

Figure 3 shows an example of three devices connected to an MCU, on an SPI bus. Only one

device is selected at a time, so only one device drives the Serial Data output (Q) line at a time, the other devices are high impedance. Resistors R (represented in Figure 3) ensure that the M25P40 is not selected if the Bus Master leaves the S

line in the high impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at the same time (for example, when the Bus Master is reset), the clock line (C) must be connected to an external pull-down resistor so that, when all inputs/outputs become high impedance, the S C do not become High at the same time, and so, that the t typical value of R is 100 kΩ, assuming that the time constant R*C

line is pulled High while the C line is pulled Low (thus ensuring that S and

requirement is met). The

SHCH

(Cp = parasitic

capacitance of the bus line) is shorter than the time during which the Bus Master leaves the SPI bus in high impedance.

10/53

M25P40 SPI modes

Example: Cp = 50 pF, that is R*Cp = 5 µs <=> the application must ensure that the Bus

Master never leaves the SPI bus in the high impedance state for a time period shorter than 5µs.

Figure 4. SPI modes supported

CPHA

CPOL

MSB

AI01438B

11/53

Operating features M25P40

4 Operating features

4.1 Page Programming

To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle (of duration t

To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory.

For optimized timings, it is recommended to use the Page Program (PP) instruction to program all consecutive targeted bytes in a single sequence versus using several Page Program (PP) sequences with each containing only a few bytes (see Page Program (PP),

Instruction times (device grade 6) and Table 16: Instruction times (device grade 3)).

4.2 Sector Erase and Bulk Erase

The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of duration t

The Erase instruction must be preceded by a Write Enable (WREN) instruction.

or tBE).

4.3 Polling during a Write, Program or Erase cycle

A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE or BE) can be achieved by not waiting for the worst case delay (t Write In Progress (WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is complete.

, tPP, tSE, or tBE). The

4.4 Active Power, Standby Power and Deep Power-down modes

When Chip Select (S) is Low, the device is selected, and in the Active Power mode.

When Chip Select (S mode until all internal cycles have completed (Program, Erase, Write Status Register). The device then goes in to the Standby Power mode. The device consumption drops to I

The Deep Power-down mode is entered when the specific instruction (the Deep Powerdown (DP) instruction) is executed. The device consumption drops further to I device remains in this mode until another specific instruction (the Release from Deep Power-down and Read Electronic Signature (RES) instruction) is executed.

All other instructions are ignored while the device is in the Deep Power-down mode. This can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent Write, Program or Erase instructions.

) is High, the device is deselected, but could remain in the Active Power

CC1

. The

CC2

12/53

M25P40 Operating features

4.5 Status Register

The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. For a detailed description of the Status Register bits, see Section 6.4: Read Status Register (RDSR).

4.6 Protection modes

The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P40 features the following data protection mechanisms:

● Power On Reset and an internal timer (t

changes while the power supply is outside the operating specification.

● Program, Erase and Write Status Register instructions are checked that they consist of

a number of clock pulses that is a multiple of eight, before they are accepted for execution.

● All instructions that modify data must be preceded by a Write Enable (WREN)

instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events:

–Power-up – Write Disable (WRDI) instruction completion – Write Status Register (WRSR) instruction completion – Page Program (PP) instruction completion – Sector Erase (SE) instruction completion – Bulk Erase (BE) instruction completion

● The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as

read-only. This is the Software Protected Mode (SPM).

● The Write Protect (W) signal allows the Block Protect (BP2, BP1, BP0) bits and Status

● In addition to the low power consumption feature, the Deep Power-down mode offers

extra software protection from inadvertent Write, Program and Erase instructions, as all instructions are ignored except one particular instruction (the Release from Deep Power-down instruction).

) can provide protection against inadvertent

PUW

13/53

Operating features M25P40

Table 2. Protected area sizes

Status Register

content

BP2

BP1

BP0

bit

0 0 0 none All sectors

0 0 1 Upper eighth (Sector 7)

0 1 0 Upper quarter (two sectors: 6 and 7) Lower three-quarters (six sectors: 0 to 5)

0 1 1 Upper half (four sectors: 4 to 7) Lower half (four sectors: 0 to 3)

1 0 0 All sectors (eight sectors: 0 to 7) none

1 0 1 All sectors (eight sectors: 0 to 7) none

1 1 0 All sectors (eight sectors: 0 to 7) none

1 1 1 All sectors (eight sectors: 0 to 7) none

1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are

4.7 Hold condition

The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. However, taking this signal Low does not terminate any Write Status Register, Program or Erase cycle that is currently in progress.

Memory content

Protected area Unprotected area

(1)

(eight sectors: 0 to 7)

Lower seven-eighths (seven sectors: 0 to

To enter the Hold condition, the device must be selected, with Chip Select (S

The Hold condition starts on the falling edge of the Hold (HOLD

) signal, provided that this

) Low.

coincides with Serial Clock (C) being Low (as shown in Figure 5).

The Hold condition ends on the rising edge of the Hold (HOLD

) signal, provided that this coincides with Serial Clock (C) being Low.

If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes Low. (This is shown in Figure 5).

During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data input (D) and Serial Clock (C) are Don’t Care.

Normally, the device is kept selected, with Chip Select (S

) driven Low, for the whole duration of the Hold condition. This is to ensure that the state of the internal logic remains unchanged from the moment of entering the Hold condition.

If Chip Select (S

) goes High while the device is in the Hold condition, this has the effect of resetting the internal logic of the device. To restart communication with the device, it is necessary to drive Hold (HOLD

) High, and then to drive Chip Select (S) Low. This prevents

the device from going back to the Hold condition.

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M25P40 Operating features

Figure 5. Hold condition activation

HOLD

Hold

Condition

(standard use)

Hold

Condition

(non-standard use)

AI02029D

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Memory organization M25P40

5 Memory organization

The memory is organized as:

● 524,288 bytes (8 bits each)

● 8 sectors (512 Kbits, 65536 bytes each)

● 2048 pages (256 bytes each).

Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or Bulk Erasable (bits are erased from 0 to 1) but not Page Erasable.

Table 3. Memory organization

Sector Address range

7 70000h 7FFFFh

6 60000h 6FFFFh

5 50000h 5FFFFh

4 40000h 4FFFFh

3 30000h 3FFFFh

2 20000h 2FFFFh

1 10000h 1FFFFh

0 00000h 0FFFFh

16/53

M25P40 Memory organization

Figure 6. Block diagram

HOLD

Control Logic

Address Register

and Counter

Y Decoder

High Voltage

Generator

I/O Shift Register

256 Byte

Data Buffer

Status

7FFFFh

Size of the

read-only

memory area

00000h

000FFh

256 Bytes (Page Size)

X Decoder

AI04986

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Instructions M25P40

6 Instructions

All instructions, addresses and data are shifted in and out of the device, most significant bit first.

Serial Data input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select (S

) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data input (D), each bit being latched on the rising edges of Serial Clock (C).

The instruction set is listed in Ta bl e 4 .

Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. Chip Select (S shifted in.

In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read), Read Identification (RDID), Read Status Register (RDSR) or Release from Deep Powerdown, and Read Electronic Signature (RES) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (S data-out sequence is being shifted out.

) must be driven High after the last bit of the instruction sequence has been

) can be driven High after any bit of the

In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP) instruction, Chip Select (S instruction is rejected, and is not executed. That is, Chip Select (S the number of clock pulses after Chip Select (S eight.

All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected.

) must be driven High exactly at a byte boundary, otherwise the

) must driven High when

) being driven Low is an exact multiple of

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M25P40 Instructions

Table 4. Instruction set

Instruction Description

One-byte instruction

code

Address

bytes

Dummy

bytes

Data

bytes

WREN Write Enable 0000 0110 06h 0 0 0

WRDI Write Disable 0000 0100 04h 0 0 0

(1)

RDID

Read Identification 1001 1111 9Fh 0 0 1 to 3

RDSR Read Status Register 0000 0101 05h 0 0 1 to ∞

WRSR Write Status Register 0000 0001 01h 0 0 1

READ Read Data Bytes 0000 0011 03h 3 0 1 to ∞

FAST_READ

Read Data Bytes at Higher Speed

0000 1011 0Bh 3 1 1 to ∞

PP Page Program 0000 0010 02h 3 0 1 to 256

SE Sector Erase 1101 1000 D8h 3 0 0

BE Bulk Erase 1100 0111 C7h 0 0 0

DP Deep Power-down 1011 1001 B9h 0 0 0

Release from Deep Powerdown, and Read Electronic

RES

Signature

1010 1011 ABh

Release from Deep Powerdown

1. The Read Identification (RDID) instruction is available only in products with Process Technology code X

(see Application Note AN1995).

0 3 1 to ∞

0 0 0

6.1 Write Enable (WREN)

The Write Enable (WREN) instruction (Figure 7) sets the Write Enable Latch (WEL) bit.

The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction.

The Write Enable (WREN) instruction is entered by driving Chip Select (S instruction code, and then driving Chip Select (S

Figure 7. Write Enable (WREN) instruction sequence

21 34567

Instruction

High Impedance

) Low, sending the

) High.

AI02281E

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Instructions M25P40

6.2 Write Disable (WRDI)

The Write Disable (WRDI) instruction (Figure 8) resets the Write Enable Latch (WEL) bit.

The Write Disable (WRDI) instruction is entered by driving Chip Select (S instruction code, and then driving Chip Select (S

) High.

The Write Enable Latch (WEL) bit is reset under the following conditions:

● Power-up

● Write Disable (WRDI) instruction completion

● Write Status Register (WRSR) instruction completion

● Page Program (PP) instruction completion

● Sector Erase (SE) instruction completion

● Bulk Erase (BE) instruction completion

Figure 8. Write Disable (WRDI) instruction sequence

21 34567

Instruction

High Impedance

AI03750D

) Low, sending the

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M25P40 Instructions

6.3 Read Identification (RDID)

The Read Identification (RDID) instruction is available in products with Process Technology code X only.

The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (20h), and the memory capacity of the device in the second byte (13h).

Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress.

The Read Identification (RDID) instruction should not be issued while the device is in Deep Power-down mode.

The device is first selected by driving Chip Select (S

) Low. Then, the 8-bit instruction code for the instruction is shifted in. This is followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data output (Q), each bit being shifted out during the falling edge of Serial Clock (C).

The instruction sequence is shown in Figure 9.

The Read Identification (RDID) instruction is terminated by driving Chip Select (S

) High at

any time during data output.

When Chip Select (S

) is driven High, the device is put in the Stand-by Power mode. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.

Table 5. Read Identification (RDID) data-out sequence

Device identification

Manufacturer identification

Memory type Memory capacity

20h 20h 13h

Figure 9. Read Identification (RDID) instruction sequence and data-out sequence

21 3456789101112131415

Instruction

16 17 18 28 29 30 31

High Impedance

Manufacturer Identification

MSB

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Device Identification

15 1413 3210

MSB

AI06809b

Instructions M25P40

6.4 Read Status Register (RDSR)

The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure 10.

Table 6. Status Register format

b7 b0

SRWD 0 0 BP2 BP1 BP0 WEL WIP

Status Register Write Protect

Block Protect bits

Write Enable Latch bit

Write In Progress bit

The status and control bits of the Status Register are as follows:

6.4.1 WIP bit

The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress.

6.4.2 WEL bit

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase instruction is accepted.

6.4.3 BP2, BP1, BP0 bits

The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP2, BP1, BP0) bits is set to 1, the relevant memory area (as defined in Ta b le 2 ) becomes protected against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect (BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect (BP2, BP1, BP0) bits are 0.

6.4.4 SRWD bit

The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W

) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected mode (when the Status Register Write Disable (SRWD) bit is set to 1, and Write Protect (W non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution.

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) is driven Low). In this mode, the

M25P40 Instructions

Figure 10. Read Status Register (RDSR) instruction sequence and data-out

sequence

21 3456789101112131415

Instruction

High Impedance

Status Register Out

7 6543210

MSB

Status Register Out

7 6543210

MSB

AI02031E

23/53

Instructions M25P40

6.5 Write Status Register (WRSR)

The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL).

The Write Status Register (WRSR) instruction is entered by driving Chip Select (S

) Low,

followed by the instruction code and the data byte on Serial Data input (D).

The instruction sequence is shown in Figure 11.

The Write Status Register (WRSR) instruction has no effect on b6, b5, b1 and b0 of the Status Register. b6 and b5 are always read as 0.

Chip Select (S

) must be driven High after the eighth bit of the data byte has been latched in. If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (S

) is driven High, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset.

The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Ta b le 2 . The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the Write Protect (W (W

) signal allow the device to be put in the Hardware Protected Mode (HPM). The Write

) signal. The Status Register Write Disable (SRWD) bit and Write Protect

Status Register (WRSR) instruction is not executed once the Hardware Protected Mode (HPM) is entered.

Figure 11. Write Status Register (WRSR) instruction sequence

21 3456789101112131415

Instruction Status

High Impedance

24/53

765432 0

MSB

AI02282D

M25P40 Instructions

Table 7. Protection modes

SRWD

signal

1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in

Table 2.

bit

Mode

Software

Protected

(SPM)

Hardware Protected

(HPM)

Write Protection of the

Status Register

Status Register is Writable (if the WREN instruction has set the WEL bit)

The values in the SRWD, BP2, BP1 and BP0 bits can be changed

Status Register is Hardware write protected

The values in the SRWD, BP2, BP1 and BP0 bits cannot be changed

Protected area

Protected against Page Program, Sector Erase and Bulk Erase

Memory content

(1)

Unprotected area

Ready to accept Page Program and Sector Erase instructions

(1)

The protection features of the device are summarized in Tab le 7 .

When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless of the whether Write Protect (W

) is driven High or Low.

When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two cases need to be considered, depending on the state of Write Protect (W

● If Write Protect (W) is driven High, it is possible to write to the Status Register provided

that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction.

● If Write Protect (W) is driven Low, it is not possible to write to the Status Register even

if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status Register, are also hardware protected against data modification.

Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered:

● by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W)

Low

● or by driving Write Protect (W) Low after setting the Status Register Write Disable

(SRWD) bit.

The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write Protect (W

If Write Protect (W

) High.

) is permanently tied High, the Hardware Protected Mode (HPM) can never be activated, and only the Software Protected Mode (SPM), using the Block Protect (BP2, BP1, BP0) bits of the Status Register, can be used.

25/53

Instructions M25P40

6.6 Read Data Bytes (READ)

The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on Serial Data output (Q), each bit being shifted out, at a maximum frequency f

The instruction sequence is shown in Figure 12.

The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely.

, during the falling edge of Serial Clock (C).

The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S Select (S

) can be driven High at any time during data output. Any Read Data Bytes (READ)

) High. Chip

instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.

Figure 12. Read Data Bytes (READ) instruction sequence and data-out sequence

21 345678910 2829303132333435

Instruction 24-Bit Address

MSB

High Impedance

1. Address bits A23 to A19 are Don’t Care.

2221 3210

76543 1 7

MSB

36 37 38

Data Out 1

Data Out 2

AI03748D

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M25P40 Instructions

6.7 Read Data Bytes at Higher Speed (FAST_READ)

The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on Serial Data output (Q), each bit being shifted out, at a maximum frequency f

The instruction sequence is shown in Figure 13.

The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely.

The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving Chip Select (S

) High. Chip Select (S) can be driven High at any time during data output. Any Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.

Figure 13. Read Data Bytes at Higher Speed (FAST_READ) instruction sequence

and data-out sequence

, during the falling edge of Serial Clock (C).

21 345678910 28293031

Instruction 24 BIT ADDRESS

High Impedance

32 33 34 36 37 38 39 40 41 42 43 44 45 46

765432 0

Dummy Byte

2221 3210

DATA OUT 1

765432 0

MSB

DATA OUT 2

7 6543210

MSB MSB

1. Address bits A23 to A19 are Don’t Care.

AI04006

27/53

Instructions M25P40

6.8 Page Program (PP)

The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).

The Page Program (PP) instruction is entered by driving Chip Select (S the instruction code, three address bytes and at least one data byte on Serial Data input (D). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S must be driven Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 14.

If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 Data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page.

(device grade 6) and Table 16: Instruction times (device grade 3)).

Chip Select (S latched in, otherwise the Page Program (PP) instruction is not executed.

As soon as Chip Select (S duration is t may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.

) must be driven High after the eighth bit of the last data byte has been

) is driven High, the self-timed Page Program cycle (whose

) is initiated. While the Page Program cycle is in progress, the Status Register

) Low, followed by

)

A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP2, BP1, BP0) bits (see Ta bl e 3 and Ta bl e 2) is not executed.

28/53

M25P40 Instructions

Figure 14. Page Program (PP) instruction sequence

21 345678910 2829303132333435

Instruction 24-Bit Address

4241 43 44 45 46 47 48 49 50 52 53 54 5540

Data Byte 2

765432 0

MSB MSB MSB

1. Address bits A23 to A19 are Don’t Care.

2221 3210

MSB

Data Byte 3 Data Byte 256

765432 0

MSB

2072

765432 0

Data Byte 1

2075

2074

2073

36 37 38

2077

2076

2078

2079

AI04082B

29/53

Instructions M25P40

6.9 Sector Erase (SE)

The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).

The Sector Erase (SE) instruction is entered by driving Chip Select (S

) Low, followed by the instruction code, and three address bytes on Serial Data input (D). Any address inside the Sector (see Ta bl e 3 ) is a valid address for the Sector Erase (SE) instruction. Chip Select (S must be driven Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 15.

Chip Select (S

) must be driven High after the eighth bit of the last address byte has been latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip Select (S

) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.

A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect (BP2, BP1, BP0) bits (see Ta bl e 3 and Ta bl e 2) is not executed.

Figure 15. Sector Erase (SE) instruction sequence

21 3456789 293031

)

Instruction

1. Address bits A23 to A19 are Don’t Care.

30/53

24 Bit Address

23 22 2 0

MSB

AI03751D

M25P40 Instructions

6.10 Bulk Erase (BE)

The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).

The Bulk Erase (BE) instruction is entered by driving Chip Select (S instruction code on Serial Data input (D). Chip Select (S

) must be driven Low for the entire

) Low, followed by the

duration of the sequence.

The instruction sequence is shown in Figure 16.

Chip Select (S

) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S is driven High, the self-timed Bulk Erase cycle (whose duration is t

) is initiated. While the

Bulk Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.

The Bulk Erase (BE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits are

0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected.

Figure 16. Bulk Erase (BE) instruction sequence

21 345670

Instruction

)

AI03752D

31/53

Instructions M25P40

6.11 Deep Power-down (DP)

Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all Write, Program and Erase instructions.

Driving Chip Select (S

) High deselects the device, and puts the device in the Standby Power mode (if there is no internal cycle currently in progress). But this mode is not the Deep Power-down mode. The Deep Power-down mode can only be entered by executing the Deep Power-down (DP) instruction, subsequently reducing the standby current (from I I

, as specified in Ta bl e 1 3 ).

CC2

CC1

Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep Power-down and Read Electronic Signature (RES) instruction. This releases the device from this mode. The Release from Deep Power-down and Read Electronic Signature (RES) instruction and the Read Identification (RDID) instruction also allow the Electronic Signature of the device to be output on Serial Data output (Q).

The Deep Power-down mode automatically stops at Power-down, and the device always Powers-up in the Standby Power mode.

The Deep Power-down (DP) instruction is entered by driving Chip Select (S by the instruction code on Serial Data input (D). Chip Select (S

) must be driven Low for the

) Low, followed

entire duration of the sequence.

The instruction sequence is shown in Figure 17.

Chip Select (S

) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as Chip Select (S to I

and the Deep Power-down mode is entered.

CC2

) is driven High, it requires a delay of tDP before the supply current is reduced

Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.

Figure 17. Deep Power-down (DP) instruction sequence

21 345670

Instruction

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Stand-by Mode

Deep Power-down Mode

AI03753D

M25P40 Instructions

6.12 Release from Deep Power-down and Read Electronic Signature (RES)

Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep Power-down and Read Electronic Signature (RES) instruction. Executing this instruction takes the device out of the Deep Power-down mode.

The instruction can also be used to read, on Serial Data output (Q), the 8-bit Electronic Signature, whose value for the M25P40 is 12h.

Except while an Erase, Program or Write Status Register cycle is in progress, the Release from Deep Power-down and Read Electronic Signature (RES) instruction always provides access to the 8-bit Electronic Signature of the device, and can be applied even if the Deep Power-down mode has not been entered.

Any Release from Deep Power-down and Read Electronic Signature (RES) instruction while an Erase, Program or Write Status Register cycle is in progress, is not decoded, and has no effect on the cycle that is in progress.

The device is first selected by driving Chip Select (S

) Low. The instruction code is followed by 3 dummy bytes, each bit being latched-in on Serial Data input (D) during the rising edge of Serial Clock (C). Then, the 8-bit Electronic Signature, stored in the memory, is shifted out on Serial Data output (Q), each bit being shifted out during the falling edge of Serial Clock (C).

The instruction sequence is shown in Figure 18.

The Release from Deep Power-down and Read Electronic Signature (RES) instruction is terminated by driving Chip Select (S least once. Sending additional clock cycles on Serial Clock (C), while Chip Select (S

) High after the Electronic Signature has been read at

) is

driven Low, cause the Electronic Signature to be output repeatedly.

When Chip Select (S

) is driven High, the device is put in the Standby Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Standby Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Standby Power mode is delayed by t must remain High for at least t

(max), as specified in Ta bl e 1 9 . Once in the Standby

RES2

, and Chip Select (S)

RES2

Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.

Driving Chip Select (S

) High after the 8-bit instruction byte has been received by the device, but before the whole of the 8-bit Electronic Signature has been transmitted for the first time (as shown in Figure 19), still ensures that the device is put into Standby Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Standby Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Standby Power mode is delayed by t must remain High for at least t

(max), as specified in Ta bl e 1 9 . Once in the Standby

RES1

, and Chip Select (S)

RES1

Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.

33/53

Instructions M25P40

Figure 18. Release from Deep Power-down and Read Electronic Signature (RES) instruction

sequence and data-out sequence

21 345678910 2829303132333435

36 37 38

Instruction 3 Dummy Bytes

High Impedance

2221 3210

MSB

Electronic Signature Out

765432 0

MSB

Deep Power-down Mode

1. The value of the 8-bit Electronic Signature, for the M25P40, is 12h.

Figure 19. Release from Deep Power-down (RES) instruction sequence

21 345670

Instruction

RES1

RES2

Stand-by Mode

AI04047C

High Impedance

34/53

Deep Power-down Mode

Stand-by Mode

AI04078B

M25P40 Power-up and Power-down

7 Power-up and Power-down

At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied on V

● V

●

(min) at Power-up, and then for a further delay of t

VSS at Power-down

A safe configuration is provided in Section 3: SPI modes.

To avoid data corruption and inadvertent write operations during power-up, a Power On Reset (POR) circuit is included. The logic inside the device is held reset while V than the Power On Reset (POR) threshold voltage, V the device does not respond to any instruction.

Moreover, the device ignores all Write Enable (WREN), Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instructions until a time delay of t

has elapsed after the moment that VCC rises above the VWI threshold. However, the

PUW

correct operation of the device is not guaranteed if, by this time, V No Write Status Register, Program or Erase instructions should be sent until the later of:

● t

after VCC passed the VWI threshold

PUW

after VCC passed the VCC(min) level

VSL

These values are specified in Ta bl e 9 .

) until VCC reaches the correct value:

VSL

– all operations are disabled, and

is less

is still below VCC(min).

If the delay, t selected for READ instructions even if the t

, has elapsed, after VCC has risen above VCC(min), the device can be

VSL

delay is not yet fully elapsed.

PUW

At Power-up, the device is in the following state:

● The device is in the Standby Power mode (not the Deep Power-down mode).

● The Write Enable Latch (WEL) bit is reset.

● The Write In Progress (WIP) bit is reset.

Normal precautions must be taken for supply rail decoupling, to stabilize the V Each device in a system should have the V

rail decoupled by a suitable capacitor close to

supply.

the package pins. (Generally, this capacitor is of the order of 100 nF).

At Power-down, when V (POR) threshold voltage, V

drops from the operating voltage, to below the Power On Reset

, all operations are disabled and the device does not respond

to any instruction. (The designer needs to be aware that if a Power-down occurs while a Write, Program or Erase cycle is in progress, some data corruption can result.)

35/53

Power-up and Power-down M25P40

Figure 20. Power-up timing

VCC(max)

Program, Erase and Write Commands are Rejected by the Device

Chip Selection Not Allowed

VCC(min)

Reset State

of the

Device

Table 8. Power-up timing and V

threshold

tVSL

tPUW

Read Access allowed Device fully

accessible

time

AI04009C

Symbol Parameter Min. Max. Unit

(1)

VSL

PUW

1. These parameters are characterized only.

VCC(min) to S low 10 µs

(1)

Time delay to Write instruction 1 10 ms

Write Inhibit voltage (device grade 6) 1 2 V

(1)

Write Inhibit voltage (device grade 3) 1 2.2 V

36/53

M25P40 Initial delivery state

8 Initial delivery state

The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0).

9 Maximum rating

Stressing the device above the rating listed in the Absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the Numonyx SURE Program and other relevant quality documents.

Table 9. Absolute maximum ratings

Symbol Parameter Min. Max. Unit

STG

LEAD

ESD

1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the Numonyx

ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.

2. JEDEC Std JESD22-A114A (C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω).

Storage temperature –65 150 °C

Lead temperature during soldering see

Input and output voltage (with respect to Ground) –0.6

(1)

0.6

Supply voltage –0.6 4.0 V

Electrostatic Discharge voltage (Human Body model)

(2)

–2000 2000 V

°C

37/53

DC and ac parameters M25P40

10 DC and ac parameters

This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristic tables that follow are derived from tests performed under the Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.

Table 10. Operating conditions

Symbol Parameter Min. Max. Unit

Supply voltage

2.3 3.6 V

Ambient operating temperature (device grade 6) –40 85

2.7 3.6 V

Ambient operating temperature (device grade 3) –40 125

Table 11. Data retention and endurance

Parameter Condition Min. Max. Unit

Erase/Program

cycles

Device grade 6 100,000

cycles per sector

Device grade 3 10,000

Data Retention at 55°C 20 years

Table 12. Capacitance

(1)

Symbol Parameter Test condition Min. Max. Unit

OUT

1. Sampled only, not 100% tested, at T

Output capacitance (Q) V

= 0 V 8 pF

OUT

Input capacitance (other pins) VIN = 0 V 6 pF

=25 °C and a frequency of 25 MHz.

°C

38/53

M25P40 DC and ac parameters

Table 13. DC characteristics (device grade 6)

Symbol Parameter

Input leakage current ± 2 µA

Output leakage current ± 2 µA

Standby current S = VCC, V

CC1

Deep Power-down current S = VCC, V

CC2

Operating current (READ)

CC3

Operating current (PP) S = V

CC4

Operating current (WRSR) S = V

CC5

Operating current (SE) S = V

CC6

Operating current (BE) S = V

CC7

Input low voltage –0.5 0.3V

Input high voltage 0.7V

Output low voltage IOL = 1.6 mA 0.4 V

Output high voltage IOH = –100 µA VCC–0.2 V

Test condition (in addition to

those in Tabl e 1 0 )

= VSS or V

C = 0.1V

= VSS or V

/ 0.9.VCC at

40 MHz and 50 MHz, Q = open

C = 0.1V

/ 0.9.VCC at

25 MHz, Q = open

Min. Max. Unit

50 µA

10 µA

8mA

4mA

15 mA

CCVCC

+0.4 V

39/53

DC and ac parameters M25P40

Table 14. DC characteristics (device grade 3)

Symbol Parameter

Input leakage current ± 2 µA

Output leakage current ± 2 µA

Standby current S = VCC, V

CC1

Deep Power-down current S = VCC, V

CC2

Test condition (in addition to

those in Table 10)

C = 0.1V

/ 0.9.VCC at 25 MHz,

Q = open

Operating current (READ)

CC3

C = 0.1V

/ 0.9.VCC at 20 MHz,

Q = open

1. This is preliminary data.

Table 15. Instruction times (device grade 6)

Operating current (PP) S = V

CC4

Operating current (WRSR) S = V

CC5

Operating current (SE) S = V

CC6

Operating current (BE) S = V

CC7

Input low voltage – 0.5 0.3V

Input high voltage 0.7V

Output low voltage IOL = 1.6 mA 0.4 V

Output high voltage IOH = –100 µA VCC–0.2 V

= VSS or V

Min

(1)

Max

CCVCC

(1)

Unit

100 µA

50 µA

8mA

4mA

15 mA

+0.4 V

Test conditions specified in Tabl e 1 0 and Ta b l e 17

Symbol Alt. Parameter Min. Typ. Max. Unit

Write Status Register cycle time 5 15 ms

Page Program cycle time (256 bytes) 1.4

(1)

1. When using the Page Program (PP) instruction to program consecutive bytes, optimized timings are

obtained with one sequence including all the bytes versus several sequences of only a few bytes. (1 ≤ n ≤

256)

Page Program cycle time (n bytes)

Sector Erase cycle time 1 3 s

Bulk Erase cycle time 4.5 10 s

0.4+

n*1/256

5ms

40/53

M25P40 DC and ac parameters

Table 16. Instruction times (device grade 3)

Test conditions specified in Tabl e 1 0 and Ta b l e 1 7

Symbol Alt. Parameter Min. Typ.

Write Status Register cycle time 8 15 ms

(1) (2)

Max.

(2)

Page Program cycle time (256 bytes) 1.5

(3)

1. At 85 °C

2. Preliminary data.

3. When using the Page Program (PP) instruction to program consecutive bytes, optimized timings are

obtained with one sequence including all the bytes versus several sequences of only a few bytes. (1 ≤ n ≤

256)

Table 17. AC measurement conditions

Page Program cycle time (n bytes)

Sector Erase cycle time 1 3 s

Bulk Erase cycle time 4.5 10 s

0.4+

n*1.1/256

5ms

Symbol Parameter Min. Max. Unit

Load capacitance 30 pF

Input rise and fall times 5 ns

Input pulse voltages 0.2VCC to 0.8V

Input timing reference voltages 0.3V

Output timing reference voltages V

to 0.7V

/ 2 V

Unit

1. Output Hi-Z is defined as the point where data out is no longer driven.

Figure 21. AC measurement I/O waveform

Input Levels

0.8V

0.2V

Table 18. Which AC characteristics to use?

Device grade VCC = 2.3 V to 3.6 V VCC = 2.7 V to 3.6 V

Device grade 3 N/A

(1)

Device grade 6 AC characteristics at 40 MHz (Tab le 21 ) AC characteristics at 50 MHz (Ta bl e 2 0 )

1. Not applicable.

Input and Output

Timing Reference Levels

0.7V

0.5V

0.3V

AI07455

AC characteristics at 25 MHz (Tab l e 1 9)

41/53

DC and ac parameters M25P40

Table 19. AC characteristics (25 MHz operation, device grade 3, VCC min = 2.7 V)

Test conditions specified in Ta b l e 10 and Ta b l e 17

Symbol Alt. Parameter Min. Typ. Max. Unit

Clock frequency for the following

(1)

CLCH

CHCL

SLCHtCSS

CHSL

DVCHtDSU

CHDX

CHSH

SHCH

SHSL

SHQZ

CLQV

CLQX

HLCH

CHHH

HHCH

CHHL

HHQX

HLQZ

WHSL

SHWL

(2)

RES1

RES2

1. tCH + tCL must be greater than or equal to 1/ f

2. Value guaranteed by characterization, not 100% tested in production.

3. Expressed as a slew-rate.

4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.

5. It is 30 µs in devices produced with the “X” process technology (grade 3 devices are only produced using

the “X” process technology). Details of how to find the process letter on the device marking are given in the Application note AN1995.

instructions: FAST_READ, PP, SE, BE, DP,

D.C. 2 5 MHz

RES, WREN, WRDI, RDSR, WRSR

Clock frequency for READ instructions D.C. 20 MHz

Clock High time 18 ns

CLH

Clock Low time 18 ns

CLL

(2)

Clock Rise time

Clock Fall time

(3)

(peak to peak)

(3)

(peak to peak) 0.1 V/ns

0.1 V/ns

S Active Setup time (relative to C) 10 ns

S Not Active Hold time (relative to C) 10 ns

Data In Setup time 5 ns

Data In Hold time 5 ns

S Active Hold time (relative to C) 10 ns

S Not Active Setup time (relative to C) 10 ns

S Deselect time 100 ns

CSH

(2)

Output Disable time 15 ns

DIS

tVClock Low to Output Valid 15 ns

Output Hold time 0 ns

HOLD Setup time (relative to C) 10 ns

HOLD Hold time (relative to C) 10 ns

HOLD Setup time (relative to C) 10 ns

HOLD Hold time (relative to C) 10 ns

(2)

HOLD to Output Low-Z 15 ns

(2)

HOLD to Output High-Z 20 ns

(4)

Write Protect Setup time 20 ns

Write Protect Hold time 100 ns

S High to Deep Power-down mode 3 μs

(2)

S High to Standby Power mode without Electronic Signature Read

S High to Standby Power mode with Electronic Signature Read

3 or 30

1.8 or 30

(5)

μs

42/53

M25P40 DC and ac parameters

Table 20. AC characteristics (50 MHz operation, device grade 6, VCC min = 2.7 V)

50 MHz available only in products with Process Technology code X

Test conditions specified in Ta b l e 10 and Ta b l e 17

Symbol Alt. Parameter Min. Typ. Max. Unit

Clock frequency for the following

instructions: FAST_READ, PP, SE, BE, DP,

D.C. 50 MHz

RES, WREN, RDID, WRDI, RDSR, WRSR

CLCH

CHCL

SLCH

CHSL

DVCH

CHDX

CHSH

SHCH

SHSL

SHQZ

CLQV

CLQX

HLCH

CHHH

HHCH

CHHL

HHQX

HLQZ

WHSL

SHWL

RES1

RES2

(2)

(3)

CLH

CSS

DSU

CSH

(3)

(5)

Clock frequency for READ instructions D.C. 25 MHz

Clock High time 9 ns

Clock Low time 9 ns

CLL

Clock Rise time

Clock Fall time

(4)

(peak to peak)

(4)

(peak to peak) 0.1 V/ns

0.1 V/ns

S Active Setup time (relative to C) 5 ns

S Not Active Hold time (relative to C) 5 ns

Data In Setup time 2 ns

Data In Hold time 5 ns

S Active Hold time (relative to C) 5 ns

S Not Active Setup time (relative to C) 5 ns

S Deselect time 100 ns

Output Disable time 8 ns

DIS

Clock Low to Output Valid 8 ns

Output Hold time 0 ns

HOLD Setup time (relative to C) 5 ns

HOLD Hold time (relative to C) 5 ns

HOLD Setup time (relative to C) 5 ns

HOLD Hold time (relative to C) 5 ns

HOLD to Output Low-Z 8 ns

HOLD to Output High-Z 8 ns

Write Protect Setup time 20 ns

Write Protect Hold time 100 ns

S High to Deep Power-down mode 3 µs

S High to Standby Power mode without Electronic Signature Read

S High to Standby Power mode with Electronic Signature Read

(1)

30 µs

1. Details of how to find the date of marking are given in Application Note, AN1995.

2. tCH + tCL must be greater than or equal to 1/ f

3. Value guaranteed by characterization, not 100% tested in production.

4. Expressed as a slew-rate.

5. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.

43/53

DC and ac parameters M25P40

Table 21. AC characteristics (40 MHz operation, device grade 6, VCC min = 2.3 V)

Extended VCC range available only in products with Process Technology code X

Test conditions specified in Ta b l e 10 and Ta b l e 17

Symbol Alt. Parameter Min. Typ. Max. Unit

Clock frequency for the following

instructions: FAST_READ, PP, SE, BE, DP,

D.C. 40 MHz

RES, WREN, RDID, WRDI, RDSR, WRSR

(2)

CLCH

CHCL

SLCH

CHSL

DVCH

CHDX

CHSH

SHCH

SHSL

SHQZ

CLQV

CLQX

HLCH

CHHH

HHCH

CHHL

HHQX

HLQZ

WHSL

SHWL

(3)

RES1

RES2

1. Details of how to find the date of marking are given in Application Note, AN1995.

2. tCH + tCL must be greater than or equal to 1/ f

3. Value guaranteed by characterization, not 100% tested in production.

4. Expressed as a slew-rate.

5. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.

(3)

(5)

(3)

CLH

CSS

DSU

CSH

Clock frequency for READ instructions D.C. 25 MHz

Clock High time 11 ns

Clock Low time 11 ns

CLL

Clock Rise time

Clock Fall time

(4)

(peak to peak)

(4)

(peak to peak) 0.1 V/ns

0.1 V/ns

S Active Setup time (relative to C) 5 ns

S Not Active Hold time (relative to C) 5 ns

Data In Setup time 2 ns

Data In Hold time 5 ns

S Active Hold time (relative to C) 5 ns

S Not Active Setup time (relative to C) 5 ns

S Deselect time 100 ns

Output Disable time 8 ns

DIS

Clock Low to Output Valid 8 ns

Output Hold time 0 ns

HOLD Setup time (relative to C) 5 ns

HOLD Hold time (relative to C) 5 ns

HOLD Setup time (relative to C) 5 ns

HOLD Hold time (relative to C) 5 ns

HOLD to Output Low-Z 8 ns

HOLD to Output High-Z 8 ns

Write Protect Setup time 20 ns

Write Protect Hold time 100 ns

S High to Deep Power-down mode 3 µs

S High to Standby Power mode without Electronic Signature Read

S High to Standby Power mode with Electronic Signature Read

(1)

30 µs

44/53

M25P40 DC and ac parameters

Figure 22. Serial input timing

tSHSL

tSLCH

tDVCH

tCHSHtCHSL

tSHCH

tCHCL

tCHDX

MSB IN

High Impedance

tCLCH

LSB IN

Figure 23. Write Protect setup and hold timing during WRSR when SRWD = 1

tWHSL

High Impedance

tSHWL

AI07439

45/53

DC and ac parameters M25P40

Figure 24. Hold timing

tHLCH

tCHHL

tCHHH

HOLD

tHHCH

tHHQXtHLQZ

AI02032

Figure 25. Output timing

tCLQV

tCLQX

ADDR.

LSB IN

tCLQX

tCLQV

tCH

tCL

tQLQH tQHQL

tSHQZ

LSB OUT

AI01449e

46/53

M25P40 Package mechanical

11 Package mechanical

Figure 26. SO8 narrow – 8 lead plastic Small Outline, 150 mils body width, package

outline

h x 45˚

1. Drawing is not to scale.

2. The ‘1’ that appears in the top view of the package shows the position of pin 1.

Table 22. SO8 narrow – 8 lead plastic Small Outline, 150 mils body width,

ccc

0.25 mm

GAUGE PLANE

SO-A

package mechanical data

millimeters inches

Symbol

Typ Min Max Typ Min Max

A1.750.069

A1 0.10 0.25 0.004 0.010

A2 1.25 0.049

b 0.28 0.48 0.011 0.019

c 0.17 0.23 0.007 0.009

ccc 0.10 0.004

D 4.90 4.80 5.00 0.193 0.189 0.197

E 6.00 5.80 6.20 0.236 0.228 0.244

E1 3.90 3.80 4.00 0.154 0.150 0.157

e1.27– –0.050– –

h 0.25 0.50 0.010 0.020

k 0°8° 0°8°

L 0.40 1.27 0.016 0.050

L1 1.04 0.041

47/53

Package mechanical M25P40

Figure 27. VFQFPN8 (MLP8) 8-lead Very thin Fine pitch Quad Flat Package No lead,

6 × 5 mm, package outline

aaa CA

ddd

CAB

eE2

bbb

70-ME

0.10 CB

0.10 CA

aaa CB

1. Drawing is not to scale.

2. The circle in the top view of the package indicates the position of pin 1.

Table 23. VFQFPN8 (MLP8) 8-lead Very thin Fine pitch Quad Flat Package No lead,

6 × 5 mm, package mechanical data

millimeters inches

Symbol

Typ Min Max Typ Min Max

A 0.85 0.80 1.00 0.0335 0.0315 0.0394

A1 0.00 0.05 0.0000 0.0020

A2 0.65 0.0256

A3 0.20 0.0079

b 0.40 0.35 0.48 0.0157 0.0138 0.0189

D 6.00 0.2362

D1 5.75 0.2264

D2 3.40 3.20 3.60 0.1339 0.1260 0.1417

E 5.00 0.1969

E1 4.75 0.1870

E2 4.00 3.80 4.30 0.1575 0.1496 0.1693

e1.27– –0.0500– –

R1 0.10 0.00 0.0039 0.0000

L 0.60 0.50 0.75 0.0236 0.0197 0.0295

Q 12° 12°

aaa 0.15 0.0059

bbb 0.10 0.0039

ddd 0.05 0.0020

48/53

M25P40 Part numbering

12 Part numbering

Table 24. Ordering information scheme

Example: M25P40 – V MN 6 T P /X

Device Type

M25P = Serial Flash memory for Code Storage

Device Function

40 = 4 Mbit (512 K x 8)

Operating Voltage

V = VCC = 2.3 V to 3.6 V

Package

MN = SO8 (150 mil width) MP = VFQFPN8 6 x 5 mm (MLP8)

Device grade

6 = Industrial temperature range, –40 to 85 °C. Device tested with standard test flow

(1)

= Device tested with High Reliability Certified Flow

Automotive temperature range (–40 to 125 °C)

(2)

Option

blank = Standard Packing T = Tape and Reel Packing

Plating technology

P or G = ECOPACK® (RoHS compliant)

Process

(3)

/X = T7Y

1. Device grade 3 available in an SO8 ECOPACK® (RoHS compliant) package.

2. Numonyx strongly recommends the use of the Automotive Grade devices for use in an automotive

environment. The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest Numonyx sales office for a copy.

3. The process letter (/X) is specified in the ordering information of grade 3 devices only.

For grade 6 devices, the process letter does not appear in the Ordering Information, it only appears on the device package (marking) and on the shipment box. Please contact your nearest Numonyx Sales Office. For more information on how to identify products by the Process Identification Letter, please refer to AN1995: Serial Flash Memory Device Marking.

For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest Numonyx Sales Office.

The category of second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label.

49/53

Revision history M25P40

13 Revision history

Table 25. Document revision history

Date Revision Changes

12-Apr-2001 1.0 Document written.

25-May-2001 1.1 Serial Paged Flash Memory renamed as Serial Flash Memory.

Changes to text: Signal Description/Chip Select; Hold Condition/1st para; Protection modes; Release from Power-down and Read Electronic Signature (RES); Power-up.

11-Sep-2001 1.2

16-Jan-2002 1.3

12-Sep-2002 1.4

13-Dec-2002 1.5

Repositioning of several tables and illustrations without changing their contents.

Power-up timing illustration; SO8W package removed. Changes to tables: Abs Max Ratings/V

FAST_READ instruction added. Document revised with new timings, V

and clock slew rate. Descriptions of Polling, Hold Condition, Page

CC3

; DC Characteristics/VIL.

Programming, Release for Deep Power-down made more precise. Value

(max) modified.

of t

Clarification of descriptions of entering Standby Power mode from Deep Power-down mode, and of terminating an instruction sequence or dataout sequence.

VFQFPN8 package (MLP8) added. Document promoted to Preliminary Data.

Typical Page Program time improved. Deep Power-down current changed. Write Protect setup and hold times specified, for applications that switch Write Protect to exit the Hardware Protection mode immediately before a WRSR, and to enter the Hardware Protection mode again immediately after.

12-Jun-2003 1.6 Document promoted from Preliminary Data to full Datasheet.

Table of contents, warning about exposed paddle on MLP8, and Pb-free options added.

24-Nov-2003 2.0

40 MHz AC Characteristics table included as well as 25 MHz. I

(typ) and tBE(typ) values improved. Change of naming for VDFPN8

package.

12-Mar-2004 3.0

05-Aug-2004 4.0

Automotive range added. Soldering temperature information clarified for RoHS compliant devices.

Device grade information clarified. Data-retention measurement temperature corrected. Details of how to find the date of marking added.

Small text changes. Notes 2 and 3 removed from Table 24: Ordering

03-Jan-2005 5.0

information scheme.

End timing line of t

Updated Page Program (PP) instructions in Page Programming, Page

01-Aug-2005 6.0

Program (PP), Instruction times (device grade 6) and Instruction times (device grade 3).

50/53

modified in Figure 25: Output timing.

SHQZ

CC3

(max),

M25P40 Revision history

Table 25. Document revision history (continued)

Date Revision Changes

50 MHz operation added (see Table 20: AC characteristics (50 MHz

operation, device grade 6, VCC min = 2.7 V)). All packages are

ECOPACK®. Blank option removed from under Plating technology in

24-Oct-2005 7.0

22-Dec-2005 8.0

14-Apr-2006 9

Table 24: Ordering information scheme. MLP package renamed as

VFQFPN, silhouette and package mechanical drawing updated (see on

page 1 and Figure 27: VFQFPN8 (MLP8) 8-lead Very thin Fine pitch Quad Flat Package No lead, 6 × 5 mm, package outline.

Note 2 added below Figure 26 and note 1 added below Figure 27 t

and t

RES1

operation, device grade 6, V

modified in Table 20: AC characteristics (50 MHz

RES2

min = 2.7 V).

Read Identification (RDID) added. Titles of Figure 27 and Ta bl e 2 3

corrected.

The data contained in Ta b l e 11 , Ta b le 1 6 and Ta bl e 1 9 is no longer preliminary data.

Figure 3: Bus Master and memory devices on the SPI bus modified and Note 2 added.

40 MHz frequency condition modified for I

in Table 14: DC

CC3

characteristics (device grade 3). Table 16: Instruction times (device grade 3) shows preliminary data.

Condition changed for the Data Retention parameter in Table 11: Data

retention and endurance. V Table 8: Power-up timing and V

parameter for device grade 3 added to

threshold.

SO8 package specifications updated (see Figure 26 and Ta bl e 2 2). /X Process added to Table 24: Ordering information scheme.

05-Jun-2006 10

18-Dec-2006 11

25-Jan-2007 12

15-May-2007 13

RES1

and t

parameter timings changed for devices produced with the

RES2

“X” process technology in Ta bl e 1 9 and Ta bl e 1 9 . SO8 Narrow package specifications updated (see Figure 26 and

Ta bl e 2 2 ).

Hardware Write Protection feature added on page 1. Small text changes.

Section 2.7: V

supply voltage and Section 2.8: VSS ground added.

Figure 3: Bus Master and memory devices on the SPI bus modified,

note 2 removed and replaced by explanatory paragraph. WIP bit behavior specified at Power-up in Section 7: Power-up and

Power-down. T

added to Table 9: Absolute maximum ratings and VIO

LEAD

max modified. VFQFPN8 package specifications updated (see Ta b le 23 and Figure 27).

voltage range from W17 2007 is extended to 2.3 V to 3.6 V.

Table 21: AC characteristics (33 MHz operation, device grade 6, VCCmin =2.3 V) added.

Table 18: Which AC characteristics to use? added. AC characteristics at

40 MHz removed.

40 MHz operation added (see Table 21: AC characteristics (40 MHz

operation, device grade 6, VCC min = 2.3 V).

Removed the note below Tab l e 1 0 . Removed “AC characteristics (33 MHz operation, device grade 6, VCCmin =2.3 V)” Table.

51/53

Revision history M25P40

Table 25. Document revision history (continued)

Date Revision Changes

Modified the note below Ta b le 1 2 .

26-Jun-2007 14

10-Dec-2007 15 Applied Numonyx branding.

Changed test condition for I Changed clock frequency, from 20 to 25 MHz, in Ta bl e 2 0 and Ta bl e 2 1 .

in Ta bl e 1 3 .

CC3

52/53

M25P40

Please Read Carefully:

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR

IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT

AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY

WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF

NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,

MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility

Numonyx may make changes to specifications and product descriptions at any time, without notice.

Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,

by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves

these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by

visiting Numonyx's website at http://www.numonyx.com.

Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.

*Other names and brands may be claimed as the property of others.

applications.

53/53

Numonyx M25P40 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Description

Figure 1. Logic diagram

Table 1. Signal names

Figure 2. SO and VFQFPN connections

2 Signal description

2.1 Serial Data output (Q)

2.2 Serial Data input (D)

2.3 Serial Clock (C)

2.4 Chip Select (S)

2.5 Hold (HOLD)

2.6 Write Protect (W)

2.7 VCC supply voltage

2.8 VSS ground

3 SPI modes

Figure 3. Bus Master and memory devices on the SPI bus

Figure 4. SPI modes supported

4 Operating features

4.1 Page Programming

4.2 Sector Erase and Bulk Erase

4.3 Polling during a Write, Program or Erase cycle

4.4 Active Power, Standby Power and Deep Power-down modes

4.5 Status Register

4.6 Protection modes

Table 2. Protected area sizes

4.7 Hold condition

Figure 5. Hold condition activation

5 Memory organization

Table 3. Memory organization

Figure 6. Block diagram

6 Instructions

Table 4. Instruction set

6.1 Write Enable (WREN)

Figure 7. Write Enable (WREN) instruction sequence

6.2 Write Disable (WRDI)

Figure 8. Write Disable (WRDI) instruction sequence

6.3 Read Identification (RDID)

Table 5. Read Identification (RDID) data-out sequence

Figure 9. Read Identification (RDID) instruction sequence and data-out sequence

6.4 Read Status Register (RDSR)

Table 6. Status Register format

6.4.1 WIP bit

6.4.2 WEL bit

6.4.3 BP2, BP1, BP0 bits

6.4.4 SRWD bit

6.5 Write Status Register (WRSR)

Figure 11. Write Status Register (WRSR) instruction sequence

Table 7. Protection modes

6.6 Read Data Bytes (READ)

Figure 12. Read Data Bytes (READ) instruction sequence and data-out sequence

6.7 Read Data Bytes at Higher Speed (FAST_READ)

6.8 Page Program (PP)

Figure 14. Page Program (PP) instruction sequence

6.9 Sector Erase (SE)

Figure 15. Sector Erase (SE) instruction sequence

6.10 Bulk Erase (BE)

Figure 16. Bulk Erase (BE) instruction sequence

6.11 Deep Power-down (DP)

Figure 17. Deep Power-down (DP) instruction sequence

6.12 Release from Deep Power-down and Read Electronic Signature (RES)

Figure 19. Release from Deep Power-down (RES) instruction sequence

7 Power-up and Power-down

Figure 20. Power-up timing

8 Initial delivery state

9 Maximum rating

Table 9. Absolute maximum ratings

10 DC and ac parameters

Table 10. Operating conditions

Table 11. Data retention and endurance

Table 12. Capacitance

Table 13. DC characteristics (device grade 6)

Table 14. DC characteristics (device grade 3)

Table 15. Instruction times (device grade 6)

Table 16. Instruction times (device grade 3)

Table 17. AC measurement conditions

Figure 21. AC measurement I/O waveform

Table 18. Which AC characteristics to use?