Numonyx M25P10-A Technical data
1 Mbit, serial Flash memory, 50 MHz SPI bus interface
Features
■ 1 Mbit of Flash memory
■ Page Program (up to 256 bytes) in 1.4 ms
(typical)
■ Sector Erase (256 Kbit) in 0.65 s (typical)
■ Bulk Erase (1 Mbit) in 1.7 s (typical)
■ 2.3 to 3.6 V single supply voltage
■ SPI bus compatible serial interface
■ 50 MHz Clock rate (maximum)
■ Deep Power-down mode 1 µA (typical)
■ Electronic signatures
– JEDEC standard two-byte signature
(2011h)
– RES instruction, one-byte signature (10h),
for backward compatibility
■ More than 20 years’ data retention
■ Packages
– ECOPACK® (RoHS compliant)
M25P10-A
SO8 (MN)
150 mil width
VFQFPN8 (MP)
(MLP8)
UFDFPN8 (MB)
2x3mm
December 2007 Rev 11 1/51
www.numonyx.com
1
Contents M25P10-A
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Chip Select (S
2.5 Hold (HOLD
2.6 Write Protect (W
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3 Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . . 11
4.4 Active Power, Standby Power and Deep Power-down modes . . . . . . . . . 11
4.5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.6 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.7 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3 Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.5 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2/51
M25P10-A Contents
6.6 Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.7 Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . 25
6.8 Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.9 Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.10 Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.11 Deep Power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.12 Release from Deep Power-down and Read Electronic Signature (RES) . 31
7 Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
11 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
12 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3/51
List of tables M25P10-A
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Protected area sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3. Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. Read identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 8. Power-up timing and VWI threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 9. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 10. Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 11. Data retention and endurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 12. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 13. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 14. DC characteristics (device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 15. DC characteristics (device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 16. Instruction times (device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 17. Instruction times (device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 18. AC characteristics (25 MHz operation, device grade 6 or 3) . . . . . . . . . . . . . . . . . . . . . . . 40
Table 19. AC characteristics (40 MHz operation, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 20. AC characteristics (50 MHz operation, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 21. SO8 narrow – 8-lead plastic small outline, 150 mils body width,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 22. VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 23. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead,
2 x 3 mm package mechanical data47
Table 24. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 25. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4/51
M25P10-A List of figures
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. SO, VFQFPN and UFDFPN8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Bus master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. Hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8. Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9. Read Identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 19
Figure 10. Read Status Register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . 21
Figure 11. Write Status Register (WRSR) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12. Read Data Bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 24
Figure 13. Read Data Bytes at Higher Speed (FAST_READ) instruction sequence
and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 14. Page Program (PP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 15. Sector Erase (SE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 16. Bulk Erase (BE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 17. Deep Power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 18. Release from Deep Power-down and Read Electronic Signature (RES) instruction
sequence and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 19. Release from Deep Power-down (RES) instruction sequence . . . . . . . . . . . . . . . . . . . . . . 32
Figure 20. Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 21. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 22. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 23. Write Protect Setup and Hold timing during WRSR when SRWD=1 . . . . . . . . . . . . . . . . . 43
Figure 24. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 25. Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 26. SO8 narrow – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . 45
Figure 27. VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead,
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 28. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead,
2 x 3 mm package outline47
5/51
Description M25P10-A
1 Description
The M25P10-A is a 1 Mbit (128 Kbit x 8) serial Flash memory, with advanced write
protection mechanisms, accessed by a high speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time, using the Page Program
instruction.
The memory is organized as 4 sectors, each containing 128 pages. Each page is 256 bytes
wide. Thus, the whole memory can be viewed as consisting of 512 pages, or 131,072 bytes.
The whole memory can be erased using the Bulk Erase instruction, or a sector at a time,
using the Sector Erase instruction.
Figure 1. Logic diagram
V
CC
D
C
S
W
HOLD
M25P10-A
V
SS
Q
AI05760
Table 1. Signal names
Signal name Function Direction
C Serial Clock Input
D Serial Data input Input
Q Serial Data output Output
S
W
HOLD
V
CC
V
SS
Chip Select Input
Write Protect Input
Hold Input
Supply voltage
Ground
6/51
M25P10-A Description
Figure 2. SO, VFQFPN and UFDFPN8 connections
M25P10-A
SV
1
2
3
W
4
SS
1. There is an exposed die paddle on the underside of the MLP8 packages. This is pulled, internally, to VSS,
and must not be allowed to be connected to any other voltage or signal line on the PCB.
2. See Package mechanical section for package dimensions, and how to identify pin-1.
8
7
6
5
AI05761B
CC
HOLDQ
C
DV
7/51
Signal descriptions M25P10-A
2 Signal descriptions
2.1 Serial Data output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
2.2 Serial Data input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be programmed. Values are latched on the rising edge of Serial
Clock (C).
2.3 Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data output (Q) changes after the falling edge of Serial Clock (C).
2.4 Chip Select (S)
When this input signal is High, the device is deselected and Serial Data output (Q) is at high
impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress,
the device will be in the Standby mode (this is not the Deep Power-down mode). Driving
Chip Select (S
After power-up, a falling edge on Chip Select (S
instruction.
) Low selects the device, placing it in the Active Power mode.
2.5 Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data
input (D) and Serial Clock (C) are Don’t care.
To start the Hold condition, the device must be selected, with Chip Select (S
2.6 Write Protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is
protected against program or erase instructions (as specified by the values in the BP1 and
BP0 bits of the Status Register).
) is required prior to the start of any
) driven Low.
8/51
M25P10-A SPI modes
3 SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
● CPOL=0, CPHA=0
● CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 4, is the clock polarity when the
bus master is in Standby mode and not transferring data:
● C remains at 0 for (CPOL=0, CPHA=0)
● C remains at 1 for (CPOL=1, CPHA=1)
Figure 3. Bus master and memory devices on the SPI bus
V
SS
V
CC
R
SPI interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SPI Bus Master
CS3 CS2 CS1
1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
SDO
SDI
SCK
device
W
V
CC
HOLD
V
CQD
RRR
SPI memory
S
CQD
SS
SPI memory
S
device
V
CC
V
SS
HOLD
W
Figure 3 shows an example of three devices connected to an MCU, on an SPI bus. Only one
device is selected at a time, so only one device drives the Serial Data output (Q) line at a
time, the other devices are high impedance. Resistors R (represented in Figure 3) ensure
that the M25P10-A is not selected if the Bus Master leaves the S
state. As the Bus Master may enter a state where all inputs/outputs are in high impedance
at the same time (for example, when the Bus Master is reset), the clock line (C) must be
connected to an external pull-down resistor so that, when all inputs/outputs become high
impedance, the S
C do not become High at the same time, and so, that the t
line is pulled High while the C line is pulled Low (thus ensuring that S and
requirement is met). The
SHCH
typical value of R is 100 kΩ, assuming that the time constant R*C
capacitance of the bus line) is shorter than the time during which the Bus Master leaves the
SPI bus in high impedance.
device
V
CC
V
SS
HOLD
W
AI12836b
CQD
SPI memory
S
line in the high impedance
(Cp = parasitic
p
9/51
SPI modes M25P10-A
Example: Cp = 50 pF, that is R*Cp = 5 µs <=> the application must ensure that the Bus
Master never leaves the SPI bus in the high impedance state for a time period shorter than
5µs.
Figure 4. SPI modes supported
CPHA
CPOL
C
0
0
1
1
C
D
Q
MSB
MSB
AI01438B
10/51
M25P10-A Operating features
4 Operating features
4.1 Page Programming
To program one data byte, two instructions are required: Write Enable (WREN), which is one
byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is
followed by the internal Program cycle (of duration t
To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be
programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive
addresses on the same page of memory.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few bytes (see Page Program (PP)
and Table 16: Instruction times (device grade 6)).
4.2 Sector Erase and Bulk Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be
applied, the bytes of memory need to have been erased to all 1s (FFh). This can be
achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the
entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of
duration t
The Erase instruction must be preceded by a Write Enable (WREN) instruction.
or tBE).
SE
PP
).
4.3 Polling during a Write, Program or Erase cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase
(SE or BE) can be achieved by not waiting for the worst case delay (t
Write In Progress (WIP) bit is provided in the Status Register so that the application program
can monitor its value, polling it to establish when the previous Write cycle, Program cycle or
Erase cycle is complete.
, tPP, tSE, or tBE). The
W
4.4 Active Power, Standby Power and Deep Power-down modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode.
When Chip Select (S
mode until all internal cycles have completed (Program, Erase, Write Status Register). The
device then goes in to the Standby Power mode. The device consumption drops to I
The Deep Power-down mode is entered when the specific instruction (the Deep Powerdown (DP) instruction) is executed. The device consumption drops further to I
device remains in this mode until another specific instruction (the Release from Deep
Power-down and Read Electronic Signature (RES) instruction) is executed.
While in the Deep Power-down mode, the device ignores all write, program and erase
instructions (see Deep Power-down (DP)). This can be used as an extra software protection
mechanism, when the device is not in active use, to protect the device from inadvertent
write, program or erase instructions.
) is High, the device is deselected, but could remain in the Active Power
.
CC1
. The
CC2
11/51
Operating features M25P10-A
4.5 Status Register
The Status Register contains a number of status and control bits, as shown in Tab l e 6 , that
can be read or set (as appropriate) by specific instructions. For a detailed description of the
Status Register bits, see Section 6.4: Read Status Register (RDSR).
4.6 Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M25P10-A features the following data protection mechanisms:
● Power On Reset and an internal timer (t
changes while the power supply is outside the operating specification.
● Program, Erase and Write Status Register instructions are checked that they consist of
a number of clock pulses that is a multiple of eight, before they are accepted for
execution.
● All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–Power-up
– Write Disable (WRDI) instruction completion
– Write Status Register (WRSR) instruction completion
– Page Program (PP) instruction completion
– Sector Erase (SE) instruction completion
– Bulk Erase (BE) instruction completion
● The Block Protect (BP1, BP0) bits allow part of the memory to be configured as read-
only. This is the Software Protected mode (SPM).
● The Write Protect (W) signal, in co-operation with the Status Register Write Disable
(SRWD) bit, allows the Block Protect (BP1, BP0) bits and Status Register Write Disable
(SRWD) bit to be write-protected. This is the Hardware Protected mode (HPM).
● In addition to the low power consumption feature, the Deep Power-down mode offers
extra software protection, as all write, program and erase instructions are ignored.
) can provide protection against inadvertent
PUW
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M25P10-A Operating features
Table 2. Protected area sizes
Status
Register
content
Memory content
BP1
bit
1. The device is ready to accept a Bulk Erase instruction if, and only if, both Block Protect (BP1, BP0) bits are
0.
BP0
bit
0 0 none All sectors
0 1 Upper quarter (sector 3) Lower three-quarters (three sectors: 0 to 2)
1 0 Upper half (two sectors: 2 and 3) Lower half (sectors 0 and 1)
1 1 All sectors (four sectors: 0, 1, 2 and 3) none
4.7 Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence. However, taking this signal Low does not terminate any
Write Status Register, Program or Erase cycle that is currently in progress.
To enter the Hold condition, the device must be selected, with Chip Select (S
The Hold condition starts on the falling edge of the Hold (HOLD
coincides with Serial Clock (C) being Low (as shown in Figure 5).
The Hold condition ends on the rising edge of the Hold (HOLD
coincides with Serial Clock (C) being Low.
If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition
starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide
with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes
Low. (This is shown in Figure 5).
Protected area Unprotected area
(1)
(four sectors: 0, 1, 2 and 3)
) Low.
) signal, provided that this
) signal, provided that this
During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data
input (D) and Serial Clock (C) are Don’t care.
Normally, the device is kept selected, with Chip Select (S
) driven Low, for the whole duration
of the Hold condition. This is to ensure that the state of the internal logic remains unchanged
from the moment of entering the Hold condition.
If Chip Select (S
) goes High while the device is in the Hold condition, this has the effect of
resetting the internal logic of the device. To restart communication with the device, it is
necessary to drive Hold (HOLD
) High, and then to drive Chip Select (S) Low. This prevents
the device from going back to the Hold condition.
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Operating features M25P10-A
Figure 5. Hold condition activation
C
HOLD
Hold
condition
(standard use)
Hold
condition
(non-standard use)
AI02029D
14/51
M25P10-A Memory organization
5 Memory organization
The memory is organized as:
● 131,072 bytes (8 bits each)
● 4 sectors (256 Kbits, 32768 bytes each)
● 512 pages (256 bytes each).
Each page can be individually programmed (bits are programmed from 1 to 0). The device is
sector or bulk erasable (bits are erased from 0 to 1) but not page erasable.
Table 3. Memory organization
Sector Address range
3 18000h 1FFFFh
2 10000h 17FFFh
1 08000h 0FFFFh
0 00000h 07FFFh
Figure 6. Block diagram
HOLD
W
S
C
D
Q
Control Logic
I/O Shift Register
Address Register
and Counter
18000h
10000h
Y Decoder
08000h
00000h
High Voltage
Generator
256 byte
Data Buffer
256 bytes (page size)
Status
Register
1FFFFh
000FFh
X Decoder
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Instructions M25P10-A
6 Instructions
All instructions, addresses and data are shifted in and out of the device, most significant bit
first.
Serial Data input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select
(S
) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most
significant bit first, on Serial Data input (D), each bit being latched on the rising edges of
Serial Clock (C).
The instruction set is listed in Ta bl e 4 .
Every instruction sequence starts with a one-byte instruction code. Depending on the
instruction, this might be followed by address bytes, or by data bytes, or by both or none.
Chip Select (S
shifted in.
In the case of a Read Data Bytes (READ), Read Data Bytes at higher speed (FAST_READ),
Read Identification (RDID), Read Status Register (RDSR) or Release from Deep Powerdown, and Read Electronic Signature (RES) instruction, the shifted-in instruction sequence
is followed by a data-out sequence. Chip Select (S
data-out sequence is being shifted out.
) must be driven High after the last bit of the instruction sequence has been
) can be driven High after any bit of the
In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status
Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP)
instruction, Chip Select (S
instruction is rejected, and is not executed. That is, Chip Select (S
the number of clock pulses after Chip Select (S
eight.
All attempts to access the memory array during a Write Status Register cycle, Program
cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program
cycle or Erase cycle continues unaffected.
) must be driven High exactly at a byte boundary, otherwise the
) must driven High when
) being driven Low is an exact multiple of
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