Numonyx M25P05-A Technical data
512-Kbit, serial flash memory, 50 MHz SPI bus interface
Features
■ 512 Kbits of flash memory
■ Page program (up to 256 bytes) in 1.4 ms
(typical)
■ Sector erase (256 Kbits) in 0.65 s (typical)
■ Bulk erase (512 Kbits) in 0.85 s (typical)
■ 2.3 to 3.6 V single supply voltage
■ SPI bus compatible serial interface
■ 50 MHz clock rate (maximum)
■ Deep power-down mode 1 µA (typical)
■ Electronic signatures
– JEDEC standard two-byte signature
(2010h)
– RES instruction, one-byte, signature (05h),
for backward compatibility
■ More than 100,000 erase/program cycles per
sector
■ More than 20 years data retention
■ ECOPACK® packages available
M25P05-A
SO8 (MN)
150 mil width
VFQFPN8 (MP)
(MLP8)
TSSOP8 (DW)
UFDFPN8 (MB)
2x3mm
April 2008 Rev 11 1/52
www.numonyx.com
1
Contents M25P05-A
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Chip Select (S
2.5 Hold (HOLD
2.6 Write Protect (W
2.7 V
2.8 V
supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CC
ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SS
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Page programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 Sector erase and bulk erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 Polling during a write, program or erase cycle . . . . . . . . . . . . . . . . . . . . . 12
4.4 Active power, standby power and deep power-down modes . . . . . . . . . . 12
4.5 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.6 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.7 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1 Write enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.2 Write disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.3 Read identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/52
M25P05-A Contents
6.4 Read status register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.4.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.4.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.4.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.4.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.5 Write status register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.6 Read data bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.7 Read data bytes at higher speed (FAST_READ) . . . . . . . . . . . . . . . . . . . 27
6.8 Page program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.9 Sector erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.10 Bulk erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.11 Deep power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.12 Release from deep power-down and read electronic signature (RES) . . 33
7 Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
11 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
12 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3/52
List of tables M25P05-A
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Protected area sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3. Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5. Read identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 6. Status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 7. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 8. Power-up timing and VWI threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 9. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 10. Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 11. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 12. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 13. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 14. Instruction times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 15. AC characteristics (25 MHz operation). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 16. AC characteristics (40 MHz operation). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 17. AC characteristics (50 MHz operation). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 18. SO8N – 8 lead plastic small outline, 150 mils body width, package mechanical data . . . . 45
Table 19. VFQFPN8 (MLP8) - 8 lead very thin fin e pitch quad flat package no lead,
6 × 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 20. TSSOP8 – 8 lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 47
Table 21. UFDFPN8 (MLP8) – 8 lead ultra thin fine pitch dual flat package no lead,
2 x 3 mm package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 22. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 23. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4/52
M25P05-A List of figures
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. SO, VFQFPN and TSSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Bus master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7. Write enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 8. Write disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9. Read identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 21
Figure 10. Read status register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . . 23
Figure 11. Write status register (WRSR) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12. Read data bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 26
Figure 13. Read data bytes at higher speed (FAST_READ) instruction sequence
and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 14. Page program (PP) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 15. Sector erase (SE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 16. Bulk erase (BE) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 17. Deep power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 18. Release from deep power-down and read electronic signature (RES)
instruction sequence and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 19. Release from deep power-down (RES) instruction sequence . . . . . . . . . . . . . . . . . . . . . . 34
Figure 20. Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 21. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 22. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 23. Write protect setup and hold timing during WRSR when SRWD =1. . . . . . . . . . . . . . . . . . 43
Figure 24. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 25. Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 26. SO8N – 8 lead plastic small outline , 150 mils body width, package outline . . . . . . . . . . . . 45
Figure 27. VFQFPN8 (MLP8) - 8 lead very thin fine pitch quad flat package no lead,
6 × 5 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 28. TSSOP8 – 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 29. UFDFPN8 (MLP8) – 8 lead ultra thin fine pitch dual flat package no lead,
2 x 3 mm package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5/52
Description M25P05-A
1 Description
The M25P05-A is a 512-Kbit (64 Kbits ×8) serial flash memory, with advanced write
protection mechanisms, accessed by a high speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time, using the page program
instruction.
The memory is organized as 2 sectors, each co ntaini ng 128 pages. Each page is 256 bytes
wide. Thus, the whole memory can be viewed as consisting of 256 pages, or 65,536 bytes.
The whole memory can be erased using the bulk erase instruction, or a sector at a time,
using the sector erase instruction.
Figure 1. Logic diagram
V
CC
D
C
S
W
HOLD
Table 1. Signal names
Signal name Function Direction
C Serial Clock Input
D Serial Data input Input
Q Serial Data output Output
S
Write Protect Input
W
Hold Input
HOLD
Chip Select Input
M25P05-A
V
SS
Q
AI05757
V
CC
V
SS
6/52
Supply voltage Supply
Ground Supply
M25P05-A Description
Figure 2. SO, VFQFPN and TSSOP connections
M25P05-A
SV
1
2
3
W
4
SS
1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally, to
VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB.
2. See Package mechanical section for package dimensions, and how to identify pin-1.
8
7
6
5
AI05758B
CC
HOLDQ
C
DV
7/52
Signal descriptions M25P05-A
2 Signal descriptions
2.1 Serial Data output (Q)
This output signal is used to transf er data serially out of the de vice . Data is shifted out on the
falling edge of Serial Clock (C).
2.2 Serial Data input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be programmed. Values are latched on the rising edge of Serial
Clock (C).
2.3 Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data output (Q) changes after the falling edge of Serial Clock (C).
2.4 Chip Select (S)
When this input signal is High, the device is deselected and Serial Data output (Q) is at high
impedance. Unless an internal program, erase or write status register cycle is in progress,
the device will be in the standby mode (this is not the deep power-do wn mode). Driving Chip
Select (S
After power-up, a falling edge on Chip Select (S
instruction.
) Low enables the device, placing it in the active power mode.
2.5 Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the de vice without
deselecting the device.
During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data
input (D) and Serial Clock (C) are don’t care.
To start the Hold condition, the device must be selected, with Chip Select (S
2.6 Write Protect (W)
The main purpose of this input signal is to freeze the size of the area of mem ory that is
protected against program or erase instructions (as specified by the values in the BP1 and
BP0 bits of the status register).
) is required prior to the start of any
) driven Low.
8/52
M25P05-A Signal descriptions
2.7 VCC supply voltage
VCC is the supply voltage.
2.8 VSS ground
VSS is the reference for the VCC supply voltage.
9/52
SPI modes M25P05-A
3 SPI modes
These devices can be drive n by a microcontroller with its SPI peripheral running in either of
the two following modes:
● CPOL=0, CPHA=0
● CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 4, is the clock polarity when the
bus master is in standby mode and not transferring data:
● C remains at 0 for (CPOL=0, CPHA=0)
● C remains at 1 for (CPOL=1, CPHA=1)
Figure 3. Bus master and memory devices on the SPI bus
V
SS
V
CC
R
SPI interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SPI bus master
CS3 CS2 CS1
1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
SDO
SDI
SCK
device
W
V
CC
HOLD
V
CQD
RR R
SPI memory
S
CQD
SS
SPI memory
S
device
W
V
CC
HOLD
V
CQD
SS
SPI memory
device
S
V
CC
V
SS
HOLD
W
AI12836b
Figure 3 shows an example of three de vices connected to an MCU , on an SPI bus . Only one
device is selected at a time, so only one device drives the Serial Data output (Q) line at a
time, the other devices are high impedance. Resistors R (represented in Figure 3) ensure
that the M25P05-A is not selected if the bus master leav es th e S
line in the high impedance
state. As the bus master ma y enter a state where all inpu ts/outputs are in high impedance at
the same time (for example, when the bus master is reset), the clock line (C) must be
connected to an external pull-down resistor so that, when all inputs/outputs become high
impedance, the S
C do not become High at the same time, and so, that the t
typical value of R is 100 kΩ, assuming that the time constant R*C
line is pulled High while the C line is pulled Low (thus ensuring that S a nd
requirement is met). The
SHCH
(Cp = parasitic
p
capacitance of the bus line) is shorter than the time during which the bus master leaves the
SPI bus in high impedance.
10/52
M25P05-A SPI modes
Example: Cp = 50 pF, that is R*Cp = 5 µs <=> the application must ensure that the bus
master never leaves the SPI bus in the high impedance state for a time period shorter than
5µs.
Figure 4. SPI modes supported
CPHA
CPOL
C
0
0
1
1
C
D
Q
MSB
MSB
AI01438B
11/52
Operating features M25P05-A
4 Operating features
4.1 Page programming
To program one data byte, two in structions are required: Write Enable (WREN), which is one
byte, and a page program (PP) sequence, which consists of four bytes plus data. This is
followed by the internal program cycle (of duration t
To spread this overhead, the page program (PP) instruction allows up to 256 bytes to be
programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive
addresses on the same page of memory.
For optimized timings, it is recommended to use the page program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several page
program (PP) sequences with each containing only a few bytes (see Section 6.8: Page
program (PP) and Table 14: Instruction times).
4.2 Sector erase and bulk erase
The page program (PP) instruction allows bits to be reset from 1 to 0. Before this can be
applied, the bytes of memory need to have been erased to all 1s (FFh). This can be
achiev ed either a sector a t a time, using the sector erase (SE) inst ruction, or t hroug hout the
entire memory, using the bulk erase (BE) instruction. This starts an internal erase cycle (of
duration t
The erase instruction must be preceded by a write enable (WREN) instruction.
or tBE).
SE
PP
).
4.3 Polling during a write, program or erase cycle
A further improvement in the time to write status register (WRSR), program (PP) or erase
(SE or BE) can be achiev ed by not waiting for the w o rst case d elay (t
write in progress (WIP) bit is provided in the status register so that the application program
can monitor its value, polling it to establish when the previous write cycle, program cycle or
erase cycle is complete.
, tPP, tSE, or tBE). The
W
4.4 Active power, standby power and deep power-down modes
When Chip Select (S) is Low, the device is selected, and in the active power mode.
When Chip Select (S
mode until all internal cycles have completed (prog ram, erase, write status register). The
device then goes in to the standby power mode. The device consumption drops to I
The deep power-do wn mo de is en tere d when th e specific in struction (the de ep power-down
(DP) instruction) is executed. The device consumption drops further to I
remains in this mode until another specific instruction (the release from deep power-down
and read electronic signature (RES) instruction) is executed.
While in the deep power-down mode, the device ignores all write, program and erase
instructions (see Section 6.11: Deep power-down (DP)). This can be used as an extra
software protection mechanism, when the device is not in active use, to protect the device
from inadvertent write, program or erase instructions .
) is High, the device is dese lected, b ut could rema in in the activ e pow er
.
CC1
. The device
CC2
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M25P05-A Operating features
4.5 Status register
The status register contains a number of status and control bits, as shown in Table 6, that
can be read or set (as appropriate) by specific instructions.
4.5.1 WIP bit
The write in progress (WIP) bit indicates whether the memory is busy with a write status
register, program or erase cycle.
4.5.2 WEL bit
The write enable latch (WEL) bit indicates the status of the internal write enable latch.
4.5.3 BP1, BP0 bits
The block protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against program and erase instructions.
4.5.4 SRWD bit
The status register write disable (SRWD) bit is operated in conjunction with the Write
Protect (W
allow the device t o be put in the hardwar e protected mode . In this mode, the non- volatile bits
of the status register (SRWD, BP1, BP0) become read-only bits.
) signal. The status register write disable ( SRWD) b it and Write Protect (W) signal
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Operating features M25P05-A
4.6 Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M25P05-A features the following data protection mechanisms:
● Power on reset and an internal timer (t
changes while the power supply is outside the operating specification
● Program, er ase and write status reg ister instructions are chec ked that they consist of a
number of clock pulses that is a multiple of eight, before they are accepted for
execution
● All instructions that modify data must be preceded by a write enable (WREN)
instruction to set the write enable latch (WEL) bit. This bit is returned to its reset state
by the following events:
–Power-up
– Write disable (WRDI) instruction completion
– Write status register (WRSR) instruction completion
– Page program (PP) instruction completion
– Sector erase (SE) instruction completion
– Bulk erase (BE) instruction completion
● The block protect (BP1, BP0) bits allow part of the memory to be configured as read-
only. This is the software protected mode (SPM)
● The Write Protect (W) signal, in co-ope ration with the status register write disable
(SRWD) bit, allows the block protect (BP1, BP0) bits and status register write disable
(SRWD) bit to be write-protected. This is the hardware protected mode (HPM)
● In addition to the low power consumption feature, the deep power-down mode offers
extra software protection, as all write, program and erase instructions are ignored.
Table 2. Protected area sizes
) can provide protection against inadvertent
PUW
Status Register
content
BP1 bit BP0 bit Protected area Unprotected area
0 0 none All sectors (sectors 0 and 1)
0 1
1 0
1 1 All sectors (sectors 0 and 1) none
1. The device is ready to accept a bulk erase instruction if, and only if, both block protect (BP1, BP0) are 0.
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No protection against page program (PP) and sector erase (SE)
All sectors (sectors 0 and 1) protected against bulk erase (BE)
Memory content
M25P05-A Operating features
4.7 Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the de vice without
resetting the clocking sequence. However, taking this signal Low does not terminate any
write status register, program or erase cycle that is currently in progress.
To enter the hold condition, the device must be selected, with Chip Select (S
The hold condition starts on the falling edge of the Hold (HOLD
) signal, provided that this
) Low.
coincides with Serial Clock (C) being Low (as shown in Figure 5).
The hold condition ends on the rising edge of the Hold (HOLD
) signal, provided that this
coincides with Serial Clock (C) being Low.
If the falling edge does not coincide with Serial Clock (C) being Low, the hold condition
starts after Serial Clock (C) next goes Low. Similarly , if the rising edge does not coincide
with Serial Clock (C) being Low, the hold condition ends after Serial Clock (C) next goes
Low (this is shown in Figure 5).
During the hold condition, the Serial Data output (Q) is high impedance, and Serial Data
input (D) and Serial Clock (C) are don’t care.
Normally , the de vice is k ept selected, with Chip Select (S
) driven Low, for the whole duration
of the hold condition. This is to ensure that the state of the inte rnal logic remains unchanged
from the moment of entering the hold condition.
If Chip Select (S
) goes High while the device is in the hold condition, this has the effect of
resetting the internal logic of the device. To restart communication with the device, it is
necessary to drive Hold (HOLD
) High, and then to drive Chip Select (S) Low. This prevents
the device from going back to the hold condition.
Figure 5. Hold condition activation
HOLD
C
Hold
condition
(standard use)
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Hold
condition
(non-standard use)
AI02029D
Memory organization M25P05-A
5 Memory organization
The memory is organized as:
● 65,536 b ytes (8 bits each)
● 2 sectors (256 Kbits, 32768 bytes each)
● 256 pages (256 bytes each).
Each page can be individually prog rammed ( bits are prog rammed from 1 t o 0). The de vice is
sector or bulk erasable (bits are erased from 0 to 1) but not page erasable.
Table 3. Memory organization
Sector Address range
1 08000h 0FFFFh
0 00000h 07FFFh
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