NTE NTE849 Datasheet

NTE849

Integrated Circuit

TV Horizontal/Vertical Countdown

Digital Sync System

Description:

The NTE849 is an integrated circuit in a 14–Lead DIP type package designed for use in TV horizontal/
vetical countdown digital sync systems. In some video playback units, there are incorrect frequency
relationships between horizontal and field frequencies. Automatic forced asynchronous mode elimi­nates jitter when equalizer pulses are correct, but these incorrect frequency relationships exist.

Automatic standard mode occurs upon detection of nine or more equalizing pulses during a six–line–
width vertical driving period after seven fields of coincidence between integrated vertical (IV) sync and
internal counter output. Standard mode is retained for seven fields of missing or mutilated vertical
sync pulses.

If two or more noise pulses are detected at Pin12 during a 384–line active scan time, a noise detector
reverts the system to standard mode at the next field of coincidence (without seven fields of coinci­dene delay). Thus, the unit stays in standard mode during tuner channel changes.

An automatic mode–recognition system places the unit in standard mode for NTSC signals or into
non–synchronous mode for non–standard sync signals.

An external oscillator (NTE701) supplies an input to Pin9 that is 32 times the horizontal rate. An inter­nal divide–by–16 counter converts this input (32fH) to 2fH for use elsewhere. This 32fH signal is further
divided to fH, which is available at Pin11 to drive the horizontal deflection circuits. A divide–by–525
counter further divides the 2fH signal to generate the vertical ramp generator timing pulses and the
vertical blanking pulse.

A phasing circuit (part of the mode recognition and vertical regeneration circuits) insures that the 525
counter is reset in coincidence with the vertical sync. It does this by comparing the internally gener­ated vertical pulse with an extrnal integrated vertical sync signal applied to Pin12. The automatic
mode recognition circuit forces the NTE849 into the standard mode for NTSC signals or into the non–
synchronous mode for non–standard sync signals such as video games. An input control signal (or
no connection) at Pin8 places the NTE849 into non–synchronous operation.

A phasing and timing logic circuit checks to see if the line counter is in sync with the IV signal at Pin12.
Seven consecutive fields of in–phase coincidence with the IV signal are needed to achieve standard
mode in unless two or more noise pulses are de–detected at input Pin12 during the active scan time.
In this case, normal mode will be acquired in one field.

Description (Cont’d):

In the standard divide–by–525 mode, the integrated vertical pulse is used only to provide coincidence
with the 545 count (counter preset = 20, 545 – 20 = 525) in the phase detector circuit. The vertical
ramp is timed by the output of the 525 counter. In standard mode, the NTE849 will maintain the divide–
by–525 count for six fields of lost or mutilated sync. If the seventh field does not have the correct coin­cidence, the unit will switch to non–standard mode. In this mode, the vertical sync is derived from
the integrated vertical pulse on a field–to–field basis. A noise immunity of 384 lines is provided. In
the absence of sync pulses, the count will be 684 instead of 525 so that rapid vertical capture may
be achieved when sync is restored. Non–satndard mode still may be selected by removing GND from
Pin8.

The vertical retrace signal is converted to a ramp signal if a capacitor is connected between Pin3 and
GND. The ramp’s slope corresponds to vertical size and is controlled by changing the input current
to Pin2. The ramp is connected to the inverting input of a diffrence amplifier. The output of this amplifi­er, connectd to Pin6, is used to drive the vertical output stage. The non –inverting input of the differ-
ence amplifier is at Pin5. A voltage derived from yoke current may be applied to this pin for linearity
improvement.

The pulse width of the vertical blanking signal at Pin7 is 608 clocks wide in the synchronous mode,
and is adjustable in width by changing the monostable RC network at Pin10 for the non–synchronous
mode.

The proportional voltage regulator output at Pin4 is about 43% of the supply voltage at Pin12. The
maximum external load current is 20mA (Peak).

Features:

D Automatic Forced Asynchronous Mode to

Remove Jitter

D Improved Low Voltage Start–Up Operation
D Lower Zero–State Horizontal–Drive Pulse

Output

D Improved Symmetry for Horizontal–Drive

Output

D Improved Automatic Standard Operation
D Noise Detector
D Handles Standard NTSC and Non–Standard

Signals

D Automatic Mode Recognition

Absolute Maximum Ratings:

DC Supply Voltage 15V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Device Dissipation (TA ≤ +70°C) 530mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Derate Linearily Above 70°C 6.7mW/°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D Clock Input
D Vertical Ramp (Sawtooth) Generator
D Vertical Amplifier
D Vertical Blanking Generator
D Horizontal Drive Pulse Output
D Ratio–Voltage Regulator
D Inherent Interlace for NTSC Signals
D Vertical–Hold Control Eliminated
D Supply Voltage Range: 10.8V to 13.2V
D Rapid Pull–In
D Co–Channel Sync Lockout for NTSC Signals
D I2L Logic

Operating Ambient Temperature Range 0° to +70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage Temperature Range –55° to +150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead Temperature (During Soldering, 1/16” from case, 10sec max) +265°C. . . . . . . . . . . . . . . . . . . .