The NTE7134 is a high performance and efficient solution for autosync monitors in a 32–Lead DIP
type package. The concept is fully DC controllable and can be used in applications with a microcontroller and stand–alone in rock bottom solutions.
This device provides synchronization processing, H + V synchronization with full autosync capability ,
and very short setting times after mode changes. External power components are givena great deal
of protection. The IC generates the drive waveforms for DC–coupled vertical boosters.
The NTE7134 provides ectended functions e.g. as a flexible SMPS block and an extensive set of geometry control facilities, providing excellent picture quality.
Features:
Concept Features
DFull Horizontal (H) Plus Vertical (V) Autosync Capability
DCompletely DC Controllable for Analog and Digital Concepts
DExcellent Geometry Control Functions (e.g. Automatic Correction of East–West (EW) Parabola
During Adjustment of Vertical Size and Vertical Shift)
DFelxible Switched Mode Power Supply (SMPS) Function Block for Feedback and Feed Forward
Converters.
DX–Ray Protection
DStart–Up and Switch–Off Sequences for safe Operation of All Power Components
DVery Good Vertical Linearity
DInternal Supply Voltage Stabilization
Synchronization Inputs
DCan Handle All Sync Signals (Horizontal, Vertical, Composite and Sync–On–Video)
DCombined Output for Video Clamping, Vertical Blanking and Protection Blanking
DStart of Video Clamping Pulses Externally Selectable
Horizontal Section
DExtremely Low Jitter
DFrequency Locked Loop for Smooth Catching of Line Frequrncy
DSimple Frequency Preset of f
DDC Controllable Wdie Range Linear Picture Position
DSoft Start for Horizontal Driver
Vertical Section
DVertical Amplitude Independent of Frequency
DDC Controllable Picture Height, Picture Position and S–Correction
DDifferential Current Outputs for DC Coupling to Vertical Booster
min
and f
by External Resistors
max
Features (Cont’d):
EW Section
DOutput for DC Adjustable EW Parabola
DDC Controllable Picture Width and Trapezium Correction
DOptional Tracking of EW Parabola with Line Frequency
DPrepared for Additional DC Controls of Vertical Linearity, EW–Corner, EW Pin Balance, EW
Parallelogram, Vertical Focus by Extended Application
Absolute Maximum Ratings: (All voltages measured with respect to GND)
Supply Voltage (Pin9), V
Input Voltages, V
Horizontal Driver Output Current, I
Horizontal Flyback Input Current, I
HDRV
HFLB
Video Clamping Pulse/Vertical Blanking Output Current, I
B+ Control OTA Output Current, I
B+ Control Driver Output Current, I
EW Driver Output Current, I
Electrostatic Discharge for All Pins (Note 1), V
Input Characteristics for DC–Coupled TTL Signals [HSYNC (Pin15)]
Sync Input Signal VoltageV
Slicing Voltage Level1.21.41.6V
Rise Time of Sync Pulset
Fall Time of Sync Pulset
Minimum Width of Sync Pulset
Input CurrentI
Input Characteristics for AC–Coupled Video Signals (Sync–on–Video, Negative Sync Polarity)
Sync Amplitude of Video Input Signal
Voltage
Slicing Voltage Level
(Measured from Top Sync)
Top Sync Clamping LevelV
Charge Current for Coupling CapacitorI
Minimum Width of Sync Pulset
Maximum Source ResistanceR
Differential Input Resistancer
Automatic Polarity Correction for Horizontal Sync
Horizontal Sync Pulse Width Related to t
Delay Time for Changing Polarityt
Vertical Sync Integrator
Integration Time for Generation of a
Vertical Trigger Pulse
Vertical Sync Slicer (DC–Coupled, TTL Compatible) [VSYNC (Pin14)]
Sync Input Signal VoltageV
Slicing Voltage Level1.21.41.6V
Input CurrentI
Vertical Sync Output at VSYNC (Pin14) During Composite Sync at HSYNC (Pin15)
Output CurrentI
Internal Clamping Voltage LevelV
Steepness of Slopes–300–ns/mA
Automatic Polarity Correction for Vertical Sync
Maximum Width of Vertical Sync Pulset
Delay for Change Polarityt
Video Clamping/Vertical Blanking Output [CLCB (Pin16)]
Width of Video Clamping Pulset
Temperature Coefficient of V
clamp(CLCB)
Steepness of Slopes for Clamping PulseRL = 1MΩ, CL = 20pF–50–ns/V
Top Voltage Level of Vertical
Blanking Pulse
Width of Vertical Blanking Pulset
H
V
AC(HSYNC)
clamp(HSYNC)
C(HSYNC)
HSYNC(min)
S(max)
diff(HSYNC)
t
p(H)
t
H
p(H)
t
int(V)
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC(max)
d(VPOL)
clamp(CLBL)
TC
clamp
V
blank(CLBL)
blank(CLBL)
–300–mV
RS = 50Ω90120150mV
1.11.281.5V
V
HSYNC
> V
clamp(HSYNC)
1.72.43.4µA
0.7––µs
Duty factor = 7%––1500Ω
During Sync–80–Ω
fH < 45kHz––20%
fH > 45kHz––25&
0.3–1.8ms
fH = 31.45kHz,
I
= 1.052mA
HREF
fH = 64kHz,
I
= 2.141mA
HREF
fH = 100kHz,
I
= 3.345mA
HREF
7.010.013.0µs
3.95.76.5µs
2.53.84.5µs
1.7––V
0V < V
< 5.5V––±10µA
SYNC
During Internal Vertical Sync–0.7–1.0–1.35mA
During Internal Vertical Sync4.44.85.2V
––300µs
0.3–1.8ms
Measured at V
= 3V0.60.70.8µs
CLBL
–+4–mV/K
Note 21.71.92.1V
240300360µs
Note 2. Continuous blanking at CLCB (Pin16) will be activated, if one of the following conditions is true:
a) No horizontal flyback pulse at HFLB (Pin1) within a line
b) X–ray protection is triggered
c) Voltage at HPLL2 (Pin31) is low (for soft start of horizontal drive)
d) Supply voltage at VVV (Pin9) is low
e) PLL1 unlocked while frequency–locked loop is in search mode
Video Clamping/Vertical Blanking Output (Cont’d) [CLCB (Pin16)]
Temperature Coefficient of V
blank(CLBL)
Output Voltage During Vertical ScanV
Temperature Coefficient of V
scan(CLBL)
Internal Sink CurrentI
External Load CurrentI
Selection of Leading/Trailing Edge for Video Clamping Pulse
Voltage at CLSEL (Pin10) for Trigger with
Leading Edge of Horizontal Sync
Voltage at CLSEL (Pin10) for Trigger with
Trailing Edge of Horizontal Sync
Delay Between Leading Edge of
Horizontal Sync and Start of
Horizontal Clamping Pulse
Delay Between Leading Trailing of
Horizontal Sync and Start of
Horizontal Clamping Pulse
Maximum Duration of Video Clamping
Pulse After End of Horizontal Sync
Input Resistance at CLSEL (Pin10)R
PLL1 Phase Comparator and Frequency–Locked Loop [HPLL1 (Pin26) and HBUF (Pin27)]
Maximum Width of Horizontal Sync Pulse
(Referenced to Line Period)
Total Lock–In Time of PLL1t
Control VoltageV
Buffered f/v Voltage at HBUF (Pin27)V
Maximum Load CurrentI
Adjustment of Horizontal Picture Position
Horizontal Shift Adjustment Range
(Referenced to Horizontal Period)
Input CurrentI
TC
blank
scan(CLBL)ICLBL
TC
scan
sink(CLBL)
load(CLBL)
V
CLSEL
t
d(clamp)
V
V
t
clamp(max)
V
V
CLSEL
t
HSYNC(max)fH
V
fH > 45kHz, Note 3––25%
lock(HPLL1)
HPLL1
HBUF
Note 4, Note 5
f
f
load(HBUF)
∆HPOSI
I
HPOS
∆HPOS = +10.5%–110–120–135µA
∆H POS = –10.5%–0–µA
–+2–mV/K
= 00.590.630.67V
––2–mV/K
2.4––mA
–––3.0mA
7–V
0–5V
> 7V–300–ns
CLSEL
< 5V–130–ns
CLSEL
CLBL
CLBL
CLSEL
= 3V, V
= 3V, V
≤ V
CC
> 7V––0.15µs
CLSEL
> 5V––1.0µs
CLSEL
80––kΩ
< 45kHz, Note 2––20&
–4080ms
, Note 6–5.6–V
H(min)
, Note 6–2.5–V
H(max)
–––4.0mA
= 0––10.5–%
HSHIFT
= –135µA–+10.5–%
HSHIFT
CC
V
Note 3. To ensure safe locking of the horizontal oscillator , one of the following procedures is required :
a) Search mode starts always from f
. Then the PLL1 filter components are a 3.3nF
min
capacitor from Pin26 to GND in parallel with an 8.2kΩ resistor in series with a 47nF
capacitor.
b) Search mode starts either from f
min
or f
with HPOS in m iddle position (I
max
HPOS
= 60µA).
Then the PLL1 filter components are a 1.5nF capacitor from Pin26 to GND in parallel
with a 27kΩ resistor in series with a 47nF capacitor.
c) After locking is achieved, HPOS can be operated in the normal way
Note 4. Loading of HPLL1 (Pin26) is not allowed.
Note 5. Oscillator frequency is f
when no sync signal is present (no continuous blanking at Pin16).
min
Note 6. V oltage at HPPL1 (Pin26) is fed to HBUF (Pin27) via a buffer. Disturbances caused by hori-
zontal sync are removed by an internal sample–and–hold circuit.
Slicing Voltage LevelV
Minimum Width of Trigger Pulset
Input Resistance at XRAY (Pin2)R
Supply Voltage for Reset of X–Ray LatchV
XRA Y
W(XRAY)
I(XRA Y)
RESET(VCC)
V
V
XRAY
XRAY
< 6.38V + V
> 6.38V + V
BE
BE
Vertical Oscillator (Oscillator Frequency in Application Without Adjustment of Free–Running Frequency f
Free–Running Frequencyf
Vertical Frequency Catching Rangef
V
v(o)
R
= 22kΩ,
VREF
C
= 100nF
VCAP
Constant Amplitude, Note 8,
Note 9, Note 10
Voltage at Reference Input for
V
VREF
Vertical Oscillator
Delay Between Trigger Pulsed and Start
t
d(scan)
of Ramp at VCAP (Pin24) (Width of
Vertical Blanking Pulse)
Control Currents of Amplitude ControlI
External Capacitor at VAGC (Pin22)C
VAGC
VAGC
Differential Vertical Current Outputs
Adjustment of Vertical Size [VAMP (Pin18)]
Vertical Size Adjustment Range
(Referenced to Nominal Vertical Size)
Input Current for Max Amplitude (100%)I
∆VAMPI
VAMP
= 0, Note 11–60–%
VAMP
I
= –135µA, Note 11–100–%
VAMP
Input Current for Min Amplitude (60%)–0–µA
Reference Voltage at InputV
ref(V AMP)
Adjustment of Vertical Shift [VPOS (Pin17)]
Vertical Shift Adjustment Range
(Referenced to 100% Vertical Size)
Input Current for Max Shift–UpI
∆VPOSI
VPOS
= –135µA, Note 11––11.5–%
VPOS
I
= 0, Note 11–+11.5–%
VPOS
Input Current for Max Shift–Down–0–µA
Reference Voltage at InputV
Vertical Shift is Centered of VPOS (Pin17)
ref(VPOS)
V
off(VPOS)
is Forced to GND
6.146.386.64V
10–µs
500––kΩ
–5–kΩ
–5.6–V
)
v(o)
40.042.043.3Hz
50–110Hz
–3.0–V
240300360µs
±120±200±300µA
––150nF
–110–120–135µA
–5.0–V
–110–120–135µA
–5.0–V
0–0.1V
Note 8. Full vertical sync range with constant amplitude (f
V(min)
: f
V(max)
= 1 : 2.5) can be made by
chosing an application with adjustment of free–running frequency.
Note 9. If higher vertical frequencies are reqiured, sync range can be shifted by using a smaller
capacitor at VCAP (Pin24).
Note10. Value of resistor at VREF (Pin23) may not be changed.
Note11. All vertical and EW adjustments are specified at nominal vertical settings, which means:
a) ∆VAMP = 100% (I
VAMP
= 135µA
b) ∆VSCOR = 0 (Pin19 Open–Circuit)
c) ∆VPOS centered (Pin17 forced to GND)
d) fH = 70kHz
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