NTE NTE3880 Datasheet
NTE3880
Integrated Circuit
NMOS, 8–Bit Microprocessor (MPU), 4MHz
Description:
The NTE3880 is a third generation single chip microprocessor with unrivaled computational power.
This increased computational power results in higher system through–put and more efficient memory
utilization when compared to second generation microprocessors. In addition it is very easy to implement into a system because of it’ s single voltage requirement plus all output signals are fully decoded
and timed to control standard memory or peripheral circuits. The circuit is implemented using an N–
channel, ion implanted, silicon gate MOS process.
This device has an internal register configuration which contains 208 bits of Read/Write memory that
are accessible to the programmer. The registers include two sets of six general purpose registers that
may be used individually as 8–bit registers or as 16–bit register pairs. There are also two sets of accumulator and flag registers. The programmer has access to either set of main or alternate registers
through a group of exchange instructions. This alternate set allows foreground/background mode of
operation or may be reserved for very fast interrupt response. The NTE3880 also contains a 16–bit
stack pointer which permits simple implementation of multiple level interrupts, unlimited subroutine
nesting and simplification of many types of data handling.
The two 16–bit index registers allow tabular data manipulation and easy implementation of relocatable code. The Refresh register provides for automatic, totally transparent refresh of external dynamic memories. The I register is used in a powerful interrupt response mode to form the upper 8 bits of
a pointer to a interrupt service address table, while the interrupting device supplies the lower 8 bits
of the pointer. An indirect call is then made to this service address.
Features:
D Single Chip, N–Channel Silicon Gate
D 158 Instructions – Includes all 78 of the 8080A Instructions with T otal Software Compatibility. N e w
Instructions Include 4–, 8– and 16–Bit Operations with more useful Addressing Modes such as
Indexed, Bit and Relative
D 17 Internal Registers
D Three Modes of Fast Interrupt Response plus a Non–Maskable Interrupt
D Directly Interfaces Standard Speed Static or Dynamic Memories with Virtually No External Logic
D 1.0µs Instruction Execution Speed
D Single 5VDC Supply and Single–Phase 5V Clock
D Out–Performs any other Single–Phase 5V Clock
D All Pins TTL Compatible
D Built–In Dynamic RAM Refresh Circuitry
Absolute Maximum Ratings:
Temperature Under Bias 0° to +70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature Range –65° to +150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage On Any Pin With Respect to GND –0.3V to +7V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation 1.5W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Note 1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only functional operation of the device at these
or any other condition above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
DC Characteristics: (TA = 0° to 70°C, VCC = 5V ±5% unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
Clock Input Low Voltage V
Clock Input High Voltage V
Input Low Voltage V
Input High Voltage V
Output Low Voltage V
Output High Voltage V
Power Supply Current I
Input Leakage Current I
Tri–State Output Leakage Current in Float I
Tri–State Output Leakage Current in Float I
Data Bus Leakage Current in Input Mode I
ILC
IHC
IL
IH
OL
OH
CC
L1
LOH
LOL
LD
IOL = 1.8mA – – 0.4 V
IOH = –250µA 2.4 – – V
VIN = 0 to V
V
OUT
V
OUT
0 ≤ VIN ≤ V
CC
= 2.4 to V
CC
= 0.4V – – –10 µA
CC
–0.3 – 0.80 V
VCC–0.6 – VCC+3 V
–0.3 – 0.8 V
2.0 – V
CC
– 90 200 mA
– – 10 µA
– – 10 µA
– – ±10 µA
V
Capacitance: (TA = +25°C, f = 1MHz, unmeasured pins to GND unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
Clock Capacitance C
Input Capacitance C
Output Capacitance C
φ
IN
OUT
– – 35 pF
– – 5 pF
– – 10 pF
AC Characteristics: (TA = 0°C to +70°C, VCC = +15V ± 5% unless otherwise specified)
Parameter Symbol Signal Test Conditions Min Typ Max Unit
Clock Period t
c
Clock Pulse Width, Clock High tw (φH)
Clock Pulse Width, Clock Low tw (φL) 110 – 2000 ns
Clock Rise and Fall Time tr, t
f
Address Output Delay tD (AD) A
Data to Float tF (AD) – – 90 ns
Address Stable Prior to MRFQ (Memory Cycle) t
Address Stable Prior to IOFQ, RD or WR (I/O Cycle) t
Address Stable from RD, WR, IORQ, or MREQ t
Address Stable from RD or WR During Float t
Note 2. tc = t
(φH) + t
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(φL) + tr + tf.
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acm
aci
ca
caf
Note 3. Although static by design, testing guarantees t
Note 4. t
Note 5. t
Note 6. tca = t
Note 7. t
= t
acm
= tc–70.
aci
= t
caf
(φH) + tf–65.
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(φL) + tr–50.
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(φL) + tr–45.
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φ 25 – Note 2 µs
110 – Note 3 ns
– – 30 ns
0–15CL
= 50pF – – 110 ns
Note 4 – – ns
Note 5 – – ns
Note 6 – – ns
Note 7 – – ns
(φH) of 200µs maximum.
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