NTE NTE3093 Datasheet

NTE3093

Optoisolator

NPN Split Darlington Output

Description:

The NTE3093 coupler uses a light emitting diode (LED) and an integrated high gain photon detector
to provide 3000V DC electrical insulation, 500V/µs common mode transient immunity and extremely
high current transfer ratio between inut and output. Separate pins for the photodiode and output stage
result in TTL compatible saturation voltages and high speed operation. Where desired, the V

terminals may be tied together to achieve conventional photodarlington operation. A base access

V

O

terminal allows a gain bandwidth adjustment to be made.

Features:

D High Current Transfer Ratio
D Low Input Current Requirement
D TTL Compatible Output
D 3000V DC Withstand Test Voltage
D High Common Mode Rejection
D Base Access Allows Gain Bandwidth Adjustment
D High Output Current
D DC to 1Mbit/s Operation

CC

and

Absolute Maximum Ratings:

(TA = +25°C unless otherwise specified)

Input Diode

Reverse Voltage, V
Peak Current (50% Duty Cycle,1ms Pulse Width), I

R

F

Peak Transient Current (≤ 1µs Pulse Width, 300pps), I
Power Dissipation, P

D

F

5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

40mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

20mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

35mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Derate Linearly Above 50°C 0.7mW/°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Transistor

Current (Pin6), I

O

60mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Derate Linearly Above 25°C 0.7mA/°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Emitter–Base Reverse Voltage (Pin5–7) 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply Voltage (Pin8–5), V
Output Voltage (Pin6–5), V
Power Dissipation, P

D

CC
O

–0.5 to 18V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–0.5 to 18V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

35mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Derate Linearly Above 50°C 0.7mW/°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Total Device

Operating Temperature Range, T
Storage Temperature Range, T

opr

stg

Lead Temperature (During Soldering, 1.6mm below seating plane, 10sec Max), T

L

0° to +70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–55° to +125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

+260°C. . . . . .

Note 1. The sm all j un cti on si zes i nherent to the design of this bipolar component increases the

component’s susceptibility to damage from electrostatic discharge (ESD). It is advised
that n ormal static p recautions b e taken i n h andling and a ssembly o f this c omponent t o pre­vent damage and/or degredation which may be induced by ESD.

Electrical Characteristics: (TA = 0° to +70°C, Note 2 unless otherwise specified)

Parameter Symbol Test Conditions Min Typ Max Unit

Current Transfer Ratio CTR IF = 0.5mA, VO = 0.4V, VCC = 4.5V, Note 3, Note 4 400 800 – %

IF = 1.6mA, VO = 0.4V, VCC = 4.5V, Note 3, Note 4 500 900 – %

Logic Low Output Voltage V

Logic High Output Current I
Logic Low Supply Current I
Logic High Supply Current I
Input Forward Voltage V
Input Reverse Breakdown

Voltage

Temperature Coefficient

of Forward Voltage
Input Capacitance C
Input–Output Insulation

Leakage Currnt
Resistance R
Capacitance C

CCHIF

V

(BR)RIF

∆V
∆T

OLIF

OH

CCLIF

F

F
A

IN

I

IO

IO
IO

= 1.6mA, IO = 6.4mA, VCC = 4.5V, Note 4 – 0.1 0.4 V
IF = 5mA, IO = 15mA, VCC = 4.5V, Note 4 – 0.1 0.4 V
IF = 12mA, IO = 24mA, VCC = 4.5V, Note 4 – 0.2 0.4 V
IF = 0, VO = VCC = 18V, Note 4 – 0.05 100 µA

= 1.6mA, VO = Open, VCC = 5V, Note 4 – 0.2 – mA

= 0mA, VO = Open, VCC = 5V, Note 4 – 10 – nA
IF = 1.6mA, TA = +25°C – 1.4 1.7 V

= 10µA, TA = +25°C 5 – – V

IF = 1.6mA – –1.8 – mV/°C

f = 1MHz, VF = 0 – 60 – pF
45% Relative Humidity, TA = +25°C, t = 5s,

V

= 3KVdc, Note 5

IO

VIO = 500Vdc, Note 5 – 10
f = 1MHz, Note 5 – 0.6 – pF

– – 1.0 µA

11

– Ω

Note 2. All typicals at TA = +25°C, VCC = 5V unless otherwise specified.
Note 3. DC Current Transfer Ratio is defined as the ratio of output collector current (I

LED input current (I

) times 100%.

F

) to the forward

O

Note 4. Pin7 Open.
Note 5. Device considered a two–terminal device (Pins 1, 2, 3 and 4 shorted together and Pins 5,

6, 7 and 8 shorted together).

Switching Characteristics:

Parameter Symbol Test Conditions Min Typ Max Unit

Propagation Delay Time

Common Mode Transient Immunity CM

(TA = +25°C unless otherwise specified)

t

PHLIF

t

PLH

CMLIF = 1.6mA, RL = 2.2kΩ, RCC = 0,

= 0.5mA, RL = 4.7kΩ, Note 3, Note 6 – 5 25 µs
IF = 12mA, RL = 270Ω, Note 3, Note 6 – 0.2 1.0 µs
IF = 0.5mA, RL = 4.7kΩ, Note 3, Note 6 – 5 60 µs
IF = 12mA, RL = 270Ω, Note 3, Note 6 – 1 7 µs

= 0, RL = 2.2kΩ, RCC = 0,

HIF

|V

|V

CM

CM

| = 10V

| = 10V

, Note 7, Note 8

P–P

, Note 7, Note 8

P–P

– 500 – V/µs

– –500 – V/µs

Note 3. DC Current Transfer Ratio is defined as the ratio of output collector current (IO) to the forward

LED input current (I

) times 100%.

F

Note 6. Use of a resistor between Pin5 and Pin7 will decrease gain abd delay time.
Note 7. Common mode transient immunity in Logic High level is the maximum tolerable (positive)

dv cm/dt on the leading edge of the common mode pulse (V
remain in a Logic High state (i.e. V

2.0V). Common mode transient immunity in Logic Low

O

) to assure that the output will

CM

level is the maximum tolerable (negative) dc cm/dt on the trailing edge of the common mode
pulse signal (V

) to assure that the output will remain in a Logic Low state (i.e. VO 0.8V).

CM

Note 8. In applications where dV/dt may exceed 50,000V/µs (such as static discharge) a series re-

sistor (R

) should be included to protect the detector IC from destructively high surge cur-

CC

rents. The recommended value is:

R

CC

=

0.15 I

1V

F

(mA)

kΩ