NTE NTE21256 Datasheet
NTE21256
262,144–Bit Dynamic Random
Access Memory (DRAM)
Description:
The N TE21256 i s a 262,144 w ord b y 1 –bit d ynamic R andom A ccess M emory. This 5 V–only c omponent
is fabricated with N–channel silicon gate technology.
Nine multiplexed address inputs permit the NTE21256 to be packaged in an industry standard
16–Lead DIP package. Features of this device include single power supply with ±10% tolerance, on–
chip address, date registers which eliminate the need for interface registers, and fully TTL compatible
inputs and outputs, including clocks.
In addition to the usual read, write, and read–modify–write cycles, the NTE21256 is capable of early
and late write cycles, RAS
early write operation.
The NTE21256 also features page mode which allows high–speed random access of bits in the same
row.
Features:
D 262,144 x 1–Bit Organization
D Single +5V Supply, ±10% Tolerance
D Low Power Dissipation:
–385mW active (Max)
–28mW standby (Max)
D Access Time: 150ns
D Cycle Time: 260ns
D All Inputs and Outputs TTL Compatible
D On–Chip Substrate Bias Generator
D Three–State Data Output
D Read, Write, Read–Modify–Write, RAS
D Common I/O Capability using “Early Write” Operation
D Page Mode Read and Write, Read–Write
D 256 Refresh Cycles with 4ms Refresh Period
–only refresh, and hidden refresh. Common I/O capability is given by using
–Only–Refresh, Hidden Refresh
Absolute Maximum Ratings:
Operating Temperature Range, T
Storage Temperature Range, T
Voltage on any pin relative to V
Power Dissipation, P
Data Out Current (Short Circuit) 50mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Note 1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to t he device. E xposure t o a bsolute m aximum r ating c onditions for extended p eriods
may affect device reliability.
D
(Note 1)
opr
stg
SS
0° to +70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65° to +150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–1 to +7V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description:
Device Initialization
Since the NTE21256 is a dynamic RAM with a single +5V supply, no power sequencing is required.
For power–up, an initial pause of 200µs is necessary for the internal bias generator to establish the
proper substrate bias voltage. To initialize the nodes of the dynamic circuitry, a minimum of 8 active
cycles of the Row Address Strobe (RAS
) has to be performed. This is also necessary after an ex-
tended inactive state of greater than 4ms.
Addressing (A0–A8)
For selecting one of the 262,144 memory cells, a total of 18 address bits are required. First 8 Row
Address bits are set up on pins A0 through A8 and latched into the row address latches by the Row
Address Strobe (RAS
into the column address latches by the Column Address Strobe (CAS
stable on the falling edges of RAS
in that it activates the sense amplifiers as well as the row decoder. C A S
). Then the 9 column address bits are set up on pins A0 through A8 and latched
). All input addresses must be
and CAS. It should be noted that RAS is similar to a Chip Enable
is used as a chip select acti-
vating the column decoder and the input and output buffers.
Write Enable (WE
The read or write mode is selected with the WE
mode; logic low (V
When WE
goes low prior to CAS, data output (DO) will remain in the high–impedance state for the
)
input. A logic high (VIH) on WE dictates read
) dictates write mode. The data input is disabled when read mode is selected.
IL
entire cycle permitting common I/O operation.
Data Input (DI)
Data is written during a write or read–modify–write cycle. The falling edge of CAS
into the on–chip data latch. In an early write cycle, WE
strobed in by CAS
with setup and hold times referenced to this signal.
is brought low prior to CAS and the data is
or WE strobes data
Data Output (DO)
The output is three–state TTL compatible with a fan–out of two standard TTL loads. Data Out has
the same polarity as Data In. The output is in a high impedance state until CAS
a read cycle or read–write cycle, the output is valid after t
is satisfied, or after t
from transition of CAS when the transition occurs after t
CAC
from transition of RAS when t
RAC
is brought low. In
RCD
(Max). In an early
RCD
(Min)
write cycle, the output is always in the high impedance state. In a delayed write or read–modify–write
cycle, the output will follow the sequence for the read cycle. With CAS
to the high impedance state within t
OFF
.
going high the output returns
Hidden Refresh
RAS
–only refresh cycle may take place while maintaining valid output data. This feature is referred
to as Hidden Refresh. Hidden Refresh is performed by holding CAS
at VIL of a previous memory read
cycle.
Refresh Cycle
A refresh operation must be performed at least every 4ms to retain data. Since the output buffer is
in the high impedance state unless CAS
during refresh. Strobing each of the 256 row addresses (A0 through A7) with RAS
in each row to be refreshed. CAS
is applied, the RAS–only refresh sequence avoids any signal
, causes all bits
can remain high (inactive) for this refresh sequence to conserve
power.
Page Mode
Page–mode operation allows effectively faster memory access by maintaining the row address and
strobing random column addresses onto the chip. Thus, the time necessary to setup and strobe sequential row addresses for the same page is no longer required. The maximum number of columns
that can be addressed in sequence is determined by t
, the maximum RAS low pulse width.
RAS
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