NSC MM54C14J-883 Datasheet
TL/F/5879
MM54C14/MM74C14 Hex Schmitt Trigger
February 1988
MM54C14/MM74C14 Hex Schmitt Trigger
General Description
The MM54C14/MM74C14 Hex Schmitt Trigger is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement transistors.
The positive and negative going threshold voltages, V
T
a
and V
T
b
, show low variation with respect to temperature
(typ. 0.0005V/
§
CatV
CC
e
10V), and hysteresis,
V
T
a
b
V
T
b
t
0.2 VCCis guaranteed.
All inputs are protected from damage due to static discharge by diode clamps to V
CC
and GND.
Features
Y
Wide supply voltage range 3.0V to 15V
Y
High noise immunity 0.70 VCC(typ.)
Y
Low power 0.4 VCC(typ.)
TTL compatibility 0.2 V
CC
guaranteed
Y
Hysteresis 0.4 VCC(typ.)
0.2 V
CC
guaranteed
Connection Diagram
Dual-In-Line Package
TL/F/5879– 1
Top View
Order Number MM54C14 or MM74C14
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at Any Pin
b
0.3V to V
CC
a
0.3V
Operating Temperature Range
MM54C14
b
55§Ctoa125§C
MM74C14
b
40§Ctoa85§C
Storage Temperature Range
b
65§Ctoa150§C
Power Dissipation
Dual-In-Line 700 mW
Small Outline 500 mW
Operating V
CC
Range 3.0V to 15V
Absolute Maximum V
CC
18V
Lead Temperature
(Soldering, 10 seconds) 260
§
C
DC Electrical Characteristics
Min/Max limits apply across the guaranteed temperature range unless otherwise noted
Symbol Parameter Conditions Min Typ Max Units
CMOS TO CMOS
V
T
a
Positive Going Threshold Voltage V
CC
e
5V 3.0 3.6 4.3 V
V
CC
e
10V 6.0 6.8 8.6 V
V
CC
e
15V 9.0 10.0 12.9 V
V
T
b
Negative Going Threshold Voltage V
CC
e
5V 0.7 1.4 2.0 V
V
CC
e
10V 1.4 3.2 4.0 V
V
CC
e
15V 2.1 5.0 6.0 V
V
T
a
–V
T
b
Hysteresis V
CC
e
5V 1.0 2.2 3.6 V
V
CC
e
10V 2.0 3.6 7.2 V
V
CC
e
15V 3.0 5.0 10.8 V
V
OUT(1)
Logical ‘‘1’’ Output Voltage V
CC
e
5V, I
O
eb
10 mA 4.5 V
V
CC
e
10V, I
O
eb
10 mA 9.0 V
V
OUT(0)
Logical ‘‘0’’ Output Voltage V
CC
e
5V, I
O
e
10 mA 0.5 V
V
CC
e
10V, I
O
e
10 mA 1.0 V
I
IN(1)
Logical ‘‘1’’ Input Current V
CC
e
15V, V
IN
e
15V 0.005 1.0 mA
I
IN(0)
Logical ‘‘0’’ Input Current V
CC
e
15V, V
IN
e
0V
b
1.0
b
0.005 mA
I
CC
Supply Current V
CC
e
15V, V
IN
e
0V/15V 0.05 15 mA
V
CC
e
5V, V
IN
e
2.5V (Note 4) 20 mA
V
CC
e
10V, V
IN
e
5V (Note 4) 200 mA
V
CC
e
15V, V
IN
e
7.5V (Note 4) 600 mA
CMOS/LPTTL INTERFACE
V
IN(1)
Logical ‘‘1’’ Input Voltage V
CC
e
5V 4.3 V
V
IN(0)
Logical ‘‘0’’ Input Voltage V
CC
e
5V 0.7 V
V
OUT(1)
Logical ‘‘1’’ Output Voltage 54C, V
CC
e
4.5V, I
O
eb
360 mA 2.4 V
74C, V
CC
e
4.75V, I
O
eb
360 mA 2.4 V
V
OUT(0)
Logical ‘‘0’’ Output Voltage 54C, V
CC
e
4.5V, I
O
e
360 mA 0.4 V
74C, V
CC
e
4.75V, I
O
e
360 mA 0.4 V
OUTPUT DRIVE (see 54C/74C Family Characteristics Data Sheet) T
A
e
25§C (Short Circuit Current)
I
SOURCE
Output Source Current V
CC
e
5V, V
OUT
e
0V
b
1.75
b
3.3 mA
(P-Channel)
I
SOURCE
Output Source Current V
CC
e
10V, V
OUT
e
0V
b
8.0
b
15 mA
(P-Channel)
I
SINK
Output Sink Current V
CC
e
5V, V
OUT
e
V
CC
1.75 3.6 mA
(N-Channel)
I
SINK
Output Sink Current V
CC
e
10V, V
OUT
e
V
CC
8.0 16 mA
(N-Channel)
2
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