NSC MM5483V, MM5483N Datasheet

MM5483 Liquid Crystal Display Driver

Y

General Description

The MM5483 is a monolithic integrated circuit utilizing
CMOS metal-gate low-threshold enhancement mode devic­es. It is available in a 40-pin molded package. The chip can
drive up to 31 segments of LCD and can be cascaded to
increase this number. This chip is capable of driving a 4(/2­digit 7-segment display with minimal interface between the
display and the data source.

The MM5483 stores the display data in latches after it is
latched in, and holds the data until another load pulse is
received

Features

Y

Serial data input

Y

Serial data output

Block and Connection Diagrams

Wide power supply operation

Y

TTL compatibility

Y

31 segment outputs

Y

Alphanumeric and bar graph capability

Y

Cascade capability

Applications

Y

COPSTMor microprocessor displays

Y

Industrial control indicator

Y

Digital clock, thermometer, counter, voltmeter

Y

Instrumentation readouts

Y

Remote displays

MM5483 Liquid Crystal Display Driver

February 1995

Dual-In-Line Package

FIGURE 1

TL/F/6140– 1

Top View

TL/F/6140– 2

FIGURE 2

Order Number MM5483MS or MM5483N

See SSOP Package Number MS40A

See NS Package Number N40A

Order Number MM5483V

TL/F/6140– 7

See NS Package Number V44A

COPSTMis a trademark of National Semiconductor Corporation.

C

1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

TL/F/6140

Absolute Maximum Ratings

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Voltage at Any Pin V

Operating Temperature

Storage Temperature

SS

b

b

a

to V

10V

SS

40§Ctoa85§C

65§Ctoa150§C

Power Dissipation 300 mW at

350 mW at

Junction Temperature

Lead Temperature

(Soldering, 10 seconds) 300

a

a

85§C

a

25§C

150§C

C

§

DC Electrical Characteristics

TAwithin operating range, V

DD

e

3.0V to 10V, V

Parameter Conditions Min Typ Max Units

Power Supply 3.0 10 V

Power Supply Current Re1M, Ce470 pF,

Outputs Open

e

V

DD

e

V

DD

e

V

DD

OSCe0V, Outputs Open,

e

BPIN

Input Voltage Levels Load, Clock, Data

Logic ‘‘0’’ V
Logic ‘‘1’’ V
Logic ‘‘0’’ V
Logic ‘‘1’’ V

DD

DD

DD

DD

e
e
e
e

Output Current Levels
Segments and Data Out

Sink V
Source V

DD

DD

e
e

BP OUT

Sink V
Source V

DD

DD

e
e

AC Electrical Characteristics V

Symbol Parameter Min Typ Max Units

f

C

t

CH

t

CL

t

DS

t

DH

t

LW

t

LTC

t

CDO

Note 1: AC input waveform specification for test purpose: t

Note 2: Clock input rise and fall times must not exceed 300 ns.

Note 3: Output offset voltage is

Clock Frequency, V

DD

Clock Period High (Notes 1, 2) 500 ns

Clock Period Low 500 ns

Data Set-Up before Clock 300 ns

Data Hold Time after Clock 100 ns

Minimum Load Pulse Width 500 ns

Load to Clock 400 ns

Clock to Data Valid 400 750 ns

g

50 mV with C

SEGMENT

e

0V, unless otherwise specified

SS

3.0V 9 15 mA

5.0V 17 25 mA

10.0V 35 45 mA

32 Hz, V

e

3.0V 1.5 2.5 m A

DD

5.0V 0.9 V

5.0V 2.4 V

3.0V 0.4 V

3.0V 2.0 V

3.0V, V

3.0V, V

3.0V, V

3.0V, V

e

e

e

0.3V 20 mA

OUT

e

2.7V 20 mA

OUT

e

0.3V 320 mA

OUT

e

2.7V 320 mA

OUT

DD

t

4.7V, V

e

0V unless otherwise specified

SS

3V 500 kHz

s

s

20 ns, t

r

250 pF, C

20 ns, fe500 kHz, 50%g10% duty cycle.

f

e

8750 pF.

BP

Functional Description

A block diagram for the MM5483 is shown in
package pinout is shown in

Figure 2.Figure 3

sible 3-wire connection system with a typical signal format
for

Figure 3

. Shown in

Figure 4

, the load input is an asyn­chronous input and lets data through from the shift register
to the output buffers any time it is high. The load input can
be connected to V

5

. In the 2-wire control mode, 31 bits (or less depending on

for 2-wire control as shown in

DD

Figure 1

and a

shows a pos-

Figure

the number of segments used) of data are clocked into the
MM5483 in a short time frame (with less than 0.1 second
there probably will be no noticeable flicker) with no more
clocks until new information is to be displayed. If data was
slowly clocked in, it can be seen to ‘‘walk’’ across the dis­play in the 2-wire mode. An AC timing diagram can be seen
in

Figure 6

. It should be noted that data out is not a TTL-

compatible output.

2