NSC LP339N, LP339MX, LP339M Datasheet
LP339
Ultra-Low Power Quad Comparator
General Description
The LP339 consists of four independent voltage comparators designed specifically to operate from a single power
supply and draw typically 60 µA of power supply drain current over a wide range of power supply voltages. Operation
from split supplies is also possible and the ultra-low power
supply drain current is independent of the power supplyvoltage. These comparators also feature a common-mode
range which includes ground, even when operated from a
single supply.
Applications include limit comparators, simple
analog-to-digital converters, pulse, square and time delay
generators; VCO’s; multivibrators; high voltage logic gates.
The LP339 was specifically designed to interface with the
CMOS logic family. The ultra-low supply current makes the
LP339 valuable in battery powered applications.
Advantages
n Ultra-low power supply drain suitable for battery
applications
n Single supply operation
n Sensing at ground
n Compatible with CMOS logic family
n Pin-out identical to LM339
Features
n Ultra-low power supply current drain
(60 µA) —independent of the supply voltage
(75 µW/comparator at +5 V
DC
)
n Low input biasing current: 3 nA
n Low input offset current:
±
0.5 nA
n Low input offset voltage:
±
2mV
n Input common-mode voltage includes ground
n Output voltage compatible with MOS and CMOS logic
n High output sink current capability (30 mA at V
O
=
2V
DC
)
n Supply Input protected against reverse voltages
Schematic and Connection Diagrams
Typical Applications
(V
+
=
5.0 V
DC
)
DS005226-1
DS005226-2
Order Number LP339M for S.O. Package
See NS Package Number M14A
Order Number LP339N for Dual-In-Line Package
See NS Package Number N14A
Basic Comparator
DS005226-3
Driving CMOS
DS005226-4
September 1999
LP339 Ultra-Low Power Quad Comparator
© 1999 National Semiconductor Corporation DS005226 www.national.com
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage 36 V
DC
or±18 V
DC
Differential Input Voltage
±
36 V
DC
Input Voltage −0.3 VDCto 36 V
DC
Power Dissipation (Note 2)
Molded DIP 570 mW
Output Short Circuit to GND (Note 3) Continuous
Input Current V
IN
<
−0.3 VDC(Note 4) 50 mA
Operating Temperature Range 0˚C to +70˚C
Storage Temperature Range −65˚ to +150˚C
Soldering Information:
Dual-In-Line Package (10 sec.) +260˚C
S.O. Package:
Vapor Phase (60 sec.) +215˚C
Infrared (15 sec.) +220˚C
See AN-450 “Surface Mounting Methods and Their Effect on
Product Reliability” for other methods of soldering surface
mount devices.
Electrical Characteristics
(V+=5VDC) (Note 5)
Parameter Conditions Min Typ Max Units
Input Offset Voltage T
A
=
25˚C (Note 10)
±
2
±
5mV
DC
Input Bias Current IIN(+) or IIN(−) with the 2.5 25 nA
DC
Output in the Linear Range, T
A
=
25˚C (Note 6)
Input Offset Current I
IN
(+)−IIN(−), T
A
=
25˚C
±
0.5
±
5nA
DC
Input Common T
A
=
25˚C (Note 7) 0 V+−1.5 V
DC
Mode Voltage Range
Supply Current R
L
=
Infinite on all Comparators, T
A
=
25˚C 60 100 µA
DC
Voltage Gain V
O
=
1V
DC
to 11 VDC, 500 V/mV
R
L
=
15 kΩ,V
+
=
15 V
DC,TA
=
25˚C
Large Signal V
IN
=
TTL Logic Swing, V
REF
=
1.4 V
DC
, 1.3 µSec
Response Time V
RL
=
5V
DC,RL
=
5.1 kΩ,T
A
=
25˚C
Response Time V
RL
=
5V
DC,RL
=
5.1 kΩ,T
A
=
25˚C (Note 8) 8 µSec
Output Sink Current V
IN
(−)=1VDC,VIN(+)=0, V
O
=
2V
DC
,1530mA
DC
T
A
=
25˚C (Note 12)
V
O
=
0.4 V
DC
0.20 0.70 mA
DC
Output Leakage Current VIN(+)=1VDC,VIN(−)=0, V
O
=
5V
DC,TA
=
25˚C 0.1 nA
DC
Input Offset Voltage (Note 10)
±
9mV
DC
Input Offset Current IIN(+)−IIN(−)
±
1
±
15 nA
DC
Input Bias Current IIN(+) or IIN(−) with Output in Linear Range 4 40 nA
DC
Input Common Single Supply 0 V+−2.0 V
DC
Mode Voltage Range
Output Sink Current V
IN
(−)=1VDC,VIN(+)=0, V
O
=
2V
DC
10 mA
DC
Output Leakage Current VIN(+)=1VDC,VIN(−)=0, V
O
=
30 V
DC
1.0 µA
DC
Differential Input Voltage All V
IN’s
≥0VDC(or V−on split supplies) (Note 9) 36 V
DC
Note 1: Absolute Maximum Ratings indicate limits beyond whichdamage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits.
Note 2: For elevated temperature operation, T
j
max is 125˚C for the LP339. θja(junction to ambient) is 175˚C/W for the LP339N and 120˚C/W for the LP339M when
either device is soldered in a printed circuit board in a still air environment. The low bias dissipation and the “ON-OFF” characteristic of the outputs keeps the chip
dissipation very small (P
D
≤ 100 mW), provided the output transistors are allowed to saturate.
Note 3: Short circuits from the output to V
+
can cause excessive heating and eventual destruction. The maximum output current is approximately 50 mA.
Note 4: This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of the input PNP transistors becoming forward biased and thereby acting as input clamp diodes. In addition to this diode action, there is also lateral NPN parasitic transistor action on the
IC chip. This transistor action can cause the output voltage of the comparators to go to the V+ voltage level (or to ground for a large input overdrive) for the time duration that an input is driven negative. This is not destructive and normal output states will re-establish when the input voltage, which is negative, again returns to a
value greater than −0.3 V
DC(TA
=
25˚C).
Note 5: These specifications apply for V
+
=
5V
DC
and 0˚C≤TA≤70˚ C, unless otherwise stated. The temperature extremes are guaranteed but not 100%production
tested. These parameters are not used to calculate outgoing AQL.
Note 6: The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the state of the output, so
no loading change exists on the reference or the input lines as long as the common-mode range is not exceeded.
Note 7: The input common-mode voltage or either input voltage should not be allowed to go negative by more than 0.3V. The upper end of the common-mode volt-
age range is V
+
−1.5V (T
A
=
25˚C), but either or both inputs can go to 30 V
DC
without damage.
Note 8: The response time specified is for a 100 mV input step with 5 mV overdrive. For larger overdrive signals 1.3 µs can be obtained. See Typical Performance
Characteristics section.
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Electrical Characteristics (Continued)
Note 9: Positive excursions of input voltage may exceed the power supply level. As long as the other voltage remains within the common-mode range, the compara-
tor will provide a proper output state. The low input voltage state must not be less than −0.3 V
DC
(or 0.3 VDCbelow the magnitude of the negative power supply, if
used) at T
A
=
25˚C.
Note 10: At output switch point, V
O
=
1.4V, R
S
=
0Ω with V
+
from 5 VDC; and over the full input common-mode range (0 VDCto V+−1.5 VDC).
Note 11: For input signals that exceed V
+
, only the overdriven comparator is affected.With a 5V supply,VINshould be limited to 25V maximum, and a limiting resistor
should be used on all inputs that might exceed the positive supply.
Note 12: The output sink current is a function of the output voltage. The LP339 has a bi-modal output section which allows it to sink large currents via a Darlington
connection at output voltages greater than approximately 1.5 V
DC
and sink lower currents below this point. (See typical characteristics section and applications sec-
tion).
Typical Performance Characteristics
Supply Current
DS005226-35
Input Current
DS005226-36
Output Sink Current
DS005226-37
Output Sink Current
DS005226-38
Response Times for
Various Input
Overdrives —
Negative Transition
DS005226-39
Response Times for
Various Input
Overdrives —
Positive Transition
DS005226-40
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Application Hints
All pins of any unused comparators should be tied to the
negative supply.
The bias network of the LP339 establishes a drain current
which is independent of the magnitude of the power supply
voltage over the range of from 2 V
DC
to 30 VDC.
It is usually unnecessary to use a bypass capacitor across
the power supply line.
The differential input voltage may be larger than V+ without
damaging the device. Protection should be provided to prevent the input voltages from going negative more than −0.3
V
DC
(at 25˚C). An input clamp diode can be used as shown
in the application section.
The output section of the LP339 has two distinct modes of
operation-a Darlington mode and a grounded emitter mode.
This unique drive circuit permits the LP339 to sink 30 mA at
V
O
=
2V
DC
(Darlington mode) and 700 µA at V
O
=
0.4 V
DC
(grounded emitter mode).
Figure 1
is a simplified schematic
diagram of the LP339 output section.
Notice that the output section is configured in a Darlington
connection (ignoring Q3). Therefore, if the output voltage is
held high enough (V
O
≥1VDC), Q1 is not saturated and the
output current is limited only by the product of the betas of
Q1, Q2 and I1 (and the 60Ω R
SAT
of Q2). The LP339 is thus
capable of driving LED’s, relays, etc. in this mode while
maintaining an ultra-low power supply current of typically
60 µA.
If transistor Q3 were omitted, and the output voltage allowed
to drop below about 0.8 V
DC
, transistor Q1 would saturate
and the output current would drop to zero. The circuit would,
therefore, be unable to “pull” low current loads down to
ground (or the negative supply, if used). Transistor Q3 has
been included to bypass transistor Q1 under these conditions and apply the current I1 directly to the base of Q2. The
output sink current is now approximately I1 times the beta of
Q2 (700 µA at V
O
=
0.4 V
DC
). The output of the LP339 exhibits a bi-modal characteristic with a smooth transition between modes. (See Output Sink Current graphs in Typical
Performance Characteristics section.)
It is also important to note that in both cases the output is an
uncommitted collector. Therefore, many collectors can be
tied together to provide an output OR’ing function. An output
pull-up resistor can be connected to any available power
supply voltage within the permitted power supply voltage
range and there is no restriction on this voltage due to the
magnitude of the voltage which is applied to the V+ terminal
of the LP339 package.
Typical Applications (V
+
=
15 V
DC
)
DS005226-11
FIGURE 1.
One-Shot Multivibrator
DS005226-13
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