NSC LMX2354TMX, LMX2354SLEX, LMX2354SLDX, LMX2354SLBX, LMX2354TM Datasheet

LMX2354
PLLatinum Fractional N RF/ Integer N IF Dual Low Power
Frequency Synthesizer
LMX2354 2.5 GHz/550 MHz

General Description

The LMX2354 is part of a family of monolithic integrated
fractional N/Integer N frequency synthesizers designed to be
used in a local oscillatorsubsystem for a radio transceiver. It
is fabricated using National’s 0.5 µ ABiC V silicon BiCMOS
process. The LMX2354 contains quadruple modulus pres­calers along with modulo 15 or 16 fractional compensation
circuitry in the RF divider. The LMX2354 provides a continu­ous divide ratio of 80 to 32767 in 16/17/20/21
(1.2 GHz–2.5 GHz) fractional mode and 40 to 16383 in
8/9/12/13 (550 MHz–1.2 GHz) fractional mode. The IF cir­cuitry for the LMX2354 contains an 8/9prescaler, and is fully
programmable. Using a fractional N phase locked loop tech­nique, the LMX2354 can generate very stable low noise
control signals for UHF and VHF voltage controlled oscilla­tors (VCOs).

For the RF PLL, a highly flexible 16 level programmable
charge pump supplies output current magnitudes from 100
µA to 1.6 mA. Two uncommitted CMOS outputs can be used
to provide external control signals, or configured to FastLock
mode. Serial dataistransferredintotheLMX2354 via a three
wire interface (Data, LE, Clock). Supply voltage can range
from 2.7V to 5.5V. The LMX2354 family features very low
current consumption; typically LMX2354 (2.5 GHz) — 7.0
mA. The LMX2354 are available in a 24-pin TSSOP surface
mount plastic package and 24-pin CSP.

Features

n Pin compatible/functional equivalent to the LMX2350
n Enhanced Low Noise Fractional Engine
n 2.7V to 5.5V operation
n Low current consumption

LMX2354: I

CC

= 7 mA typical at 3V

n Programmable or logical power down mode:

I

CC

= 5 µA typical at 3V

n Modulo 15 or 16 fractional RF N divider supports ratios

of 1, 2, 3, 4, 5, 8, 15, or 16

n Programmable charge pump current levels

RF 100 µA to 1.6 mA in 100 µA steps
IF 100 µA or 800 µA

n Digital filtered lock detect
n Available in 24-pin TSSOP and 24-pin CSP

Applications

n Portable wireless communications (PCS/PCN, cordless)
n Dual mode cellular telephone systems
n Zero blind slot TDMA systems
n Spread spectrum communication systems (CDMA)
n Cable TV Tuners (CATV)

Functional Block Diagram

20004801

August 2001

LMX2354 PLLatinum Fractional N RF/ Integer N IF Dual Low Power Frequency Synthesizer

© 2001 National Semiconductor Corporation DS200048 www.national.com

Connection Diagrams

20004802

Order Number LMX2354TM or LMX2355TM

See NS Package Number MTC24

20004822

Order Number LMX2354SLB or LMX2355SLB

See NS Package Number SLB

LMX2354

www.national.com 2

Pin Descriptions

Pin No. for

TSSOP

Package

Pin No. for

CSP

Package

Pin

Name I/O Description

1 24 OUT0 O Programmable CMOS output. Level of the output is controlled by IF_N [17] bit.
21V

CC

RF

— RF PLL power supply voltage input. Must be equal to VccIF. May range from

2.7V to 5.5V. Bypass capacitors should be placed as close as possible to this
pin and be connected directly to the ground plane.

32V

P

RF

— Power supply for RF charge pump. Must be ≥ V

CC

RF

and V

CC

IF

.

43CP

o

RF

O RF charge pump output. Connected to a loop filter for driving the control input

of an external VCO.
5 4 GND — Ground for RF PLL digital circuitry.
6 5 fin RF I RF prescaler input. Small signal input from the VCO.
7 6 fin RF

I RF prescaler complimentary input. A bypass capacitor should be placed as

close as possible to this pin and be connected directly to the ground plane.
8 7 GND — Ground for RF PLL analog circuitry.
9 8 OSC

RF

I Dual mode oscillator output or RF R counter input. Has a VCC/2 input threshold

when configured as an input and can be driven from an external CMOS or TTL

logic gate.

10 9 OSC

IF

I Oscillator input which can be configured to drive both the IF and RF R counter

inputs or only the IF R counter depending on the state of the OSC

programming bit. (See functional description 1.1 and programming description

3.1.)

11 10 Fo/LD O Multiplexed output of N or R divider and RF/IF lock detect. CMOS output. (See

programming description 3.1.5.)

12 11 RF_EN I RF PLL Enable. Powers down RF N and R counters, prescaler, and

TRI-STATE

®

charge pump output when LOW. Bringing RF_EN high powers up

RF PLL depending on the state of RF_CTL_WORD. (See functional description

1.9.)

13 12 IF_EN I IF PLL Enable. Powers down IF N and R counters, prescaler, and TRI-STATE

charge pump output when LOW. Bringing IF_EN high powers up IF PLL

depending on the state of IF_CTL_WORD. (See functional description 1.9.)

14 13 CLOCK I High impedance CMOS Clock input. Data for the various counters is clocked

into the 24-bit shift register on the rising edge.

15 14 DATA I Binary serial data input. Data entered MSB first. The last two bits are the

control bits. High impedance CMOS input.

16 15 LE I Load Enable high impedance CMOS input. Data stored in the shift registers is

loaded into one of the 4 internal latches when LE goes HIGH. (See functional

description 1.7.)

17 16 GND — Ground for IF analog circuitry.
18 17 fin IF

I IF prescaler complimentary input. A bypass capacitor should be placed as

close as possible to this pin and be connected directly to the ground plane.

19 18 fin IF I IF prescaler input. Small signal input from the VCO.
20 19 GND — Ground for IF digital circuitry.
21 20 CPo

IF

O IF charge pump output. For connection to a loop filter for driving the input of an

external VCO.

22 21 V

PIF

— Power supply for IF charge pump. Must be ≥ V

CC

RF

and V

CC

IF

.

23 22 V

CC

IF

— IF power supply voltage input. Must be equal to V

CC

RF

. Input may range from

2.7V to 5.5V. Bypass capacitors should be placed as close as possible to this

pin and be connected directly to the ground plane.

24 23 OUT1 O Programmable CMOS output. Level of the output is controlled by IF_N [18] bit.

LMX2354

www.national.com3

Absolute Maximum Ratings (Notes 1, 2)

Parameter Symbol

Value

Units

Min Typ Max

Power Supply Voltage V

CC

RF

−0.3 6.5 V

V

CC

IF

−0.3 6.5 V

Vp

RF

−0.3 6.5 V

Vp

IF

−0.3 6.5 V

Voltage on any pin with GND = 0V Vi −0.3 V

CC

+ 0.3 V
Storage Temperature Range Ts −65 +150 C˚
Lead Temperature (Solder 4 sec.) T

L

+260 C˚

Recommended Operating Conditions

Parameter Symbol

Value

Units

Min Typ Max

Power Supply Voltage V

CC

RF

2.7 5.5 V

V

CC

IF

V

CC

RF

V

CC

RF

V

V

pRF

V

CC

5.5 V

V

pIF

V

CC

5.5 V

Operating Temperature T

A

−40 +85 ˚C

Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended tobe functional, but donot guarantee specific performancelimits. For guaranteed specificationsand test conditions, seethe Electrical Characteristics. The
guaranteed specifications apply only for the test conditions listed.

Note 2: This Device is ahigh performance RF integrated circuit with an ESDrating

<

2kV and is ESDsensitive. Handling and assembly of this device shouldonly

be done at ESD-free workstations.

Electrical Characteristics (V

cc

RF

=V

cc

IF

=V

P

RF

=V

P

IF

= 3.0V; −40˚C<T

A

<

+85˚C except as specified)

All min/max specifications are guaranteed by design, or test, or statistical methods.

Symbol Parameter Conditions

Value

Units

Min Typ Max

GENERAL

I

CC

Power Supply Current RF and IF 6.0 8.5 mA

IF Only 1.1 2.0 mA

I

CC-PWDN

Power Down Current RF_EN = IF_EN = LOW 20 50 µA

f

in

RF RF Operating Frequency 0.5 2.5 GHz

f

in

IF IF Operating Frequency 10 550 MHz

f

OSC

Oscillator Frequency No load on OSC

RF

2 50 MHz
fφ Phase Detector Frequency RF and IF 10 MHz
Pf

in RF

RF Input Sensitivity VCC= 3.0V −15 0 dBm

V

CC

= 5.0V −10 0 dBm

Pf

in IF

IF Input Sensitivity 2.7V ≤ VCC≤ 5.5V −10 0 dBm

V

OSC

Oscillator Sensitivity OSCIF, OSC

RF

0.5 V

CC

V

PP

CHARGE PUMP

ICPo-

source RF

RF Charge Pump Output
Current (see Programming
Description 3.2.2)

VCPo Vp/2, RF_CP_WORD =
0000

−100 µA

ICPo-

sink RF

VCPo = Vp/2, RF_CP_WORD =
0000

100 µA

ICPo-

source RF

VCPo = Vp/2, RF_CP_WORD =
1111

−1.6 mA

ICPo-

sink RF

VCPo = Vp/2, RF_CP_WORD =
1111

1.6 mA

LMX2354

www.national.com 4

Electrical Characteristics (V

cc

RF

=V

cc

IF

=V

P

RF

=V

P

IF

= 3.0V; −40˚C<T

A

<

+85˚C except as specified)

All min/max specifications are guaranteed by design, or test, or statistical methods. (Continued)

Symbol Parameter Conditions

Value

Units

Min Typ Max

ICPo-

source IF

IF Charge Pump Output
Current (see Programming
Description 3.1.4)

VCPo = Vp/2, CP_GAIN_8 = 0 −100 µA

ICPo-

sink IF

VCPo = Vp/2, CP_GAIN_8 = 0 100 µA

ICPo-

source IF

VCPo = Vp/2, CP_GAIN_8 = 1 −800 µA

ICPo-

sink IF

VCPo = Vp/2, CP_GAIN_8 = 1 800 µA

ICPo-

Tri

Charge Pump TRI-STATE
Current

0.5 ≤ VCPo ≤ Vp −0.5

−40˚C

<

T

A

<

+85˚C

−2.5 2.5 nA

RF ICPo-

sink

vs. ICPo-

source

RF CP Sink vs. Source
Mismatch

VCPo = Vp/2 TA= 25˚C
RF ICPo=900µA − 1.6mA

3.5 10 %

ICPo vs. VCPo CP Current vs. Voltage

Variation

0.5 ≤ VCPo ≤ Vp −0.5
T

A

= 25˚C RF ICPo

510%

ICPo vs. T CP Current vs

Temperature

VCPo = Vp/2

−40˚C

<

T

A

<

+85˚C RF ICPo

8%

V

CP

Charge Pump Output
Voltage (RF only)

2.7V ≤ VCC≤ 3.3V, Doubler
Enabled

2*V

CC

−0.5

V

DIGITAL INTERFACE (DATA, CLK, LE, EN, FoLD)

V

IH

High-level Input Voltage (Note 3) 0.8 V

CC

V

V

IL

Low-level Input Voltage (Note 3) 0.2 V

CC

V

I

IL

Low-level Input Current VIL=0,VCC= 5.5V, (Note 3) −1.0 1.0 µA

I

IH

High-level Input Current VIH=VCC= 5.5V, (Note 3) −1.0 1.0 µA

I

IH

Oscillator Input Current VIH=VCC= 5.5V 100 µA

I

IL

Oscillator Input Current VIL=0,VCC= 5.5V −100 µA

V

OH

High-level Output Voltage IOH= −500 µA V

CC

−0.4

V

V

OL

High-level Output Voltage IOL= 500 µA 0.4 V

MICROWIRE TIMING

t

CS

Data to Clock Setup Time See Data Input Timing 50 ns

t

CH

Data to Clock Hold Time See Data Input Timing 10 ns

t

CWH

Clock Pulse Width High See Data Input Timing 50 ns

t

CWL

Clock Pulse Width Low See Data Input Timing 50 ns

t

ES

Clock to Load Enable Set
Up Time

See Data Input Timing

50 ns

t

EW

Load Enable Pulse Width See Data Input Timing 50 ns

Note 3: except fIN, OSCIFand OSC

RF

LMX2354

www.national.com5

Charge Pump Current Specification Definitions

20004823

I1 = CP sink current at VDo=Vp−∆V
I2 = CP sink current at V

Do

= Vp/2

I3 = CP sink current at V

Do

= ∆V

I4 = CP source current at V

Do

=Vp−∆V

I5 = CP source current at V

Do

= Vp/2

I6 = CP source current at V

Do

= ∆V

∆V = Voltage offset from positive and negative rails. Dependent on VCO tuning range relative to V

CC

and ground. Typical values are between 0.5V and 1.0V.

Note 4: I

Do

vs VDo= Charge Pump Output Current magnitude variation vs Voltage = [1⁄

2

*

{||1| − ||3|}]/[1⁄

2

*

{||1| + ||3|}]*100% and [1⁄

2

*

{||4| − ||6|}]/[1⁄

2

*

{||4| +

||6|}]

*

100%

Note 5: I

Do-sink

vs I

Do-source

= Charge Pump Output Current Sink vs Source Mismatch = [||2| − ||5|]/[1⁄

2

*

{||2| + ||5|}]*100%

Note 6: I

Do

vs TA= Charge Pump Output Current magnitude variation vs Temperature = [||2@temp| − ||2@25˚C|]/||2@25˚C|*100% and [||5@temp| − ||5

@

25˚C|]/||5@25˚C|*100%

LMX2354

www.national.com 6

RF Sensitivity Test Block Diagram

20004824

Note: N = 10,000 R = 50 P = 16
Note: Sensitivity limit is reached when the error of the divided RF output, F

o

LD, is ≥ 1 Hz.

Typical Performance Characteristics

ICCvs V

CC

LMX2354

I

CPO

TRI-STATE vs

CP

O

Voltage

20004825 20004827

Charge Pump Current vs CPOVoltage

RF_CP_WORD = 0000 and 0111

IF CP_GAIN_8 = 0 and 1

Charge Pump Current vs CP

O

Voltage

RF_CP_WORD = 0011 and 1111

20004828

20004829

LMX2354

www.national.com7