NSC LMX2306MWC, LMX2306TM Datasheet

LMX2306/LMX2316/LMX2326
PLLatinum

™

Low Power Frequency Synthesizer for RF
Personal Communications
LMX2306 550 MHz
LMX2316 1.2 GHz
LMX2326 2.8 GHz

General Description

The LMX2306/16/26 are monolithic, integrated frequency
synthesizers with prescalers that are designed to be used to
generate a very stable low noise signal for controlling the lo­cal oscillator of an RF transceiver. They are fabricated using
National’s ABiC V silicon BiCMOS 0.5µ process.

The LMX2306 contains a 8/9 dual modulus prescaler while
the LMX2316 and the LMX2326 have a 32/33 dual modulus
prescaler. The LMX2306/16/26 employ a digital phase
locked loop technique. When combined with a high quality
reference oscillator and loop filter, the LMX2306/16/26 pro­vide the feedback tuning voltage for a voltage controlled os­cillator to generate a low phase noise local oscillator signal.
Serial data is transferredintothe LMX2306/16/26 via a three
wire interface (Data, Enable, Clock). Supply voltage can
range from 2.3V to 5.5V. The LMX2306/16/26 feature ultra
low current consumption; LMX2306 - 1.7 mA at 3V,
LMX2316 - 2.5 mA at 3V, and LMX2326 - 4.0 mA at 3V.

The LMX2306/16/26 synthesizers are available in a 16-pin
TSSOP surface mount plastic package.

Features

n 2.3V to 5.5V operation
n Ultra low current consumption
n 2.5V V

CC

JEDEC standard compatible

n Programmable or logical power down mode:

—I

CC

= 1 µA typical at 3V

n Dual modulus prescaler:

— LMX2306 8/9
— LMX2316/26 32/33

n Selectable charge pump TRI-STATE

®

mode

n Selectable FastLock

™

mode with timeout counter

n MICROWIRE

™

Interface

n Digital Lock Detect

Applications

n Portable wireless communications (PCS/PCN, cordless)
n Wireless Local Area Networks (WLANs)
n Cable TV tuners (CATV)
n Pagers
n Other wireless communication systems

Functional Block Diagram

TRI-STATE®is a registered trademark of National Semiconductor Corporation.
FastLock

™

, PLLatinum™and MICROWIRE™are trademarks of National Semiconductor Corporation.

DS100127-1

April 2000

LMX2306/LMX2316/LMX2326 PLLatinum Low Power Frequency Synthesizer for RF Personal

Communications

© 2000 National Semiconductor Corporation DS100127 www.national.com

Connection Diagrams

Pin Descriptions

16-Pin

TSSOP

16-Pin

CSP

Pin

Name

I/O Description

115FL

o

O FastLock Output. For connection of parallel resistor to the loop filter. (See Section 1.3.4

FASTLOCK MODES description.)

216CP

o

O Charge Pump Output. For connection to a loop filter for driving the input of an external VCO.
3 1 GND Charge Pump Ground.
4 2 GND Analog Ground.
53f

IN

I RF Prescaler Complementary Input. A bypass capacitor should be placed as close as possible to

this pin and be connected directly to the ground plane. The complementary input can be left
unbypassed, with some degradation in RF sensitivity.

64f

IN

I RF Prescaler Input. Small signal input from the VCO.

75V

CC1

Analog Power Supply Voltage Input. Input may range from 2.3V to 5.5V. Bypass capacitors should
be placed as close as possible to this pin and be connected directly to the ground plane. V

CC1

must equal V

CC2

.

8 6 OSC

IN

I Oscillator Input. This input is a CMOS input with a threshold of approximately VCC/2 and an

equivalent 100k input resistance. The oscillator input is driven from a reference oscillator.

9 7 GND Digital Ground.

10 8 CE I Chip Enable. A LOW on CE powers down the device and will TRI-STATE the charge pump output.

Taking CE HIGH will power up the device depending on the status of the power down bit F2. (See
Section 1.3.1 POWERDOWN OPERATION and Section 1.7.1 DEVICE PROGRAMMING AFTER
FIRST APPLYING V

CC

.)

11 9 Clock I High Impedance CMOS Clock Input. Data for the various counters is clocked in on the rising edge

into the 21-bit shift register.

12 10 Data I Binary Serial Data Input. Data entered MSB first. The last two bits are the control bits. High

impedance CMOS input.

13 11 LE I Load Enable CMOS Input. When LE goes HIGH, data stored in the shift registers is loaded into one

of the 3 appropriate latches (control bit dependent).

14 12 Fo/LD O Multiplexed Output of the RF Programmable or Reference Dividers and Lock Detect. CMOS output.

(See

Table 4

.)

15 13 V

CC2

Digital Power Supply Voltage Input. Input may range from 2.3V to 5.5V. Bypass capacitors should
be placed as close as possible to this pin and be connected directly to the ground plane. V

CC1

must equal V

CC2

.

16 14 V

P

Power Supply for Charge Pump. Must be ≥ VCC.

LMX2306/16/26

DS100127-2

16-Lead (0.173” Wide) Thin Shrink Small Outline

Package(TM)

Order Number LMX2306TM, LMX2306TMX,

LMX2316TM, LMX2316TMX,

LMX2326TM or LMX2326TMX

See NS Package Number MTC16

LMX2306/16/26

DS100127-19

16-pin Chip Scale Package

Order Number LMX2306SLBX, LMX2316SLBX or

LM2326SLBX

See NS Package Number SLB16A

LMX2306/LMX2316/LMX2326

www.national.com 2

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Power Supply Voltage

V

CC1

−0.3V to +6.5V

V

CC2

−0.3V to +6.5V

V

p

−0.3V to +6.5V

Voltage on Any Pin

with GND = 0V (V

I

) −0.3V to VCC+ 0.3V

Storage Temperature Range (T

S

) −65˚C to +150˚C

Lead Temperature (T

L

)

(solder, 4 sec.) +260˚C

Recommended Operating
Conditions

Min Max Units

Power Supply Voltage

V

CC1

2.3 5.5 V

V

CC2

V

CC1

V

CC1

V

V

p

V

CC

5.5 V

Operating Temperature (T

A

) −40 +85 ˚C

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to
the device may occur. Recommended operating conditions indicate condi­tions for which the device is intended to be functional, but do not guarantee
specific performance limits. For guaranteed specifications and test condi­tions, see the Electrical Characteristics. The guaranteed specifications apply
only for the test conditions listed.

Note 2: Thisdevice is a high performance RF integrated circuit with an ESD
rating

<

2 keV and is ESD sensitive. Handling and assembly of this device

should only be done at ESD protected work stations.

Electrical Characteristics

VCC= 3.0V, Vp= 3.0V; −40˚C<T

A

<

85˚C except as specified

Symbol Parameter Conditions Values Units

Min Typ Max

I

CC

Power Supply Current LMX2306 VCC= 2.3V to 5.5 V 1.7 mA

LMX2316 V

CC

= 2.3V to 5.5V 2.5 mA

LMX2326 V

CC

= 2.3V to 5.5V 4.0 mA

I

CC-PWDN

Powerdown Current VCC= 3.0V 1 µA

f

IN

RF Input Operating
Frequency

LMX2306 VCC= 2.3V to 5.5V 25 550 MHz
LMX2316 V

CC

= 2.3V to 5.5V 0.1 1.2 GHz

LMX2326 V

CC

= 2.3V to 5.5V 0.1 2.1 GHz

V

CC

= 2.6V to 5.5V 0.1 2.8 GHz

f

osc

Maximum Oscillator Frequency 5 40 MHz
fφ Maximum Phase Detector Frequency 10 MHz
Pf

IN

RF Input Sensitivity VCC= 3.0V −15 +0 dBm

V

CC

= 5.0V −10 +0 dBm

V

CC

=2.3V to 5.5V −10 +0 dBm

P

osc

Oscillator Sensitivity OSC

IN

−5 dBm

V

IH

High-Level Input Voltage (Note 4) 0.8 x V

CC

V

V

IL

Low-Level Input Voltage (Note 4) 0.2 x

V

CC

V

I

IH

High-Level Input Current VIH=VCC= 5.5V (Note 4) −1.0 1.0 µA
I

IL

Low-Level Input Current VIL= 0V, VCC= 5.5V

(Note 4)

−1.0 1.0 µA

I

IH

Oscillator Input Current VIH=VCC= 5.5V 100 µA
I

IL

Oscillator Input Current VIL= 0V, VCC= 5.5V −100 µA
ICP

o-source

Charge Pump Output Current VDo=Vp/2, ICPo= LOW

(Note 3)

−250 µA

ICP

o-sink

VDo=Vp/2, ICPo= LOW
(Note 3)

250 µA

ICP

o-source

VDo=Vp/2, ICPo= HIGH
(Note 3)

−1.0 mA

ICP

o-sink

V

CPo=Vp

/2, ICPo= HIGH

(Note 3)

1.0 mA

ICP

o-Tri

Charge Pump TRI-STATE Current 0.5 ≤ V

CPo

≤ Vp− 0.5 −1.0 1.0 nA

−40˚C

<

T

A

<

85˚C

ICP

o-sink vs

CP Sink vs Source Mismatch V

CPo=Vp

/2 5 %

ICP

o-source

TA= 25˚C

LMX2306/LMX2316/LMX2326

www.national.com3

Electrical Characteristics (Continued)

VCC= 3.0V, Vp= 3.0V; −40˚C<T

A

<

85˚C except as specified

Symbol Parameter Conditions Values Units

Min Typ Max

ICP

o

vs VDoCP Current vs Voltage 0.5 ≤ V

CPo

≤ Vp− 0.5 5 %

T

A

= 25˚C

ICP

o

vs T CP Current vs Temperature V

CPo=Vp

/2 5 %

−40˚C

<

T

A

<

85˚C

V

OH

High-Level Output Voltage IOH= −500 µA VCC− 0.4 V

V

OL

Low-Level Output Voltage IOL= 500 µA 0.4 V

t

CS

Data to Clock Set Up Time See Data Input Timing 50 ns

t

CH

Data to Clock Hold Time See Data Input Timing 10 ns

t

CWH

Clock Pulse Width High See Data Input Timing 50 ns

t

CWL

Clock Pulse Width Low See Data Input Timing 50 ns

t

ES

Clock to Load Enable Set Up Time See Data Input Timing 50 ns

t

EW

Load Enable Pulse Width See Data Input Timing 50 ns

Note 3: See PROGRAMMABLE MODES for ICPodescription
Note 4: Except f

IN

and OSCIN.

LMX2306/LMX2316/LMX2326

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Charge Pump Current Specification Definitions

I1 = CP sink current at V

CPo=Vp

–∆V

I2 = CP sink current at V

CPo=Vp

/2

I3 = CP sink current at V

CPo

= ∆V

I4 = CP source current at V

CPo=Vp

–∆V

I5 = CP source current at V

CPo=Vp

/2

I6 = CP source current at V

CPo

= ∆V

∆V = Voltageoffset from positive and negative rails. Dependent on VCO tuning range relative to VCCand ground. Typicalvalues

are between 0.5V and 1.0V

1. ICP

o

vs V

CPo

= Charge Pump Output Current magnitude variation vs Voltage =

[

1

⁄

2

*

{ |I1| − |I3|}]/[1⁄

2

*

{|I1| + |I3|}]*100% and [1⁄

2

*

{|I4| − |I6|}]/[1⁄

2

*

{|I4| + |I6|}]*100%

2. ICP

o-sink

vs ICP

o–source

= Charge Pump Output Current Sink vs Source Mismatch =

[|I2| − |I5|]/[

1

⁄

2

*

{|I2| + |I5|}]*100%

3. ICP

o

vs T = Charge Pump Output Current magnitude variation vs Temperature =

[|I2

@

temp| − |I2@25˚C|]/|I2@25˚C|*100% and [|I5@temp| − |I5@25˚C|]/|I5@25˚C|*100%

DS100127-3

LMX2306/LMX2316/LMX2326

www.national.com5

RF Sensitivity Test Block Diagram

DS100127-15

Note 5: N=10,000 R=50 P=32
Note 6: Sensitivity limit is reached when the error of the divided RF output, FoLD, is greater than or equal to 1 Hz.

LMX2306/LMX2316/LMX2326

www.national.com 6