LMC6572 Dual/LMC6574 Quad
Low Voltage (2.7V and 3V) Operational Amplifier
LMC6572 Dual/LMC6574 Quad Low Voltage (2.7V and 3V) Operational Amplifier
December 1996
General Description
Low voltage operation and low power dissipation make the
LMC6574/2 ideal for battery-powered systems.
3V amplifier performance is backed by 2.7V guarantees to
ensure operation throughout battery lifetime. These guarantees also enable analog circuits to operate from the same
3.3V supply used for digital logic.
Battery life is maximized because each amplifier dissipates
only micro-watts of power.
The LMC6574/2 does not sacrifice functionality for low volt-
age operation. The LMC6574/2 generates 120 dB of
open-loop gain just like a conventional amplifier, but the
LMC6574/2 can do this from a 2.7V supply.
These amplifiers are designed with features that optimize
low voltage operation. The output voltage swings rail-to-rail
to maximize signal-to-noise ratio and dynamic signal range.
The common-mode input voltage range extends from
800 mV below the positive supply to 100 mV below ground.
This device is built with National’s advanced Double-Poly
Silicon-Gate CMOS process.
LMC6572 is also available in MSOP package which is almost half the size of a SO-8 device.
Connection Diagrams
8-Pin DIP/SO/MSOP
Features
(Typical unless otherwise noted)
n Guaranteed 2.7V and 3V Performance
n Rail-to-Rail Output Swing (within 5 mV of supply rail,
100 kΩ load)
n Ultra-Low Supply Current: 40 µA/Amplifier
n Low Cost
n Ultra-Low Input Current: 20 fA
n High Voltage Gain
n Specified for 100 kΩ and 5 kΩ loads
n Available in MSOP Package
=
@
V
S
2.7V, R
=
100 kΩ: 120 dB
L
Applications
n Transducer Amplifier
n Portable or Remote Equipment
n Battery-Operated Instruments
n Data Acquisition Systems
n Medical Instrumentation
n Improved Replacement for TLV2322 and TLV2324
14-Pin DIP/SO
DS011934-1
Order Number LMC6572AIN, LMC6572BIN,
LMC6572AIM, LMC6572BIM or LMC6572BIMM
See NS Package Number N08E, M08A or MUA08A
Order Number LMC6574AIN, LMC6574BIN,
LMC6574AIM or LMC6574BIM
See NS Package Number N14A or M14A
© 1999 National Semiconductor Corporation DS011934 www.national.com
DS011934-2
Ordering Information
Package Temperature Range NSC Drawing Transport
Industrial, −40˚C to +85˚C Media
8-Pin Molded DIP LMC6572AIN, LMC6572BIN N08E Rail
8-Pin Small Outline LMC6572AIM, LMC6572BIM M08A Rail
LMC6572AIMX, LMC6572BIMX Tape and Reel
8-Pin Mini SO LMC6572BIMM MUA08A Rail
LMC6572BIMMX Tape and Reel
14-Pin Molded DIP LMC6574AIN, LMC6574BIN N14A Rail
14-Pin Small Outline LMC6574AIM, LMC6574BIM M14A Rail
LMC6574AIMX, LMC6574BIMX Tape and Reel
www.national.com 2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ESD Tolerance (Note 2) 2000V
Differential Input Voltage
Voltage at Input/Output Pin (V
+−V−
Supply Voltage (V
) 12V
Current at Input Pin
Current at Output Pin (Note 3)
Current at Power Supply Pin 35 mA
Lead Temperature
(Soldering, 10 Seconds) 260˚C
Storage Temperature Range −65˚C to +150˚C
±
Supply Voltage
+
) +0.3V,
−
) −0.3V
(V
±
±
10 mA
5mA
Junction Temperature (Note 4) 150˚C
Operating Ratings (Note 1)
Supply Voltage 2.7V ≤ V
Junction Temperature Range
LMC6572AI, LMC6572BI −40˚C ≤ T
LMC6574AI, LMC6574BI −40˚C ≤ T
Thermal Resistance (θ
)
JA
N Package, 8-Pin Molded DIP 115˚C/W
M Package, 8-Pin Surface Mount 193˚C/W
MSOP Package, 8-Pin Mini SO 217˚C/W
N Package, 14-Pin Molded DIP 81˚C/W
M Package, 14-Pin Surface Mount 126˚C/W
+
≤ 11V
≤ +85˚C
J
≤ +85˚C
J
2.7V DC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for T
face limits apply at the temperature extremes.
Symbol Parameter Conditions Typ
+
V
OS
TCV
Input Offset Voltage V
Input Offset Voltage 1.5 µV/˚C
OS
=
2.7V and 3V 0.5 3 7 mV
=
J
25˚C. V
+
=
2.7V, V
−
=
(Note 5)
Average Drift
I
B
I
OS
R
C
Input Current 0.02 pA
Input Offset Current 0.01 pA
Input Resistance
IN
Common-Mode 3 pF
IN
>
Input Capacitance
CMRR Common Mode 0V ≤ V
Rejection Ratio V
+PSRR Positive Power Supply 2.7V ≤ V
Rejection Ratio V
−PSRR Negative Power Supply −2.7V ≤ V
Rejection Ratio V
V
Input Common-Mode V
CM
≤ 3.5V 75 63 60 dB
CM
+
=
5V 60 57 Min
+
≤ 5V, 75 67 60 dB
−
=
0V 65 58 Min
−
+
+
≤ −5V, 83 75 67 dB
=
0V 73 65 Min
=
2.7V and 3V −0.1 −0.05 −0.05 V
Voltage Range for CMRR ≥ 50 dB 00Max
+
V
− 0.8 V+− 1.0 V+− 1.0 V
A
Large Signal R
V
=
100 kΩ Sourcing 1000 V/mV
L
Voltage Gain (Note 7)
Sinking 500 V/mV
0V, V
=
/2 and R
V
CM
V
O
>
1MΩ. Bold-
L
+
=
LMC6574AI LMC6574BI Units
LMC6572AI LMC6572BI
Limit Limit
(Note 6) (Note 6)
3.5 7.5 Max
10 10 Max
66Max
1 Tera Ω
+
V
− 1.3 V+− 1.3 Min
www.national.com3
2.7V DC Electrical Characteristics (Continued)
Unless otherwise specified, all limits guaranteed for T
face limits apply at the temperature extremes.
=
J
25˚C. V
+
=
Symbol Parameter Conditions Typ
+
V
I
SC
Output Swing V
O
Output Short Sourcing, V
=
2.7V 2.695 2.68 2.65 V
=
R
100 kΩ to V
L
+
=
V
2.7V 2.66 2.55 2.45 V
=
R
5kΩto V
L
+
=
V
3V 2.995 2.98 2.95 V
=
R
100 kΩ to V
L
+
=
V
3V 2.96 2.85 2.75 V
=
R
5kΩto V
L
+
/2 2.66 2.62 Min
+
/2 2.45 2.35 Min
+
/2 2.96 2.93 Min
+
/2 2.75 2.65 Min
=
0V 6.0 4.0 3.0 mA
O
Circuit Current 3.0 2.0 Min
=
+2.7V, V
=
2.7V 4.0 3.0 2.5 mA
O
+
=
/2 280 280 Max
V
O
Sinking, V
I
S
Supply Current Quad Package 160 240 240 µA
+
V
Quad Package 160 240 240 µA
+
=
V
+3V, V
+
=
/2 280 280 Max
V
O
Dual Package 80 120 120 µA
V
+
=
+2.7V, V
+
=
/2 140 140 Max
V
O
Dual Package 80 120 120 µA
+
=
V
+3V, V
+
=
/2 140 140 Max
V
O
−
=
2.7V, V
(Note 5)
0.005 0.03 0.06 V
0.04 0.15 0.25 V
0.005 0.03 0.06 V
0.04 0.15 0.25 V
+
=
=
0V, V
CM
/2 and R
V
V
O
LMC6574AI LMC6574BI Units
LMC6572AI LMC6572BI
Limit Limit
(Note 6) (Note 6)
0.05 0.09 Max
0.25 0.35 Max
0.05 0.09 Max
0.25 0.35 Max
2.0 1.5 Min
>
1MΩ. Bold-
L
2.7V AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for T
face limits apply at the temperature extremes.
J
=
25˚C, V
+
=
2.7V, V
Symbol Parameter Conditions Typ
+
=
SR Slew Rate V
2.7V and 3V 90 30 30 V/ms
(Note 8) 10 10 Min
+
GBW Gain-Bandwidth Product V
φ
m
G
m
Phase Margin 60 Deg
Gain Margin 12 dB
=
3V 0.22 MHz
Amp-to-Amp Isolation (Note 9) 120 dB
e
n
i
n
www.national.com 4
Input-Referred F=1 kHz 45 nV/√Hz
Voltage Noise V
=
1V
CM
Input-Referred F=1 kHz 0.002 pA/√Hz
−
=
0V, V
(Note 5)
+
=
=
/2 and R
V
CM
V
O
>
1MΩ.Bold-
L
LMC6574AI LMC6574BI Units
LMC6572AI LMC6572BI
Limit Limit
(Note 6) (Note 6)
2.7V AC Electrical Characteristics (Continued)
Unless otherwise specified, all limits guaranteed for T
face limits apply at the temperature extremes.
=
J
25˚C, V
+
=
Symbol Parameter Conditions Typ
Current Noise
=
T.H.D. Total Harmonic Distortion F=10 kHz, A
=
R
10 kΩ,V
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device mayoccur. Operating Ratings indicate conditions for which the device isintended to be functional, but specific performance is not guaranteed. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2: Human body model, 1.5 kΩ in series with 100 pF.
Note 3: Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in exceeding the
maximum allowed junction temperature of 150˚C.
Note 4: The maximum power dissipation is a function of T
=
P
(T
D
Note 5: Typical values represent the most likely parametric norm.
Note 6: All limits are guaranteed by testing or statistical analysis.
Note 7: V
Note 8: Connected as Voltage Follower with 1.0V step input. Number specified is the slower of the positive and negative slew rates.
Note 9: Input referred, V
)/θJA. All numbers apply for packages soldered directly into a PC board.
J(Max)−TA
+
=
3V, V
CM
=
1.5V and R
+
connected to 1.5V. For Sourcing tests, 1.5V ≤ VO≤ 2.5V. For Sinking tests, 0.5V ≤ VO≤ 1.5V.
L
=
3V and R
=
100 kΩ connected to 1.5V. Each amp excited in turn with 1 KHz to produce V
L
L
J(Max)
−2 0.05
V
=
1.0 V
O
, θJA, and TA. The maximum allowable power dissipation at any ambient temperature is
2.7V, V
PP
−
=
0V, V
(Note 5)
=
CM
+
=
/2 and R
V
V
O
>
1MΩ.Bold-
L
LMC6574AI LMC6574BI Units
LMC6572AI LMC6572BI
Limit Limit
(Note 6) (Note 6)
=
.
2V
O
PP
%
Typical Performance Characteristics V
Supply Current vs
Supply Voltage (Dual Package)
DS011934-18
Sinking Current vs
Output Voltage
DS011934-21
Input Current vs
Temperature
Output Voltage Swing vs
Supply Voltage
=
S
+3V, T
=
25˚C, Unless otherwise specified
A
Sourcing Current vs
Output Voltage
DS011934-19
DS011934-20
Input Voltage Noise vs
Frequency
DS011934-22
DS011934-23
www.national.com5
Typical Performance Characteristics V
=
S
+3V, T
=
25˚C, Unless otherwise specified (Continued)
A
Crosstalk Rejection vs
Frequency
CMRR vs Frequency
Open Loop Frequency
Response vs Temperature
DS011934-24
DS011934-27
Positive PSRR vs
Frequency
Input Voltage vs
Output Voltage (V
=
±
S
Maximum Output Swing
vs Frequency
1.5)
DS011934-25
DS011934-28
Negative PSRR vs
Frequency
Open Loop Frequency
Response
Z
vs Frequency
OUT
DS011934-26
DS011934-29
DS011934-30
www.national.com 6
DS011934-31
DS011934-32
Typical Performance Characteristics V
=
S
+3V, T
=
25˚C, Unless otherwise specified (Continued)
A
Slew Rate
vs Supply Voltage
Inverting Large Signal
Pulse Response
Stability
vs Capacitive Load
DS011934-33
DS011934-36
Non-Inverting Large Signal
Pulse Response
Inverting Small Signal
Pulse Response
Stability
vs Capacitive Load
DS011934-34
DS011934-37
Non-Inverting Small Signal
Pulse Response
DS011934-35
Stability
vs Capacitive Load
DS011934-38
Stability
vs Capacitive Load
DS011934-39
DS011934-40
DS011934-41
www.national.com7
Typical Performance Characteristics V
=
S
+3V, T
=
25˚C, Unless otherwise specified (Continued)
A
Bandwidth vs
Capacitive Load
DS011934-44
Capacitive Load
vs Phase Margin
Applications Hints
1.0 LOW VOLTAGE AMPLIFIER TOPOLOGY
The LMC6574/2 incorporates a novel op-amp design topology that enables it to maintain rail-to-rail output swing even
when driving a large load. Instead of relying on a push-pull
unity gain output buffer stage, the output stage is taken directly from the internal integrator, which provides both low
output impedance and large gain. Special feed-forward compensation design techniques are incorporated to maintain
stability over a wider range of operating conditions than traditional micropower op-amps. These features make the
LMC6574/2 both easier to design with, and provide higher
speed than products typically found in this ultra-low power
class.
2.0 COMPENSATING FOR INPUT CAPACITANCE
It is quite common to use large values of feedback resistance for amplifiers with ultra-low input current, like the
LMC6574/2.
Although the LMC6574/2 is highly stable over a wide range
of operating conditions, a large feedback resistor will react
even with small values of capacitance at the input of the
op-amp to reduce phase margin. The capacitance at the input of the op-amp comes from transducers, photodiodes and
circuit board parasitics.
The effect of input capacitance can be compensated for by
adding a capacitor, C
Figure 1
) such that:
, around the feedback resistors (as in
f
Capacitive Load
vs Gain Margin
DS011934-45
DS011934-46
DS011934-6
FIGURE 1. Cancelling the Effect of Input Capacitance
3.0 CAPACITIVE LOAD TOLERANCE
Direct capacitive loading will reduce the phase margin of
many op-amps. Apole in the feedback loop is created by the
combination of the op-amp’s output impedance and the capacitive load. This pole induces phase lag at the unity-gain
crossover frequency of the amplifier resulting in either an oscillatory or underdamped pulse response. With a few external components, op amps can easily indirectly drive capacitive loads, as shown in
Figure 2
.
or
≤ R2C
R
1CIN
f
Since it is often difficulttoknowtheexactvalueofCIN,Cfcan
be experimentally adjusted so that the desired pulse response is achieved. Refer to the LMC660 and LMC662 for a
more detailed discussion on compensating for input capacitance.
When high input impedances are demanded, guarding of the
LMC6574/2 is suggested. Guarding input lines will not only
reduce leakage, but lowers stray input capacitance as well.
(See
Printed-Circuit-Board Layout for High Impedance
Work).
www.national.com 8
DS011934-7
FIGURE 2. LMC6574/2 Noninverting Gain of 10
Amplifier, Compensated to Handle Capacitive Loads
Figure 2
In the circuit of
, R1 and C1 serve to counteract the
loss of phase margin by feeding the high frequency compo-
Applications Hints (Continued)
nent of the output signal back to the amplifier’s inverting input, thereby preserving phase margin in the overall feedback
loop.
4.0 PRINTED-CIRCUIT-BOARD LAYOUT
FOR HIGH-IMPEDANCE WORK
It is generally recognized that any circuit which must operate
with less than 1000 pA of leakage current requires special
layout of the PC board. When one wishes to take advantage
of the ultra-low bias current of the LMC6574/2, typically less
than 20 fA, it is essential to have an excellent layout. Fortunately, the techniques of obtaining low leakages are quite
simple. First, the user must not ignore the surface leakage of
the PC board, even though it may sometimes appear acceptably low, because under conditions of high humidity or dust
or contamination, the surface leakage will be appreciable.
To minimize the effect of any surface leakage, lay out a ring
of foil completely surrounding the LMC6574/2’s inputs and
the terminals of capacitors, diodes, conductors, resistors, relay terminals, etc. connected to the op-amp’s inputs, as in
Figure 3
. To have a significant effect, guard rings should be
placed on both the top and bottom of the PC board. This PC
foil must then be connected to a voltage which is at the same
voltage as the amplifier inputs, since no leakage current can
flow between two points at the same potential. For example,
a PC board trace-to-pad resistance of 10
mally considered a very large resistance, could leak 5 pA if
the trace were a 5V bus adjacent to the pad of the input. This
would cause a 250 times degradation from the LMC6574/2’s
actual performance. However, if a guard ring is held within
5 mV of the inputs, then even a resistance of 10
cause only 0.05 pAof leakage current. See
cal connections of guard rings for standard op-amp
configurations.
12
Ω, which is nor-
11
Ω would
Figure 4
for typi-
DS011934-9
Inverting Amplifier
DS011934-10
Non-Inverting Amplifier
DS011934-11
Follower
FIGURE 4. Typical Connections of Guard Rings
The designer should be aware that when it is inappropriate
to lay out a PC board for the sake of just a few circuits, there
is another technique which is even better than a guard ring
on a PC board: Don’t insert the amplifier’s input pin into the
board at all, but bend it up in the air and use only air as an insulator. Air is an excellent insulator. In this case you may
have to forego some of the advantages of PC board construction, but the advantages are sometimes well worth the
effort of using point-to-point up-in-the-air wiring. See
5
.
Figure
DS011934-8
FIGURE 3. Example of Guard Ring in P.C. Board
Layout
(Input pins are lifted out of PC board and soldered directly to components.
All other pins connected to PC board).
DS011934-12
FIGURE 5. Air Wiring
www.national.com9
Applications Hints (Continued)
5.0 SPICE MACROMODEL
A spice macromodel is available for the LMC6574/2. This
model includes accurate simulation of:
input common-mode voltage range
•
frequency and transient response
•
GBW dependence on loading conditions
•
quiescent and dynamic supply current
•
output swing dependence on loading conditions
•
and many more characteristics as listed on the macromodel
disk.
Contact your local National Semiconductor sales office to
obtain an operational amplifier spice model library disk.
Typical Single-Supply Applications
DS011934-13
FIGURE 6. Low-Power Two-Op-Amp
Instrumentation Amplifier
DS011934-15
FIGURE 8. 1 Hz Square Wave Oscillator
DS011934-16
FIGURE 9. Adder/Subtractor Circuit
DS011934-14
FIGURE 7. Sample and Hold
www.national.com 10
DS011934-17
FIGURE 10. Low Pass Filter
Physical Dimensions inches (millimeters) unless otherwise noted
Order Package Number LMC6572AIM or LMC6572BIM
Order Package Number LMC6574AIM or LMC6574BIM
8-Pin Small Outline Package
NS Package Number M08A
14-Pin Small Outline Package
NS Package Number M14A
www.national.com11
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
8-Lead Mini-Small Outline Molded Package, JEDEC
Order Number LMC6572BIMM or LMC6572BIMMX
www.national.com 12
NS Package Number MUA08A
8-Pin Molded Dual-In-Line Package
Order Number LMC6572AIN or LMC6572BIN
NS Package Number N08E
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Pin Molded Dual-In-Line Package
Order Number LMC6574AIN or LMC6574BIN
NS Package Number N14A
LMC6572 Dual/LMC6574 Quad Low Voltage (2.7V and 3V) Operational Amplifier
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
labeling, can be reasonably expected to result in a
significant injury to the user.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitryandspecifications.
National Semiconductor
Europe
Fax: +49 (0) 1 80-530 85 86
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 1 80-530 85 85
English Tel: +49 (0) 1 80-532 78 32
Français Tel: +49 (0) 1 80-532 93 58
Italiano Tel: +49 (0) 1 80-534 16 80
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
Email: sea.support@nsc.com
National Semiconductor
Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
Loading...