NSC LM6313N Datasheet

LM6313 High Speed,
High Power Operational Amplifier

LM6313 High Speed, High Power Operational Amplifier

February 1995

General Description

The LM6313 is a high-speed, high-power operational ampli­fier. This operational amplifier features a 35 MHz small sig­nal bandwidth, and 250 V/ms slew rate. A compensation pin
is included for adjusting the open loop bandwidth. The input
stage (A1) and output stage (A2) are pinned out separately,
and can be used independently. The operational amplifier is
designed for low impedance loads and will deliver

g

300 mA. The LM6313 has both overcurrent and thermal
shutdown protection with an error flag to signal both these
fault conditions.

These amplifiers are built with National’s VIP

TM

(Vertically
Integrated PNP) process which provides fast PNP transis­tors that are true complements to the already fast NPN de­vices. This advanced junction-isolated process delivers high
speed performance without the need for complex and ex­pensive dielectric isolation.

Connection Diagram

Dual-In-Line Package

Features

Y

High slew rate 250 V/ms

Y

Wide bandwidth 35 MHz

Y

Peak output current

Y

Input and output stages pinned out separately

Y

Single or dual supply operation

Y

Thermal protection

Y

Error flag warns of faults

Y

Wide supply voltage range

g

300 mA

g

5V tog15V

Applications

Y

High speed ATE pin driver

Y

Data acquisition

Y

Driving capacitive loads

Y

Flash A-D input driver

Y

Precision 50X –75X video line driver

Y

Laser diode driver

Typical Application

TL/H/10521– 2

TL/H/10521– 1

Top View

Order Number LM6313N

See NS Package Number N16A

*Heat sink pins

See Note 5 and Applications.

**Do not ground or otherwise connect to this pin.

VIPTMis a trademark of National Semiconductor Corporation.

C

1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.

TL/H/10521

Absolute Maximum Ratings (Note 1)

a

Total Supply Voltage (

A1 Differential Input Voltage (Note 2)

A1 Input Voltage (V

A2 Input to Output Voltage

A2 Input Voltage

Flag Output Voltage GND toaV

Short-Circuit to Ground (Note 3)

Storage Temperature Range

VStobVS) 36V (g18)

g

a

b

b

65§CsT

0.7) to (V

7V

b

b

7V)

g

7V

g

V

s

a

150§C

Lead Temperature (Soldering, 5 seconds) 260

ESD Tolerance (Note 4)

Pins 10 and 11
All Other Pins

Operating Temperature Range

S

S

LM6313N 0

Thermal Derating Information (Note 5)

i

JA

T

(Max) 125§C

J

g

600V

g

1500V

Cto70§C

§

40§C/W

C

§

Operational Amplifier DC Electrical Characteristics Unless otherwise specified, all limits

guaranteed for T

e

R

50X, the circuit configured as in

S

Symbol Parameter Conditions Typical

V

OS

DVOS/DT Average Input Offset

I

b

I

OS

DIOS/DT Average Input Offset

R

IN

C

IN

V

CM

A

V1

A

V2

CMRR Common-Mode

PSRR Power Supply

V

O1

V

O2

V

O3

I

S

I

SC

e

25§C, and Supply Voltage V

A

Figure 1

e

g

15V. Boldface limits apply at temperature extremes. V

S

.

C0

25

§

Cto70§C

§

Limit Limit

CM

e

Units

Input Offset Voltage 5 20 22 mV (Max)

Voltage Drift

10 mV/

Input Bias Current 2 5 7 mA (Max)

Input Offset Current 0.15 1.5 1.9 mA (Max)

Current Drift

0.4 nA/

§

Input Resistance Differential 325 kX

Input Capacitance A

Common-Mode
Voltage Range

Voltage Gain 1 R
Voltage Gain 2 R

Rejection Ratio

Rejection Ratio

Output Voltage Swing 1 R
Output Voltage Swing 2 R
Output Voltage Swing 3 R

Supply Current T

Peak Short-Circuit Output (See

ea

1, fe10 MHz 2.2 pF

V

a

14.2

b

13.2

e

L

e

L

b

10VsV

g

5VsV

e

L

e

L

e

L

e

0§C 24

J

e

T

25§C 18 23 mA (Max)

J

e

T

125§C 21

J

Figure 3

e

1kX,V
50X,V

g

10V 6000 2500 2000

O

e

g

8V 5000 2000 1500

O

s

a

10V

CM

s

g

16V

S

90 72 70 dB (Min)

90 72 70 dB (Min)

1kX 13.1 11.8 11.2
100X 12.0 10.5 10.0
50X 11.0 9.0 8.5

) 300 mA

a

13.8

b

12.8

a
b

13.7

12.7

V (Min)

V/V (Min)

g

V (Min)

0V,

C

§

C

FIGURE 1

2

TL/H/10521– 3

Electrical Characteristics (Continued)

Operational Amplifier AC Electrical Characteristics Unless otherwise specified, all limits

guaranteed for T

e

R

50X, the circuit configured as in

S

e

25§C, and Supply Voltage V

A

Figure 1

e

g

15V. Boldface limits apply at temperature extremes. V

S

.

CM

e

Symbol Parameter Conditions Typical Units

GBW Gain-Bandwidth Product

SR Slew Rate A

PBW Power Bandwidth V

t

S

Settling Time 10V Step to 0.1% (See

Phase Margin A

@

fe30 MHz 35 MHz

V

OUT

V

eb

eb

e

1, R

50X (Note 6) 250 V/ms

L

e

20 V

1, R

L

PP

e

1kX,C

Figure 2

) 200 ns

e

50 pF 53 Deg

L

3.0 MHz

Differential Gain 0.1 %

Differential Phase 0.1 Deg

e

n

i

n

A1 DC Electrical Characteristics Unless otherwise specified, all limits guaranteed for T

Supply Voltage V

Symbol Parameter Conditions Typical

A

VOL

CMRR Common-Mode

PSRR Power Supply

I

SC

Input Noise Voltage fe10 kHz 14 nV/SHz

Input Noise Current fe10 kHz 1.8 pA/SHz

e

g

15V. Boldface limits apply at temperature extremes. V

S

CM

e

0V, R

25

e

50X.

S

C0

§

Cto70§C

§

Limit Limit

Large Signal Voltage Gain V

Rejection Ratio

Rejection Ratio

Output Short
Circuit Current

OUT

V

OUT

b

10VsV

g

5V

e

g

e

g

s

g

10V, R
10V, R

CM

s

V

S

e

2kX 650 300 250

L

e %

L

s

a

10V

a

16V

6000 2500 2000

90 72 70 dB (Min)

90 72 70 dB (Min)

g

60

g

30

g

25 mA (Min)

A

e

25§C, and

V/V (Min)

Units

0V,

A1 AC Electrical Characteristics Unless otherwise specified, all limits guaranteed for T

Supply Voltage V

Symbol Parameter Conditions Typical

e

g

15V. Boldface limits apply at temperature extremes. R

S

e

50X.

S

25

§

Limit

e

25§C, and

A

C Units

GBW Gain-Bandwidth fe30 MHz 37 25 MHz (Min)

e

1500X.

ea

V

g

2V

SR Slew Rate A

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. For guaranteed specifications and test conditions, see the
Electrical Characteristics. The guaranteed specifications apply only for the test condition listed. Some performance characteristics may degrade when the device is
not operated under the listed test conditions.

Note 2: In order to achieve optimum AC performance, the input stage was designed without protective clamps. Exceeding the maximum differential input voltage
results in reverse breakdown of the base-emitter junction of one of the input transistors. Degradation of the input parameters (especially V
proportional to the level of the externally limited breakdown current and the accumulated duration of the breakdown condition.

Note 3: Continuous short-circuit operation of A1 at elevated temperature can result in exceeding the maximum allowed junction temperature of 125
current limit and thermal shutdown to protect against fault conditions. The device may be damaged by shorts to the supplies.

Note 4: Human body model, C

e

100 pF, R

S

OUT

1, R

L

e

100 kX,g4VIN,

250 150 V/ms (Min)

, and Noise) is

OS,IOS

C. A2 contains

§

3