Application Hints
EXTERNAL CAPACITORS
The output capacitor is critical to maintaining regulator stability, and must meet the required conditions for both ESR
(Equivalent Series Resistance) and minimum amount of capacitance.
MINIMUM CAPACITANCE:
The minimum output capacitance required to maintain stabil-
ity is 10 µF (this value may be increased without limit).
Larger values of output capacitance will give improved transient response.
ESR LIMITS:
The ESR of the output capacitor will cause loop instability if
it is too high or too low. The acceptable range of ESR plotted
versus load current is shown in the graph below.
It is essential that the output capacitor meet these requirements,
or oscillations can result.
It is important to note that for most capacitors, ESR is specified only at room temperature. However, the designer must
ensure that the ESR will stay inside the limits shown over the
entire operating temperature range for the design.
For aluminum electrolytic capacitors, ESR will increase by
about 30X as the temperature is reduced from 25˚C to
−40˚C. This type of capacitor is not well-suited for low temperature operation.
Solid tantalum capacitors have a more stable ESR over temperature, but are more expensive than aluminum electrolytics. A cost-effective approach sometimes used is to parallel
an aluminum electrolytic with a solid Tantalum, with the total
capacitance split about 75/25%with the Aluminum being the
larger value.
If two capacitors are paralleled, the effective ESR is the parallel of the two individual values. The “flatter” ESR of the Tantalum will keep the effective ESR from rising as quickly at low
temperatures.
HEATSINKING
A heatsink may be required depending on the maximum
power dissipation and maximum ambient temperature of the
application. Under all possible operating conditions, the junction temperature must be within the range specified under
Absolute Maximum Ratings.
To determine if a heatsink is required, the power dissipated
by the regulator, P
D
, must be calculated.
The figure below shows the voltages and currents which are
present in the circuit, as well as the formula for calculating
the power dissipated in the regulator:
The next parameter which must be calculated is the maximum allowable temperature rise, T
R
(max). This is calcu-
lated by using the formula:
T
R
(max)=TJ(max) − TA(max)
where: T
J
(max) is the maximum allowable junction tem-
perature, which is 125˚C for commercial
grade parts.
T
A
(max) is the maximum ambient temperature
which will be encountered in the application.
Using the calculated values for T
R
(max) and PD, the maximum allowable value for the junction-to-ambient thermal resistance, θ
(J−A)
, can now be found:
θ
(J−A)
=
T
R
(max)/P
D
IMPORTANT: If the maximum allowable value for θ
(J−A)
is
found to be ≥ 53˚C/W for the TO-220 package, ≥ 80˚C/W for
the TO-263 package, or ≥174˚C/W for the SOT-223 package, no heatsink is needed since the package alone will dissipate enough heat to satisfy these requirements.
If the calculated value for θ
(J−A)
falls below these limits, a
heatsink is required.
HEATSINKING TO-220 PACKAGE PARTS
The TO-220 can be attached to a typical heatsink, or secured to a copper plane on a PC board. If a copper plane is
to be used, the values of θ
(J−A)
will be the same as shown in
the next section for the TO-263.
If a manufactured heatsink is to be selected, the value of
heatsink-to-ambient thermal resistance, θ
(H−A)
, must first be
calculated:
θ
(H−A)
=
θ
(J−A)
− θ
(C−H)
− θ
(J−C)
Where: θ
(J−C)
is defined as the thermal resistance from
the junction to the surface of the case. A
value of 3˚C/W can be assumed for θ
(J−C)
for this calculation.
θ
(C−H)
is defined as the thermal resistance between the case and the surface of the heatsink. The value of θ
(C−H)
will vary from
about 1.5˚C/W to about 2.5˚C/W (depending on method of attachment, insulator,
etc.). If the exact value is unknown, 2˚C/W
should be assumed for θ
(C−H)
.
When a value for θ
(H−A)
is found using the equation shown,
a heatsink must be selected that has a value that is less than
or equal to this number.
Output Capacitor ESR
DS100113-17
FIGURE 1. ESR Limits
DS100113-19
I
IN
=
I
L
÷
I
G
P
D
=
(V
IN−VOUT)IL
+(VIN)I
G
FIGURE 2. Power Dissipation Diagram
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