NSC DS34LV86TMX, DS34LV86TM Datasheet

DS34LV86T 3V Enhanced CMOS Quad Differential Line Receiver

General Description

The DS34LV86Tisahighspeedquaddifferential CMOS receiver that meets the requirements of both TIA/EIA-422-B and ITU-T V.11.TheCMOSDS34LV86Tfeatures typical low static I

of 9 mA which makes it ideal for battery powered

and power conscious applications. The TRI-STATE

enables, EN, allow the device to be disabled when not in use to minimize power consumption. The dual enable scheme allows for flexibility in turning receivers on and off.

The receiver output (RO) is guaranteed to be High when the inputs are left open. The receiver can detect signals as low as

200 mV over the common mode range of±10V.The receiver outputs (RO) are compatible with TTL and LVCMOS levels.

Features

n Low power CMOS design (30 mW typical) n Interoperable with existing 5V RS-422 networks n Industrial temperature range n Meets TIA/EIA-422-B (RS-422) and ITU-T V.11

recommendation

n 3.3V Operation

7V common mode range VID=3V

10V common mode range VID= 0.2V

n Receiver OPEN input failsafe feature n Guaranteed AC parameter:

Maximum Receiver Skew: 4 ns Transition time: 10 ns

n Pin compatible with DS34C86T n 32 MHz Toggle Frequency n 6.5k ESD Tolerance (HBM) n Available in SOIC packaging

Connection Diagram Truth Table

Enable Inputs Output

EN RI+–RI− RO

LXZ HV

≥ +0.2V H

≤ −0.2V L

H Open

†

L = Logic Low H = Logic High X = Irrelevant Z = TRI-STATE

†

= Open, Not Terminated

TRI-STATE®is a registered trademark of National Semiconductor Corporation.

Dual-In-Line Package

DS012644-1

Top View

Order Number DS34LV86TN, DS34LV86TM

See NS Package Number M16A or N16E

February 1997

DS34LV86T 3V Enhanced CMOS Quad Differential Line Receiver

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Supply Voltage (V

) +7V Enable Input Voltage (EN) +7V Receiver Input Voltage

: RI+, RI−)

14V

Receiver Input Voltage

: RI+, RI−)

14V

Receiver Output Voltage (RO) −0.5V to V

+ 0.5V

Receiver Output Current (RO)

25 mA

Maximum Package Power Dissipation +25˚C

M Package 1190 mW N Package 1645 mW

Derate M Package 9.8 mW/˚C above +25˚C

Derate N Package 13.9 mW/˚C above +25˚C Storage Temperature Range 65˚C to +150˚C Lead Temperature Range

Soldering (4 Seconds) +260˚C

ESD Ratings (HBM, 1.5k, 100 pF)

Receiver Inputs and Enables ≥6.5 kV Other Pins ≥2kV

Recommended Operating Conditions

Min Typ Max Units

Supply Voltage (V

) 3.0 3.3 3.6 V

Operating Free Air

Temperature (T

) −40 +25 +85 ˚C

Electrical Characteristics (Notes 2, 3)

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.

Symbol Parameter Conditions Pin Min Typ Max Units

Differential Input Threshold V

OUT=VOH

or V

RI+,

RI−

−200

17.5 +200 mV

−7V

+7V

Hysteresis VCM= 1.5V 35 mV

Minimum High Level Input Voltage

2.0 V

Minimum Low Level Input Voltage

0.8 V

Input Resistance VIN= −7V, +7V

RI+,

RI−

5.0 8.5 kΩ

(Other Input = GND)

Input Current (Other Input = 0V, Power On or V

= 0V)

= +10V 0 1.1 1.8 mA

= +3V 0 0.27 mA

= 0.5V −0.02 mA

= −3V 0 −0.43 mA

= −10V 0 −1.26 −2.2 mA

VIN=0VtoV

1µA

High Level Output Voltage IOH= −6 mA, VID= +1V

2.4 3 V

= −6 mA, VID= OPEN

High Level Output Voltage IOH= −100 µA, VID= +1V VCC− 0.1 V

= −100 µA, VID= OPEN

Low Level Output Voltage IOL= +6 mA, VID= −1V 0.13 0.5 V

Output TRI-STATE Leakage Current

VIN=VCCor GND

50 µA

EN=V

Output Short Circuit Current VO= 0V, VID≥ |200 mV| −10 −35 −70 mA

(Note 4)

Power Supply Current No Load, All RI+, RI− = Open, V

915mA

EN=V

or GND

www.national.com 2

Switching Characteristics (Notes 3, 9, 10)

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

PHL

Propagation Delay High to Low CL=15pF

(

Figures 1, 2

)

6 17.5 35 ns

PLH

Propagation DeIay Low to High 6 17.8 35 ns

Rise Time (20%to 80%) 4.1 10 ns

Fall Time (80%to 20%) 3.3 10 ns

PHZ

Disable Time CL=50pF 40 ns

PLZ

Disable Time (

Figures 3, 4

)40ns

PZH

Enable Time 40 ns

PZL

Enable Time 40 ns

SK1

Skew, |t

PHL−tPLH

|(Note 5) CL=15pF 0.3 4 ns

SK2

Skew, Pin to Pin (Note 6) 0.6 4 ns

SK3

Skew, Part to Part (Note 7) 7 17 ns

MAX

Maximum Operating Frequency CL=15pF 32 MHz (Note 8)

Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.

Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except V

Note 3: All typicals are given for: V

= +3.3V, TA= +25˚C.

Note 4: Short one output at a time to ground. Do not exceed package power dissipation ratings. Note 5: t

SK1

is the |t

PHL−tPLH

| of a channel.

Note 6: t

SK2

is the maximum skew between any two channels within a device, on either edge.

Note 7: t

SK3

is the difference in propagation delay times between any channels of any devices. This specification (maximum limit) applies to devices within V

0.1V of one another,anda DeltaT

5˚C (between devices) within the operating temperature range. This parameter is guaranteed by design and characterization.

Note 8: All channels switching, output duty cycle criteria is 40%/60%measured at 50%Input = 1V to 2V, 50%Duty Cycle, t

r/tf

≤ 5 ns. This parameter is guaranteed

by design and characterization.

Parameter Measurement Information

Note 9: Generator waveform for all tests unless otherwise specified:f=1MHz, Duty Cycle = 50%,ZO=50Ω,tr≤10 ns, tf≤ 10 ns. Note 10: C

includes probe and jig capacitance.

DS012644-2

FIGURE 1. Receiver Propagation Delay and Transition Time Test Circuit (Notes 9, 10)

DS012644-3

FIGURE 2. Receiver Propagation Delay and Transition Time Waveform (Notes 9, 10)

www.national.com3

+ 7 hidden pages