NSC DP83950BVQB-MPC, DP83950BVQB Datasheet
October 1995
DP83950B RIC Repeater Interface Controller
DP83950B RIC
TM
Repeater Interface Controller
General Description
The DP83950B Repeater Interface Controller ‘‘RIC’’ may be
used to implement an IEEE 802.3 multiport repeater unit. It
fully satisfies the IEEE 802.3 repeater specification including
the functions defined by the repeater, segment partition and
jabber lockup protection state machines.
The RIC has an on-chip phase-locked-loop (PLL) for Manchester data decoding, a Manchester encoder and an Elasticity Buffer for preamble regeneration.
Each RIC can connect to 13 cable segments via its network
interface ports. One port is fully AUI compatible and is able
to connect to an external MAU using the maximum length of
AUI cable. The other 12 ports have integrated 10BASE-T
transceivers. These transceiver functions may be bypassed
so that the RIC may be used with external transceivers, for
example DP8392 coaxial transceivers. In addition, large repeater units, containing several hundred ports may be constructed by cascading RICs together over an Inter-RIC bus.
The RIC is configurable for specific applications. It provides
port status information for LED array displays and a simple
interface for system processors. The RIC posseses multifunction counter and status flag arrays to facilitate network
statistics gathering. A serial interface, known as the Management Interface is available for the collection of data in
Managed Hub applications.
Features
Y
Compliant with the IEEE 802.3 Repeater Specification
Y
13 network connections (ports) per chip
Y
Selectable on-chip twisted-pair transceivers
Y
Cascadable for large hub applications
Y
Compatible with AUI compliant transceivers
Y
On-chip Elasticity Buffer, Manchester encoder and decoder
Y
Separate partition state machines for each port
Y
Provides port status information for LED displays including: receive, collision, partition and link status
Y
Power-up configuration options:
Repeater and Partition Specifications, Transceiver Interface, Status Display, Processor Operations
Y
Simple processor interface for repeater management
and port disable
Y
On-chip Event Counters and Event Flag Arrays
Y
Serial Management Interface to combine packet and
repeater status information together
Y
CMOS process for low power dissipation
Y
Single 5V supply
Table of Contents
1.0 SYSTEM DIAGRAM
2.0 CONNECTION DIAGRAM
3.0 PIN DESCRIPTIONS
4.0 BLOCK DIAGRAM
5.0 FUNCTIONAL DESCRIPTION
6.0 HUB MANAGEMENT SUPPORT
7.0 PORT LOGIC FUNCTIONS
8.0 RIC REGISTER DESCRIPTIONS
9.0 AC AND DC SPECIFICATIONS
10.0 AC TIMING TEST CONDITIONS
11.0 PHYSICAL DIMENSIONS
1.0 System Diagram
Simple RIC Hub
TL/F/11096– 1
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
TM
RIC
and SONICTMare trademarks of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M16/Printed in U. S. A.
TL/F/11096
2.0 Connection DiagramÐ160 Pin PQFP Package
Pin Table (12 T.P. Portsa1 AUI Bottom View)
Pin Name Pin No.
b
TXO12P
a
TXO12
b
TXO12
a
TXO12P
b
RXI12
a
RXI12
V
CC
GND 33
b
RXI11
a
RXI11
a
TXO11P
b
TXO11
a
TXO11
b
TXO11P
V
CC
GND 25
b
TXO10P
a
TXO10
b
TXO10
a
TXO10P
b
RXI10
a
RXI10
V
CC
GND 17
b
RXI9
a
RXI9
a
TXO9P
b
TXO9
a
TXO9
b
TXO9P
V
CC
GND 9
b
TXO8P
a
TXO8
b
TXO8
a
TXO8P
b
RXI8
a
RXI8
V
CC
GND 1
Note: NCeNo Connect
40
39
38
37
36
35
34
32
31
30
29
28
27
26
24
23
22
21
20
19
18
16
15
14
13
12
11
10
8
7
6
5
4
3
2
Pin Name Pin No.
NC 160
b
RXI7
RXI7
TXO7P
TXO7
TXO7
TXO7P
V
CC
a
a
b
a
b
159
158
157
156
155
154
153
GND 152
b
TXO6P
TXO6
TXO6
TXO6P
RXI6
RXI6
V
CC
a
b
a
b
a
151
150
149
148
147
146
145
GND 144
b
RXI5
RXI5
TXO5P
TXO5
TXO5
TXO5P
V
CC
a
a
b
a
b
143
142
141
140
139
138
137
GND 136
b
TXO4P
TXO4
TXO4
TXO4P
RXI4
RXI4
V
CC
a
b
a
b
a
135
134
133
132
131
130
129
GND 128
b
RXI3
RXI3
TXO3P
TXO3
TXO3
TXO3P
a
a
b
a
b
127
126
125
124
123
122
NC 121
Pin Name Pin No.
V
CC
GND 119
b
TXO2P
a
TXO2
b
TXO2
a
TXO2P
b
RXI2
a
RXI2
V
CC
GND 111
b
RX1
a
RX1
b
CD1
a
CD1
b
TX1
a
TX1
V
CC
GND 103
V
CC
GND 101
CLKIN 100
RA4 99
RA3 98
RA2 97
RA1 96
RA0 95
V
CC
GND 93
MLOAD 92
CDEC 91
WR 90
RD 89
D7 88
D6 87
D5 86
D4 85
D3 84
D2 83
D1 82
D0 81
120
118
117
116
115
114
113
112
110
109
108
107
106
105
104
102
94
Pin Name Pin No.
V
CC
80
GND 79
IRC 78
IRE 77
IRD 76
COLN 75
V
CC
74
GND 73
PKEN 72
RXMPLL 71
BUFEN 70
RDY 69
ELI 68
RTI 67
STR1 66
V
CC
65
GND 64
STR0 63
ACTND 62
ANYXND 61
ACKO 60
MRXC 59
MEN 58
MRXD 57
MCRS 56
V
CC
55
GND 54
ACKI 53
ACTNS 52
ANYXNS 51
PCOMP 50
NC 49
b
RXI13
RXI13
TXO13P
TXO13
TXO13
TXO13P
V
CC
a
a
b
a
b
48
47
46
45
44
43
42
GND 41
2
2.0 Connection DiagramÐ160 Pin PQFP Package (Continued)
Ports 2–13 TP
Port 1 AUI
Order Number DP83950BVQB
See NS Package Number VUL160A
3
TL/F/11096– 42
2.0 Connection DiagramÐ160 Pin PQFP Package (Continued)
a
6–13 T.P. Ports)
Pin Name Pin No.
V
CC
GND 119
b
TX2
a
TX2
b
CD2
a
CD2
a
RX2
b
RX2
V
CC
GND 111
b
RX1
a
RX1
b
CD1
a
CD1
b
TX1
a
TX1
V
CC
GND 103
V
CC
GND 101
CLKIN 100
RA4 99
RA3 98
RA2 97
RA1 96
RA0 95
V
CC
GND 93
MLOAD 92
CDEC 91
WR 90
RD 89
D7 88
D6 87
D5 86
D4 85
D3 84
D2 83
D1 82
D0 81
120
118
117
116
115
114
113
112
110
109
108
107
106
105
104
102
94
Pin Name Pin No.
b
TXO12P
a
TXO12
b
TXO12
a
TXO12P
b
RXI12
a
RXI12
V
CC
GND 33
b
RXI11
a
RXI11
a
TXO11P
b
TXO11
a
TXO11
b
TXO11P
V
CC
GND 25
b
TXO10P
a
TXO10
b
TXO10
a
TXO10P
b
RXI10
a
RXI10
V
CC
GND 17
b
RXI9
a
RXI9
a
TXO9P
b
TXO9
a
TXO9
b
TXO9P
V
CC
GND 9
b
TXO8P
a
TXO8
b
TXO8
a
TXO8P
b
RXI8
a
RXI8
V
CC
GND 1
Note: NCeNo Connect
Pin Table (1–5 AUI
Pin Name Pin No.
40
39
38
37
36
35
34
32
31
30
29
28
27
26
24
23
22
21
20
19
18
16
15
14
13
12
11
10
8
7
6
5
4
3
2
NC 160
b
RXI7
RXI7
TXO7P
TXO7
TXO7
TXO7P
V
CC
a
a
b
a
b
159
158
157
156
155
154
153
GND 152
b
TXO6P
TXO6
TXO6
TXO6P
RXI6
RXI6
V
CC
a
b
a
b
a
151
150
149
148
147
146
145
GND 144
a
RX5
RX5
CD5
CD5
TX5
TX5
V
CC
b
a
b
a
b
143
142
141
140
139
138
137
GND 136
b
TX4
TX4
CD4
CD4
RX4
RX4
V
CC
a
b
a
a
b
135
134
133
132
131
130
129
GND 128
a
RX3
RX3
CD3
CD3
TX3
TX3
b
a
b
a
b
127
126
125
124
123
122
NC 121
Pin Name Pin No.
V
CC
80
GND 79
IRC 78
IRE 77
IRD 76
COLN 75
V
CC
74
GND 73
PKEN 72
RXMPLL 71
BUFEN 70
RDY 69
ELI 68
RTI 67
STR1 66
V
CC
65
GND 64
STR0 63
ACTND 62
ANYXND 61
ACKO 60
MRXC 59
MEN 58
MRXD 57
MCRS 56
V
CC
55
GND 54
ACKI 53
ACTNS 52
ANYXNS 51
PCOMP 50
NC 49
b
RXI13
RXI13
TXO13P
TXO13
TXO13
TXO13P
V
CC
a
a
b
a
b
48
47
46
45
44
43
42
GND 41
4
2.0 Connection DiagramÐ160 Pin PQFP Package (Continued)
Ports 6–13 TP
Ports 1–5 AUI
Order Number DP83950BVQB
See NS Package Number VUL160A
5
TL/F/11096– 43
2.0 Connection DiagramÐ160 Pin PQFP Package (Continued)
a
8–13 T.P. Ports)
Pin Name Pin No.
V
CC
GND 119
b
TX2
a
TX2
b
CD2
a
CD2
a
RX2
b
RX2
V
CC
GND 111
b
RX1
a
RX1
b
CD1
a
CD1
b
TX1
a
TX1
V
CC
GND 103
V
CC
GND 101
CLKIN 100
RA4 99
RA3 98
RA2 97
RA1 96
RA0 95
V
CC
GND 93
MLOAD 92
CDEC 91
WR 90
RD 89
D7 88
D6 87
D5 86
D4 85
D3 84
D2 83
D1 82
D0 81
120
118
117
116
115
114
113
112
110
109
108
107
106
105
104
102
94
Pin Name Pin No.
b
TXO12P
a
TXO12
b
TXO12
a
TXO12P
b
RXI12
a
RXI12
V
CC
GND 33
b
RXI11
a
RXI11
a
TXO11P
b
TXO11
a
TXO11
b
TXO11P
V
CC
GND 25
b
TXO10P
a
TXO10
b
TXO10
a
TXO10P
b
RXI10
a
RXI10
V
CC
GND 17
b
RXI9
a
RXI9
a
TXO9P
b
TXO9
a
TXO9
b
TXO9P
V
CC
GND 9
b
TXO8P
a
TXO8
b
TXO8
a
TXO8P
b
RXI8
a
RXI8
V
CC
GND 1
Note: NCeNo Connect
Pin Table (1–7 AUI
Pin Name Pin No.
40
39
38
37
36
35
34
32
31
30
29
28
27
26
24
23
22
21
20
19
18
16
15
14
13
12
11
10
8
7
6
5
4
3
2
NC 160
a
RX7
RX7
CD7
CD7
TX7
TX7
V
CC
b
a
b
a
b
159
158
157
156
155
154
153
GND 152
b
TX6
TX6
CD6
CD6
RX6
RX6
V
CC
a
b
a
a
b
151
150
149
148
147
146
145
GND 144
a
RX5
RX5
CD5
CD5
TX5
TX5
V
CC
b
a
b
a
b
143
142
141
140
139
138
137
GND 136
b
TX4
TX4
CD4
CD4
RX4
RX4
V
CC
a
b
a
a
b
135
134
133
132
131
130
129
GND 128
a
RX3
RX3
CD3
CD3
TX3
TX3
b
a
b
a
b
127
126
125
124
123
122
NC 121
Pin Name Pin No.
V
CC
80
GND 79
IRC 78
IRE 77
IRD 76
COLN 75
V
CC
74
GND 73
PKEN 72
RXMPLL 71
BUFEN 70
RDY 69
ELI 68
RTI 67
STR1 66
V
CC
65
GND 64
STR0 63
ACTND 62
ANYXND 61
ACKO 60
MRXC 59
MEN 58
MRXD 57
MCRS 56
V
CC
55
GND 54
ACKI 53
ACTNS 52
ANYXNS 51
PCOMP 50
NC 49
b
RXI13
RXI13
TXO13P
TXO13
TXO13
TXO13P
V
CC
a
a
b
a
b
48
47
46
45
44
43
42
GND 41
6
2.0 Connection DiagramÐ160 Pin PQFP Package (Continued)
Ports 8–13 TP
Ports 1–7 AUI
Order Number DP83950BVQB
See NS Package Number VUL160A
7
TL/F/11096– 44
2.0 Connection DiagramÐ160 Pin PQFP Package (Continued)
Pin Table (All AUI Ports)
Pin Name Pin No.
b
TX12
a
TX12
b
CD12
a
CD12
a
RX12
b
RX12
V
CC
GND 33
a
RX11
b
RX11
a
CD11
b
CD11
a
TX11
b
TX11
V
CC
GND 25
b
TX10
a
TX10
b
CD10
a
CD10
a
RX10
b
RX10
V
CC
GND 17
a
RX9
b
RX9
a
CD9
b
CD9
a
TX9
b
TX9
V
CC
GND 9
b
TX8
a
TX8
b
CD8
a
CD8
a
RX8
b
RX8
V
CC
GND 1
Note: NCeNo Connect
40
39
38
37
36
35
34
32
31
30
29
28
27
26
24
23
22
21
20
19
18
16
15
14
13
12
11
10
8
7
6
5
4
3
2
Pin Name Pin No.
NC 160
a
RX7
RX7
CD7
CD7
TX7
TX7
V
CC
b
a
b
a
b
159
158
157
156
155
154
153
GND 152
b
TX6
TX6
CD6
CD6
RX6
RX6
V
CC
a
b
a
a
b
151
150
149
148
147
146
145
GND 144
a
RX5
RX5
CD5
CD5
TX5
TX5
V
CC
b
a
b
a
b
143
142
141
140
139
138
137
GND 136
b
TX4
TX4
CD4
CD4
RX4
RX4
V
CC
a
b
a
a
b
135
134
133
132
131
130
129
GND 128
a
RX3
RX3
CD3
CD3
TX3
TX3
b
a
b
a
b
127
126
125
124
123
122
NC 121
Pin Name Pin No.
V
CC
120
GND 119
b
TX2
TX2
CD2
CD2
RX2
RX2
V
CC
a
b
a
a
b
118
117
116
115
114
113
112
GND 111
b
RX1
RX1
CD1
CD1
TX1
TX1
V
CC
a
b
a
b
a
110
109
108
107
106
105
104
GND 103
V
CC
102
GND 101
CLKIN 100
RA4 99
RA3 98
RA2 97
RA1 96
RA0 95
V
CC
94
GND 93
MLOAD 92
CDEC 91
WR 90
RD 89
D7 88
D6 87
D5 86
D4 85
D3 84
D2 83
D1 82
D0 81
Pin Name Pin No.
V
CC
80
GND 79
IRC 78
IRE 77
IRD 76
COLN 75
V
CC
74
GND 73
PKEN 72
RXMPLL 71
BUFEN 70
RDY 69
ELI 68
RTI 67
STR1 66
V
CC
65
GND 64
STR0 63
ACTND 62
ANYXND 61
ACKO 60
MRXC 59
MEN 58
MRXD 57
MCRS 56
V
CC
55
GND 54
ACKI 53
ACTNS 52
ANYXNS 51
PCOMP 50
NC 49
a
RX13
RX13
CD13
CD13
TX13
TX13
V
CC
b
a
b
a
b
48
47
46
45
44
43
42
GND 41
8
2.0 Connection DiagramÐ160 Pin PQFP Package (Continued)
All AUI Ports
Order Number DP83950BVQB
See NS Package Number VUL160A
9
TL/F/11096– 45
2.0 Connection DiagramÐ160 Pin PGA Package (Continued)
a
1 AUI Bottom View)
Pin Name Pin No.
V
CC
S1
GND P4
b
TXO2P
TXO2
TXO2
TXO2P
RXI2
RXI2
V
CC
a
b
a
b
a
S2
S3
R4
P5
R5
S4
S5
GND S6
b
RX1
RX1
CD1
CD1
TX1
TX1
V
CC
a
b
a
b
a
P6
R6
S7
R7
P7
P8
R8
GND S8
V
CC
S9
GND R9
CLKIN P9
RA4 S10
RA3 R10
RA2 S11
RA1 P10
RA0 R11
V
CC
S12
GND R12
MLOAD P11
CDEC S13
WR R13
RD S14
D7 P12
D6 R14
D5 S15
D4 P13
D3 P14
D2 R15
D1 S16
D0 R16
Pin Name Pin No.
b
TXO12P
a
TXO12
b
TXO12
a
TXO12P
b
RXI12
a
RXI12
V
CC
GND C11
b
RXI11
a
RXI11
a
TXO11P
b
TXO11
a
TXO11
b
TXO11P
V
CC
GND B9
b
TXO10P
a
TXO10
b
TXO10
a
TXO10P
b
RXI10
a
RXI10
V
CC
GND A7
b
RXI9
a
RXI9
a
TXO9P
b
TXO9
a
TXO9
b
TXO9P
V
CC
GND B4
b
TXO8P
a
TXO8
b
TXO8
a
TXO8P
b
RXI8
a
RXI8
V
CC
GND D3
Note: NCeNo Connect
A15
A14
B14
C13
B13
A13
C12
B12
B11
A12
A11
C10
A10
B10
C9
C8
A9
A8
B8
B7
C7
A6
B6
C6
C5
B5
A5
A4
C4
A3
C3
D4
B3
B2
A2
Pin Table (12 T.P. Ports
Pin Name Pin No.
b
RXI7
RXI7
TXO7P
TXO7
TXO7
TXO7P
V
CC
a
a
b
a
b
C2
A1
B1
D2
E3
F3
C1
GND D1
b
TXO6P
TXO6
TXO6
TXO6P
RXI6
RXI6
a
b
a
b
a
E2
G3
F2
E1
G2
H3
NC F1
NC G1
V
CC
H2
GND J3
b
RXI5
RXI5
TXO5P
TXO5
TXO5
TXO5P
V
CC
a
a
b
a
b
J2
H1
J1
K1
K3
K2
L1
GND L2
b
TXO4P
TXO4
TXO4
TXO4P
RXI4
RXI4
V
CC
a
b
a
b
a
M1
L3
M2
N1
N2
M3
P1
GND R1
b
RXI3
RXI3
TXO3P
TXO3
TXO3
TXO3P
a
a
b
a
b
P2
N3
P3
R2
N4
R3
Pin Name Pin No.
V
CC
N13
GND P15
IRC N14
IRE P16
IRD N15
COLN N16
V
CC
M15
GND M14
PKEN L14
RXM L15
BUFEN M16
RDY L16
ELI K16
RTI K14
STR1 K15
V
CC
J16
GND J15
STR0 J14
ACTND H16
ANYXND H15
ACKO H14
MRXC G14
MEN G15
MRXD G16
MCRS F16
V
CC
F14
GND F15
ACKI E15
ACTNS E14
ANYXNS E16
PCOMP D16
b
RXI13
RXI13
TXO13P
TXO13
TXO13
TXO13P
V
CC
a
b
a
D15
D14
a
C16
C15
B16
b
B15
D13
GND C14
10
2.0 Connection DiagramÐ160 Pin PGA Package (Continued)
Bottom View
a
1 AUI
2–13 T.P. Ports
Order Number DP83950BNU
See NS Package Number UP159A
11
TL/F/11096– 2
2.0 Connection DiagramÐ160 Pin PGA Package (Continued)
a
6–13 T.P. Ports)
Pin Name Pin No.
V
CC
GND P4
b
TX2
a
TX2
b
CD2
a
CD2
a
RX2
b
RX2
V
CC
GND S6
b
RX1
a
RX1
b
CD1
a
CD1
b
TX1
a
TX1
V
CC
GND S8
V
CC
GND R9
CLKIN P9
RA4 S10
RA3 R10
RA2 S11
RA1 P10
RA0 R11
V
CC
GND R12
MLOAD P11
CDEC S13
WR R13
RD S14
D7 P12
D6 R14
D5 S15
D4 P13
D3 P14
D2 R15
D1 R16
D0 R16
S1
S2
S3
R4
P5
R5
S4
S5
P6
R6
S7
R7
P7
P8
R8
S9
S12
Pin Name Pin No.
b
TXO12P
a
TXO12
b
TXO12
a
TXO12P
b
RXI12
a
RXI12
V
CC
GND C11
b
RXI11
a
RXI11
a
TXO11P
b
TXO11
a
TXO11
b
TXO11P
V
CC
GND B9
b
TXO10P
a
TXO10
b
TXO10
a
TXO10P
b
RXI10
a
RXI10
V
CC
GND A7
b
RXI9
a
RXI9
a
TXO9P
b
TXO9
a
TXO9
b
TXO9P
V
CC
GND B4
b
TXO8P
a
TXO8
b
TXO8
a
TXO8P
b
RXI8
a
RXI8
V
CC
GND D3
Note: NCeNo Connect
A15
A14
B14
C13
B13
A13
C12
B12
B11
A12
A11
C10
A10
B10
C9
C8
A9
A8
B8
B7
C7
A6
B6
C6
C5
B5
A5
A4
C4
A3
C3
D4
B3
B2
A2
Pin Table (1–5 AUI
Pin Name Pin No.
b
RXI7
RXI7
TXO7P
TXO7
TXO7
TXO7P
V
CC
a
a
b
a
b
C2
A1
B1
D2
E3
F3
C1
GND D1
b
TXO6P
TXO6
TXO6
TXO6P
RXI6
RXI6
a
b
a
b
a
E2
G3
F2
E1
G2
H3
NC F1
NC G1
V
CC
H2
GND J3
a
RX5
RX5
CD5
CD5
TX5
TX5
V
CC
b
a
b
a
b
J2
H1
J1
K1
K3
K2
L1
GND L2
b
TX4
TX4
CD4
CD4
RX4
RX4
V
CC
a
b
a
a
b
M1
L3
M2
N1
N2
M3
P1
GND R1
a
RX3
RX3
CD3
CD3
TX3
TX3
b
a
b
a
b
P2
N3
P3
R2
N4
R3
Pin Name Pin No.
V
CC
N13
GND P15
IRC N14
IRE P16
IRD N15
COLN N16
V
CC
M15
GND M14
PKEN L14
RXM L15
BUFEN M16
RDY L16
ELI K16
RTI K14
STR1 K15
V
CC
J16
GND J15
STR0 J14
ACTND H16
ANYXND H15
ACKO H14
MRXC G14
MEN G15
MRXD G16
MCRS F16
V
CC
F14
GND F15
ACKI E15
ACTNS E14
ANYXNS E16
PCOMP D16
b
RXI13
RXI13
TXO13P
TXO13
TXO13
TXO13P
V
CC
a
b
a
D15
D14
a
C16
C15
B16
b
B15
D13
GND C14
12
2.0 Connection DiagramÐ160 Pin PGA Package (Continued)
Bottom View
a
1–5 AUI
Order Number DP83950BNU
See NS Package Number UP159A
6–13 T.P. Ports
13
TL/F/11096– 3
2.0 Connection DiagramÐ160 Pin PGA Package (Continued)
a
8–13 T.P. Ports)
Pin Name Pin No.
V
CC
GND P4
b
TX2
a
TX2
b
CD2
a
CD2
a
RX2
b
RX2
V
CC
GND S6
b
RX1
a
RX1
b
CD1
a
CD1
b
TX1
a
TX1
V
CC
GND S8
V
CC
GND R9
CLKIN P9
RA4 S10
RA3 R10
RA2 S11
RA1 P10
RA0 R11
V
CC
GND R12
MLOAD P11
CDEC S13
WR R13
RD S14
D7 P12
D6 R14
D5 S15
D4 P13
D3 P14
D2 R15
D1 S16
D0 R16
S1
S2
S3
R4
P5
R5
S4
S5
P6
R6
S7
R7
P7
P8
R8
S9
S12
Pin Name Pin No.
b
TXO12P
a
TXO12
b
TXO12
a
TXO12P
b
RXI12
a
RXI12
V
CC
GND C11
b
RXI11
a
RXI11
a
TXO11P
b
TXO11
a
TXO11
b
TXO11P
V
CC
GND B9
b
TXO10P
a
TXO10
b
TXO10
a
TXO10P
b
RXI10
a
RXI10
V
CC
GND A7
b
RXI9
a
RXI9
a
TXO9P
b
TXO9
a
TXO9
b
TXO9P
V
CC
GND B4
b
TXO8P
a
TXO8
b
TXO8
a
TXO8P
b
RXI8
a
RXI8
V
CC
GND D3
Note: NCeNo Connect
A15
A14
B14
C13
B13
A13
C12
B12
B11
A12
A11
C10
A10
B10
C9
C8
A9
A8
B8
B7
C7
A6
B6
C6
C5
B5
A5
A4
C4
A3
C3
D4
B3
B2
A2
Pin Table (1–7 AUI
Pin Name Pin No.
a
RX7
RX7
CD7
CD7
TX7
TX7
V
CC
b
a
b
a
b
C2
A1
B1
D2
E3
F3
C1
GND D1
b
TX6
TX6
CD6
CD6
RX6
RX6
a
b
a
a
b
E2
G3
F2
E1
G2
H3
NC F1
NC G1
V
CC
H2
GND J3
a
RX5
RX5
CD5
CD5
TX5
TX5
V
CC
b
a
b
a
b
J2
H1
J1
K1
K3
K2
L1
GND L2
b
TX4
TX4
CD4
CD4
RX4
RX4
V
CC
a
b
a
a
b
M1
L3
M2
N1
N2
M3
P1
GND R1
a
RX3
RX3
CD3
CD3
TX3
TX3
b
a
b
a
b
P2
N3
P3
R2
N4
R3
Pin Name Pin No.
V
CC
N13
GND P15
IRC N14
IRE P16
IRD N15
COLN N16
V
CC
M15
GND M14
PKEN L14
RXM L15
BUFEN M16
RDY L16
ELI K16
RTI K14
STR1 K15
V
CC
J16
GND J15
STR0 J14
ACTND H16
ANYXND H15
ACKO H14
MRXC G14
MEN G15
MRXD G16
MCRS F16
V
CC
F14
GND F15
ACKI E15
ACTNS E14
ANYXNS E16
PCOMP D16
b
RXI13
RXI13
TXO13P
TXO13
TXO13
TXO13P
V
CC
a
b
a
D15
D14
a
C16
C15
B16
b
B15
D13
GND C14
14
2.0 Connection DiagramÐ160 Pin PGA Package (Continued)
Bottom View
a
1–7 AUI
Order Number DP83950BNU
See NS Package Number UP159A
8–13 T.P. Ports
15
TL/F/11096– 4
2.0 Connection DiagramÐ160 Pin PGA Package (Continued)
Pin Table ( All AUI Ports)
Pin Name Pin No.
b
TX12
a
TX12
b
CD12
a
CD12
a
RX12
b
RX12
V
CC
GND C11
a
RX11
b
RX11
a
CD11
b
CD11
a
TX11
b
TX11
V
CC
GND B9
b
TX10
a
TX10
b
CD10
a
CD10
a
RX10
b
RX10
V
CC
GND A7
a
RX9
b
RX9
a
CD9
b
CD9
a
TX9
b
TX9
V
CC
GND B4
b
TX8
a
TX8
b
CD8
a
CD8
a
RX8
b
RX8
V
CC
GND D3
Note: NCeNo Connect
A15
A14
B14
C13
B13
A13
C12
B12
B11
A12
A11
C10
A10
B10
C9
C8
A9
A8
B8
B7
C7
A6
B6
C6
C5
B5
A5
A4
C4
A3
C3
D4
B3
B2
A2
Pin Name Pin No.
a
RX7
RX7
CD7
CD7
TX7
TX7
V
CC
b
a
b
a
b
C2
A1
B1
D2
E3
F3
C1
GND D1
b
TX6
TX6
CD6
CD6
RX6
RX6
a
b
a
a
b
E2
G3
F2
E1
G2
H3
NC F1
NC G1
V
CC
H2
GND J3
a
RX5
RX5
CD5
CD5
TX5
TX5
V
CC
b
a
b
a
b
J2
H1
J1
K1
K3
K2
L1
GND L2
b
TX4
TX4
CD4
CD4
RX4
RX4
V
CC
a
b
a
a
b
M1
L3
M2
N1
N2
M3
P1
GND R1
a
RX3
RX3
CD3
CD3
TX3
TX3
b
a
b
a
b
P2
N3
P3
R2
N4
R3
Pin Name Pin No.
V
CC
S1
GND P4
b
TX2
TX2
CD2
CD2
RX2
RX2
V
CC
a
b
a
a
b
S2
S3
R4
P5
R5
S4
S5
GND S6
b
RX1
RX1
CD1
CD1
TX1
TX1
V
CC
a
b
a
b
a
P6
R6
S7
R7
P7
P8
R8
GND S8
V
CC
S9
GND R9
CLKIN P9
RA4 S10
RA3 R10
RA2 S11
RA1 P10
RA0 R11
V
CC
S12
GND R12
MLOAD P11
CDEC S13
WR R13
RD S14
D7 P12
D6 R14
D5 S15
D4 P13
D3 P14
D2 R15
D1 S16
D0 R16
Pin Name Pin No.
V
CC
N13
GND P15
IRC N14
IRE P16
IRD N15
COLN N16
V
CC
M15
GND M14
PKEN L14
RXM L15
BUFEN M16
RDY L16
ELI K16
RTI K14
STR1 K15
V
CC
J16
GND J15
STR0 J14
ACTND H16
ANYXND H15
ACKO H14
MRXC G14
MEN G15
MRXD G16
MCRS F16
V
CC
F14
GND F15
ACKI E15
ACTNS E14
ANYXNS E16
PCOMP D16
a
RX13
RX13
CD13
CD13
TX13
TX13
V
CC
b
a
b
a
b
D15
D14
C16
C15
B16
B15
D13
GND C14
16
2.0 Connection DiagramÐ160 Pin PGA Package (Continued)
Bottom View
All AUI Ports
Order Number DP83950BNU
See NS Package Number UP159A
17
TL/F/11096– 5
3.0 Pin Descriptions
Pin Pin Driver
No. Name Type
NETWORK INTERFACE PINS (On-Chip Transceiver Mode)
RXI2bto RXI13
RXI2ato RXI13
TXOP2bto TXOP13
TXO2bto TXO13
TXO2ato TXO13
TXOP2ato TXOP13
a
CD1
b
CD1
a
RX1
b
RX1
a
TX1
b
TX1
b
a
b
b
a
a
TP I Twisted Pair Receive Input Negative
TP I Twisted Pair Receive Input Positive
TT O Twisted Pair Pre-emphasis Transmit Output Negative
TT O Twisted Pair Transmit Output Negative
TT O Twisted Pair Transmit Output Positive
TT O Twisted Pair Pre-emphasis Transmit Output Positive
AL I AUI Collision Detect Input Positive
AL I AUI Collision Detect Input Negative
AL I AUI Receive Input Positive
AL I AUI Receive Input Negative
AD O AUI Transmit Output Positive
AD O AUI Transmit Output Negative
NETWORK INTERFACE PINS (External Transceiver Mode AUI Signal Level Compatibility Selected)
TX2ato TX13
TX2bto TX13
CD2ato CD13
CD2bto CD13
RX2ato RX13
RX2bto RX13
a
CD1
b
CD1
a
RX1
b
RX1
a
TX1
b
TX1
Note: ADeAUI level and Drive compatible, TPeTwisted Pair interface compatible, ALeAUI Level compatible, TTeTTL compatible, IeInput, OeOutput.
a
b
a
b
a
b
AL O Transmit Output Positive
AL O Transmit Output Negative
AL I Collision Input Positive
AL I Collision Input Negative
AL I Receive Input Positive
AL I Receive Input Negative
AL I AUI Collision Detect Input Positive
AL I AUI Collision Detect Input Negative
AL I AUI Receive Input Positive
AL I AUI Receive Input Negative
AD O AUI Transmit Output Positive
AD O AUI Transmit Output Negative
I/O Description
18
3.0 Pin Descriptions (Continued)
Pin Pin Driver
No. Name Type
PROCESSOR BUS PINS
RA0–RA4 TT I REGISTER ADDRESS INPUTS: These five pins are used to select a register to be read or
STR0 C O DISPLAY UPDATE STROBE 0
STR1 C O DISPLAY UPDATE STROBE 1
D0–D7 TT B, Z DATA BUS
BUFEN COBUFFER ENABLE: This output controls the TRI-STATEÉoperation of the bus transceiver
RDY C O DATA READY STROBE: The falling edge of this signal during a read cycle indicates that data
ELI COEVENT LOGGING INTERRUPT: A low level on the ELI output indicates the RIC’s hub
RTI COREAL TIME INTERRUPT: A low level on the RTI output indicates the RIC’s real time (packet
CDEC TT I COUNTER DECREMENT: A low level on the CDEC input strobe decrements all of the RIC’s
WR TT I WRITE STROBE: Strobe from the CPU used to write an internal register defined by the
RD TT I READ STROBE: Strobe from the CPU used to read an internal register defined by the RA0 –
MLOAD TT I DEVICE RESET AND MODE LOAD: When this input is low all of the RIC’s state machines,
I/O Description
written. The state of these inputs are ignored when the read, write and mode load input strobes
are high. (Even under these conditions these inputs must not be allowed to float at an
undefined logic state).
Maximum Display Mode: This signal controls the latching of display data for network ports 1
to 7 into the off chip display latches.
Minimum Display Mode: This signal controls the latching of display data for the RIC into the
off chip display latch.
During processor access cycles (read or write is asserted) this signal is inactive (high).
Maximum Display Mode: This signal controls the latching of display data for network ports 8
to 13 into the off chip display latches.
Minimum Display Mode: No operation
During processor access cycles (read or write is asserted) this signal is inactive (high).
Display Update Cycles: These pins become outputs providing display data and port address
information. Address information only available in Maximum Display mode.
Processor Access Cycles: Data input or output is performed via these pins. The read, write
and mode load inputs control the direction of the signals.
Note: The data pins remain in their display update function, i.e., asserted as outputs unless either the read or
write strobe is asserted.
which provides the interface between the RIC’s data pins and the processor’s data bus.
Note: The buffer enable output indicates the function of the data pins. When it is high they are performing
display update cycles, when it is low a processor access or mode load cycle is occurring.
is stable and valid for sampling. In write cycles the falling edge of RDY
data has been latched by the RIC. Therefore data must have been available and stable for this
operation to be successful.
management logic requires CPU attention. The interrupt is cleared by accessing the Port Event
Recording register or Event Counter that produced it. All interrupt sources may be masked.
specific) interrupt logic requires CPU attention. The interrupt is cleared by reading the Real
Time Interrupt Status register. All interrupt sources may be masked.
Port Event Counters by one. This input is internally synchronized and if necessary the
operation of the signal is delayed if there is a simultaneous internally generated counting
operation.
RA0–RA4 inputs.
RA4 inputs.
counters and network ports are reset and held inactive. On the rising edge of MLOAD
levels present on the D0–7 pins and RA0 –RA4 inputs are latched into the RIC’s configuration
registers. The rising edge of MLOAD
also signals the beginning of the display test operation.
denotes that the write
the logic
19
3.0 Pin Descriptions (Continued)
Pin Pin Driver
No. Name Type
INTER-RIC BUS PINS
ACKI TT I ACKNOWLEDGE INPUT: Input to the network ports’ arbitration chain.
ACKO TT O ACKNOWLEDGE OUTPUT: Output from the network ports’ arbitration chain.
IRD TT B, Z INTER-RIC DATA: When asserted as an output this signal provides a serial data stream in NRZ
IRE TT B, Z INTER-RIC ENABLE: When asserted as an output this signal provides an activity framing enable
IRC TT B, Z INTER-RIC CLOCK: When asserted as an output this signal provides a clock signal for the serial
COLN TT B, Z COLLISION ON PORT N: This denotes that a collision is occurring on the port receiving the
PKEN C O PACKET ENABLE: This output acts as an active high enable for an external bus transceiver (if
CLKIN TT I 40 MHz CLOCKINPUT: This input is used to generate the RIC’s timing reference for the state
ACTND OD O ACTIVITY ON PORT NDRIVE: This output is active when the RIC is receiving data or collision
ACTNS TT I ACTIVITY ON PORT NSENSE: This input senses when this or another RIC in a multi-RIC
ANYXND OD O ACTIVITY ON ANY PORT EXCLUDING PORT NDRIVE: This output is active when a RIC is
ANYXNS TT I ACTIVITY ON ANY PORT EXCLUDING PORT NSENSE: This input senses when this RIC or
I/O Description
format. The signal is asserted by a RIC when it is receiving data from one of its network
segments. The default condition of this signal is to be an input. In this state it may be driven by
other devices on the Inter-RIC bus.
for the serial data stream. The signal is asserted by a RIC when it is receiving data from one of
its network segments. The default condition of this signal is to be an input. In this state it may be
driven by other devices on the Inter-RIC bus.
data stream. Data (IRD) is changed on the falling edge of the clock. The signal is asserted by a
RIC when it is receiving data from one of its network segments. The default condition of this
signal is to be an input. When an input IRD is sampled on the rising edge of the clock. In this
state it may be driven by other devices on the Inter-RIC bus.
data packet. The default condition of this signal is to be an input. In this state it may be driven by
other devices on the Inter-RIC bus.
required) for the IRE, IRC IRD and COLN signals. When high the bus transceiver should be
transmitting on to the bus, i.e., this RIC is driving the IRD, IRE, IRC and COLN bus lines. When
low the bus transceiver should receive from the bus.
machines, and phase lock loop decoder.
information from one of its network segments.
system is receiving data or collision information.
experiencing a transmit collision or multiple ports have active collisions on their network
segments.
other RICs in a multi-RIC system are experiencing transmit collisions or multiple ports have
active collisions on their network segments.
20
3.0 Pin Descriptions (Continued)
Pin Pin Driver
No. Name Type
MANAGEMENT BUS PINS
MRXC TT O, Z MANAGEMENT RECEIVE CLOCK: When asserted this signal provides a clock signal for the
MCRS TT B, Z MANAGEMENT CARRIERSENSE: When asserted this signal provides an activity framing
MRXD TT O, Z MANAGEMENT RECEIVE DATA: When asserted this signal provides a serial data stream in NRZ
MEN C O MANAGEMENT BUS OUTPUT ENABLE: This output acts as an active high enable for an
PCOMP TT I PACKET COMPRESS: This input is used to activate the RIC’s packet compress logic. A low level
POWER AND GROUND PINS
V
CC
GND Negative Supply
EXTERNAL DECODER PINS
RXM TT O RECEIVE DATA MANCHESTER FORMAT: This output makes the data, in Manchester format,
Note: TTeTTL compatible, BeBi-directional, CeCMOS compatible, ODeOpen Drain, IeInput, OeOutput, ZeTRI-STATE
I/O Description
MRXD serial data stream. The MRXD signal is changed on the falling edge of this clock. The
signal is asserted when a RIC is receiving data from one of its network segements. Otherwise the
signal is inactive.
enable for the serial output data stream (MRXD). The signal is asserted when a RIC is receiving
data from one of its network segments. Otherwise the signal is an input.
format. The data stream is made up of the data packet and RIC status information. The signal is
asserted when a RIC is receiving data from one of its network segments. Otherwise the signal is
inactive.
external bus transceiver (if required) for the MRXC, MCRS and MRXD signals. When high the bus
transceiver should be transmitting on to the bus.
on this signal when MCRS is active will cause that packet to be compressed. If PCOMP
low all packets are compressed, if PCOMP
Positive Supply
received by port N available for test purposes. If not used for testing this pin should be left open.
is tied high packet compression is inhibited.
is tied
21
4.0 Block Diagram
TL/F/11096– 6
FIGURE 5.1
22
5.0 Functional Description
The I.E.E.E. repeater specification details a number of functions a repeater system must perform. These requirements
allied with a need for the implementation to be multiport
strongly favors the choice of a modular design style. In such
a design, functionality is split between those tasks common
to all data channels and those exclusive to each individual
channel. The RIC follows this approach, certain functional
blocks are replicated for each network attachment, (also
known as a repeater port), and others are shared. The following section briefly describes the functional blocks in the
RIC.
5.1 OVERVIEW OF RIC FUNCTIONS
Segment Specific Block: Network Port
As shown in the Block Diagram, the segment specific blocks
consist of:
1. One or more physical layer interfaces.
2. A logic block required for performing repeater operations
upon that particular segment. This is known as the ‘‘port’’
logic since it is the access ‘‘port’’ the segment has to the
rest of the network.
This function is repeated 13 times in the RIC (one for each
port) and is shown on the right side of the Block Diagram,
Figure 5.1
The physical layer interfaces provided depends upon the
port under examination. Port 1 has an AUI compliant interface for use with AUI compatible transceiver boxes and cable. Ports 2 to 13 may be configured for use with one of two
interfaces: twisted pair or an external transceiver. The former utilizes the RIC’s on-chip 10BASE-T transceivers, the
latter allows connection to external transceivers. When using the external transceiver mode the interface is AUI compatible. Although AUI compatible transceivers are supported the interface is not designed for use with an interface
cable, thus the transceivers are necessarily internal to the
repeater equipment.
Inside the port logic there are 3 distinct functions:
1. The port state machine ‘‘PSM’’ is required to perform
2. The port partition logic implements the segment partition-
3. The port status register reflects the current status of the
Shared Functional Blocks:
Repeater Core Logic
The shared functional blocks consist of the Repeater Main
State Machine (MSM) and Timers, a 32 bit Elasticity Buffer,
PLL Decoder, and Receive and Transmit Multiplexors.
These blocks perform the majority of the operations needed
to fulfill the requirements of the IEEE repeater specification.
When a packet is received by a port it is sent via the Receive Multiplexor to the PLL Decoder. Notification of the
.
data and collision repetition as described by the repeater
specification, for example, it determines whether this port
should be receiving from or transmitting to its network
segment.
ing algorithm. This algorithm is defined by the IEEE specification and is used to protect the network from malfunctioning segements.
port. It may be accessed by a system processor to obtain
this status or to perform certain port configuration operations, such as port disable.
data and collision status is sent to the main state machine
via the receive multiplexor and collision activity status signals. This enables the main state machine to determine the
source of the data to be repeated and the type of data to be
transmitted. The transmit data may be either the received
packet’s data field or a preamble/jam pattern consisting of
a 1010 . . . bit pattern.
Associated with the main state machine are a series of timers. These ensure various IEEE specification times (referred
to as the TW1 to TW6 times) are fulfilled.
A repeater unit is required to meet the same signal jitter
performance as any receiving node attached to a network
segment. Consequently, a phase locked loop Manchester
decoder is required so that the packet may be decoded, and
the jitter accumulated over the receiving segment recovered. The decode logic outputs data in NRZ format with an
associated clock and enable. In this form the packet is in a
convenient format for transfer to other devices, such as network controllers and other RICs, via the Inter-RIC bus (described later). The data may then be re-encoded into Manchester data and transmitted.
Reception and transmission via physical layer transceiver
units causes a loss of bits in the preamble field of a data
packet. The repeater specification requires this loss to be
compensated for. To accomplish this an elasticity buffer is
employed to temporarily store bits in the data field of the
packet.
The sequence of operation is as follows:
Soon after the network segment receiving the data packet
has been identified, the RIC begins to transmit the packet
preamble pattern (1010 . . . ) onto the other network segments. While the preamble is being transmitted the Elasticity Buffer monitors the decoded received clock and data signals (this is done via the Inter-RIC bus as described later).
When the start of frame delimiter ‘‘SFD’’ is detected the
received data stream is written into the elasticity buffer. Removal of data from the buffer for retransmission is not allowed until a valid length preamble pattern has been transmitted.
Inter-RIC Bus Interface
Using the RIC in a repeater system allows the design to be
constructed with many more network attachments than can
be supported by a single chip. The split of functions already
described allows data packets and collision status to be
transferred between multiple RICs, and at the same time the
multiple RICs still behave as a single logical repeater. Since
all RICs in a repeater system are identical and capable of
performing any of the repetition operations, the failure of
one RIC will not cause the failure of the entire system. This
is an important issue in large multiport repeaters.
RICs communicate via a specialized interface known as the
Inter-RIC bus. This allows the data packet to be transferred
from the receiving RIC to the other RICs in the system.
These RICs then transmit the data stream to their segments. Just as important as data transfer is the notification
of collisions occurring across the network. The Inter-RIC
bus has a set of status lines capable of conveying collision
information between RICs to ensure their main state machines operate in the appropriate manner.
23
5.0 Functional Description (Continued)
LED Interface and Hub Management Function
Repeater systems usually possess optical displays indicating network activity and the status of specific repeater operations. The RIC’s display update block provides the system
designer with a wide variety of indicators. The display updates are completely autonomous and merely require SSI
logic devices to drive the display devices, usually made up
of light emitting diodes, LEDs. The status display is very
flexible allowing the user to choose those indicators appropriate for the specification of the equipment.
The RIC has been designed with special awareness for system designers implementing large repeaters possessing
hub management capabilities. Hub management uses the
unique position of repeaters in a network to gather statistics
about the network segments they are attached to. The RIC
provides hub management statistical data in 3 steps. Important events are gathered by the management block from
logic blocks throughout the chip. These events may then be
stored in on-chip latches or counted in on-chip counters according to user supplied latching and counting masks.
The fundamental task of a hub management system implementation is to associate the current packet and any management status information with the network segment, i.e.,
repeater port where the packet was received. The ideal system would place this combined data packet and status field
in system memory for examination by hub management
software. The ultimate function of the RIC’s hub management support logic is to provide this function.
To accomplish this the RIC utilizes a dedicated hub management interface. This is similar to the Inter-RIC bus since
it allows the data packet to be recovered from the receiving
RIC. Unlike the Inter-RIC bus the intended recipient is not
another RIC but National Semiconductor’s DP83932
TM
‘‘SONIC
allows a management status field to be appended at the
end of the data packet. This can be done without affecting
the operation of the repeater system.
Processor Interface
The RIC’s processor interface allows connection to a system processor. Data transfer occurs via an octal bi-directional data bus. The RIC has a number of on-chip registers
indicating the status of the hub management functions, chip
configuration and port status. These may be accessed by
providing the chosen address at the Register Address
(RA4–RA0) input pins.
Display update cycles and processor accesses occur utilizing the same data bus. An on-chip arbiter in the processor/
display block schedules and controls the accesses and ensures the correct information is written into the display latches. During the display update cycles the RIC behaves as a
master of its data bus. This is the default state of the data
bus. Consequently, a TRI-STATE buffer must be placed between the RIC and the system processor’s data bus. This
’’ Network controller. The use of a dedicated bus
ensures bus contention is avoided during simultaneous display update cycles and processor accesses of other devices on the system bus. When the processor accesses a RIC
register, the RIC enables the data buffer and selects the
operation, either input or output, of the data pins.
5.2 DESCRIPTION OF REPEATER OPERATIONS
In order to implement a multi-chip repeater system which
behaves as though it were a single logical repeater, special
consideration must be paid to the data path used in packet
repetition. For example, where in the path are specific operations such as Manchester decoding and elasticity buffering
performed. Also the system’s state machines which utilize
available network activity signals, must be able to accommodate the various packet repetition and collision scenarios
detailed in the repeater specification.
The RIC contains two types of inter-acting state machines.
These are:
1. Port State Machines (PSMs). Every network attachment
has its own PSM.
2. Main State Machine (MSM). This state machine controls
the shared functional blocks as shown in the block diagram
Figure 5.1.
Repeater Port and Main State Machines
These two state machines are described in the following
sections. Reference is made to expressions used in the
IEEE Repeater specification. For the precise definition of
these terms please refer to the specification. To avoid confusion with the RIC’s implementation, where references are
made to repeater states or terms as described in the IEEE
specification, these items are written in
state diagram is shown in
diagram is shown in
FIGURE 5.2. Inter-RIC Bus State Diagram
Figure 5-3
Figure 5-2
.
italics.
, the Inter-RIC bus state
The IEEE
TL/F/11096– 7
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