NSC DP83849CVS, DP83849C Datasheet

August 2006

DP83849C PHYTER® DUAL Commercial Temperature

Dual Port 10/100 Mb/s Ethernet Physical Layer Transceiver

DP83849C PHYTER® DUAL Commercial Temperature Dual Port 10/100 Mb/s Ethernet Physical Layer Transceiver

General Description

The number of applications requiring Ethernet Connectivity continues to expand. Along with this increased market demand is a change in application requirements. Where single channel Ethernet used to be sufficient, many applications such as wireless remote base stations and industrial networking now require DUAL Port functionality for redundancy or system management.

The DP83849C is a highly reliable, feature rich device perfectly suited for commercial or industrial applications enabling Ethernet on the factory floor. The DP83849C features two fu lly i ndepen dent 1 0/100 p orts for multi-port applications.

The DP83849C provides optimum flexibility in MPU selection by supporting both MII and RMII interfaces. In additio n this device includes a powerful new diagnostics tool to ensure initial network operation and maintenance. In addition to the TDR scheme, commonly used for detecting faults during installation, NATIONAL’s innovative cable diagnostics provides for real time continuous monitoring of the link quality. This allows the system designer to implement a fault prediction mechanism to detect and warn of changing or deteriorating link conditions.

With the DP83849C, National Semiconductor continues to build on its Ethernet expertise and leadership position by providing a powerful combination of features and flexibili ty, easing Ethernet implementation for the system designer.

Features

• Low-power 3.3V, 0.18µm CMOS technology

• Low power consumption <600mW Typical

• 3.3V MAC Interface

• Auto-MDIX for 10/100 Mb/s

• Energy Detection Mode

• Dynamic Integrity Utility

• Dynamic Link Quality Monitoring

• TDR based Cable Diagnostic and Cable Length Detection

• Optimized Latency for Real Time Ethernet Operation

• Reference Clock out

• RMII Rev. 1.2 Interface (configurable)

• SNI Interface (configurable)

• MII Serial Management Interface (MDC and MDIO)

• IEEE 802.3u MII

• IEEE 802.3u Auto-Negotiation and Parallel Detection

• IEEE 802.3u ENDEC, 10BASE-T transceivers and filters

• IEEE 802.3u PCS, 100BASE-TX transceivers and filters

• Integrated ANSI X3.263 compliant TP-PMD physical sub-layer

with adaptive equalization and Baseline Wander compensation

• Programmable LED support for Link, 10 /100 Mb/s Mode, Activ-

ity, Duplex and Collision Detect

• Single register access for complete PHY status

• 10/100 Mb/s packet BIST (Built in Self Test)

• 80-pin TQFP package (12mm x 12mm)

Applications

• Medical Instrumentation

• Factory Automation

• Motor & Motion Control

• Wireless Remote Base Station

• General Embedded Applications

System Diagram

Port B

DP83849C

Port A

Status

LEDs

Magnetics

MPU/CPU

MII/RMII/SNI

MAC

MII/RMII/SNI

MAC

25 MHz Clock

Source

Typical Application

PHYTER is a registered trademark of National Semiconductor Corporation

10BASE-T

RJ-45

100BASE-TX

10BASE-T

RJ-45

100BASE-TX

DP83849C

LED

DRIVERS

PORT A

MII/RMII/SNI

10/100 PHY CORE

PORT A

MII MANAGEMENT

INTERFACE

MDC

MANAGEMENT

INTERFACE

MDIO

PORT B

MII/RMII/SNI

RXTXTX RX

10/100 PHY CORE

PORT B

LED

DRIVERS

LEDS

TPTD± TPRD±

Figure 1. DP83849C Functional Block Diagram

LEDS

TPRD±TPTD±

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Table of Contents

1.0 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.1 Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

1.2 MAC Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

1.3 Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

1.4 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

1.5 Reset and Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

1.6 Strap Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

1.7 10 Mb/s and 100 Mb/s PMD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

1.8 Special Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

1.9 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

1.10 Package Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

2.0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.1 Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

2.1.1 Auto-Negotiation Pin Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.1.2 Auto-Negotiation Register Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.1.3 Auto-Negotiation Parallel Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.1.4 Auto-Negotiation Restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.1.5 Enabling Auto-Negotiation via Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.1.6 Auto-Negotiation Complete Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.2 Auto-MDIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

2.3 PHY Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

2.3.1 MII Isolate Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.4 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

2.4.1 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.4.2 LED Direct Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.5 Half Duplex vs. Full Duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

2.6 Internal Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

2.7 BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

3.0 MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.1 MII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

3.1.1 Nibble-wide MII Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.1.2 Collision Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.1.3 Carrier Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.2 Reduced MII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

3.3 10 Mb Serial Network Interface (SNI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

3.4 802.3u MII Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

3.4.1 Serial Management Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.4.2 Serial Management Access Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.4.3 Serial Management Preamble Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.4.4 Simultaneous Register Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.0 Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.1 100BASE-TX TRANSMITTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

4.1.1 Code-group Encoding and Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.1.2 Scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.1.3 NRZ to NRZI Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.1.4 Binary to MLT-3 Convertor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.2 100BASE-TX RECEIVER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

4.2.1 Analog Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.2.2 Digital Signal Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.2.2.1 Digital Adaptive Equalization and Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.2.2.2 Base Line Wander Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.2.3 Signal Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.2.4 MLT-3 to NRZI Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.2.5 NRZI to NRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.2.6 Serial to Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.2.7 Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.2.8 Code-group Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

DP83849C

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4.2.9 4B/5B Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.2.10 100BASE-TX Link Integrity Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.2.11 Bad SSD Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.3 10BASE-T TRANSCEIVER MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

4.3.1 Operational Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.3.2 Smart Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.3.3 Collision Detection and SQE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.3.4 Carrier Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.3.5 Normal Link Pulse Detection/Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.3.6 Jabber Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.3.7 Automatic Link Polarity Detection and Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.3.8 Transmit and Receive Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.3.9 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.3.10 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

5.0 Design Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.1 TPI Network Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

5.2 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

5.3 Clock In (X1) Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

5.4 Power Feedback Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

5.5 Power Down/Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

5.5.1 Power Down Control Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

5.5.2 Interrupt Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.6 Energy Detect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

5.7 Link Diagnostic Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

5.7.1 Linked Cable Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.7.1.1 Polarity Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.7.1.2 Cable Swap Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.7.1.3 100MB Cable Length Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.7.1.4 Frequency Offset Relative to Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5.7.1.5 Cable Signal Quality Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.7.2 Link Quality Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.7.2.1 Link Quality Monitor Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.7.2.2 Checking Current Parameter Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.7.2.3 Threshold Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.7.3 TDR Cable Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.7.3.1 TDR Pulse Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.7.3.2 TDR Pulse Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.7.3.3 TDR Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.7.3.4 TDR Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.0 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

6.1 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

6.2 Full Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

6.3 Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

7.0 Register Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7.1 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

7.1.1 Basic Mode Control Register (BMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

7.1.2 Basic Mode Status Register (BMSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7.1.3 PHY Identifier Register #1 (PHYIDR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.1.4 PHY Identifier Register #2 (PHYIDR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.1.5 Auto-Negotiation Advertisement Register (ANAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

7.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page) . . . . . . . . . . . . . . . . 53

7.1.7 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page) . . . . . . . . . . . . . . . . . 54

7.1.8 Auto-Negotiate Expansion Register (ANER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

7.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR) . . . . . . . . . . . . . . . . . . . . . . . . . . 56

7.1.10 PHY Status Register (PHYSTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

7.1.11 MII Interrupt Control Register (MICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

7.1.12 MII Interrupt Status and Misc. Control Register (MISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

7.1.13 Page Select Register (PAGESEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

7.2 Extended Registers - Page 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

7.2.1 False Carrier Sense Counter Register (FCSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

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7.2.2 Receiver Error Counter Register (RECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

7.2.3 100 Mb/s PCS Configuration and Status Register (PCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 61

7.2.4 RMII and Bypass Register (RBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

7.2.5 LED Direct Control Register (LEDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

7.2.6 PHY Control Register (PHYCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

7.2.7 10 Base-T Status/Control Register (10BTSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

7.2.8 CD Test and BIST Extensions Register (CDCTRL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

7.2.9 Phy Control Register 2 (PHYCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

7.2.10 Energy Detect Control (EDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

7.3 Link Diagnostics Registers - Page 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

7.3.1 100Mb Length Detect Register (LEN100_DET), Page 2, address 14h . . . . . . . . . . . . . . . . . 70

7.3.2 100Mb Frequency Offset Indication Register (FREQ100), Page 2, address 15h . . . . . . . . . 70

7.3.3 TDR Control Register (TDR_CTRL), Page 2, address 16h . . . . . . . . . . . . . . . . . . . . . . . . . . 71

7.3.4 TDR Window Register (TDR_WIN), Page 2, address 17h . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

7.3.5 TDR Peak Register (TDR_PEAK), Page 2, address 18h . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

7.3.6 TDR Threshold Register (TDR_THR), Page 2, address 19h . . . . . . . . . . . . . . . . . . . . . . . . . 72

7.3.7 Variance Control Register (VAR_CTRL), Page 2, address 1Ah . . . . . . . . . . . . . . . . . . . . . . 73

7.3.8 Variance Data Register (VAR_DATA), Page 2, address 1Bh . . . . . . . . . . . . . . . . . . . . . . . . 73

7.3.9 Link Quality Monitor Register (LQMR), Page 2, address 1Dh . . . . . . . . . . . . . . . . . . . . . . . . 74

7.3.10 Link Quality Data Register (LQDR), Page 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

8.0 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

8.1 DC Specs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

8.2 AC Specs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

8.2.1 Power Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

8.2.2 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

8.2.3 MII Serial Management Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

8.2.4 100 Mb/s MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

8.2.5 100 Mb/s MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

8.2.6 100BASE-TX MII Transmit Packet Latency Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

8.2.7 100BASE-TX MII Transmit Packet Deassertion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

8.2.8 100BASE-TX Transmit Timing (tR/F & Jitter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

8.2.9 100BASE-TX MII Receive Packet Latency Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

8.2.10 100BASE-TX MII Receive Packet Deassertion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

8.2.11 10 Mb/s MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

8.2.12 10 Mb/s MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

8.2.13 10 Mb/s Serial Mode Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

8.2.14 10 Mb/s Serial Mode Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

8.2.15 10BASE-T Transmit Timing (Start of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

8.2.16 10BASE-T Transmit Timing (End of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

8.2.17 10BASE-T Receive Timing (Start of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

8.2.18 10BASE-T Receive Timing (End of Packet) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

8.2.19 10 Mb/s Heartbeat Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

8.2.20 10 Mb/s Jabber Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

8.2.21 10BASE-T Normal Link Pulse Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

8.2.22 Auto-Negotiation Fast Link Pulse (FLP) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

8.2.23 100BASE-TX Signal Detect Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

8.2.24 100 Mb/s Internal Loopback Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

8.2.25 10 Mb/s Internal Loopback Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

8.2.26 RMII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

8.2.27 RMII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

8.2.28 Isolation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

8.2.29 CLK2MAC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

9.0 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

DP83849C

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List of Figures

Figure 1. DP83849C Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Figure 2. PHYAD Strapping Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 3. AN Strapping and LED Loading Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 4. Typical MDC/MDIO Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 5. Typical MDC/MDIO Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 6. 100BASE-TX Transmit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 7. 100BASE-TX Receive Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 9. EIA/TIA Attenuation vs. Frequency for 0, 50, 100, 130 & 150 meters of CAT 5 cable . . . . . . . . . . . 30

Figure 10. 100BASE-TX BLW Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 11. 10BASE-T Twisted Pair Smart Squelch Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 12. 10/100 Mb/s Twisted Pair Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 13. Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 14. Power Feeback Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

DP83849C

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List of Tables

Table 1. Auto-Negotiation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Table 2. PHY Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 3. LED Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Table 4. Supported packet sizes at +/-50ppm frequency accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Table 5. Typical MDIO Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 13. 4B5B Code-Group Encoding/Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 14. 25 MHz Oscillator Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 15. 50 MHz Oscillator Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 16. 25 MHz Crystal Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Table 17. Link Quality Monitor Parameter Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Table 18. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Table 19. Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 20. Basic Mode Control Register (BMCR), address 00h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Table 21. Basic Mode Status Register (BMSR), address 01h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Table 22. PHY Identifier Register #1 (PHYIDR1), address 02h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Table 23. PHY Identifier Register #2 (PHYIDR2), address 03h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Table 24. Negotiation Advertisement Register (ANAR), address 04h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Table 25. Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page), address 05h . . . . . . . . .53

Table 26. Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page), address 05h . . . . . . . . . .54

Table 27. Auto-Negotiate Expansion Register (ANER), address 06h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Table 28. Auto-Negotiation Next Page Transmit Register (ANNPTR), address 07h . . . . . . . . . . . . . . . . . . . .56

Table 29. PHY Status Register (PHYSTS), address 10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Table 30. MII Interrupt Control Register (MICR), address 11h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Table 31. MII Interrupt Status and Misc. Control Register (MISR), address 12h . . . . . . . . . . . . . . . . . . . . . . .59

Table 32. Page Select Register (PAGESEL), address 13h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Table 33. False Carrier Sense Counter Register (FCSCR), address 14h . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Table 34. Receiver Error Counter Register (RECR), address 15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Table 35. 100 Mb/s PCS Configuration and Status Register (PCSR), address 16h . . . . . . . . . . . . . . . . . . . . .61

Table 36. RMII and Bypass Register (RBR), addresses 17h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Table 37. LED Direct Control Register (LEDCR), address 18h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Table 38. PHY Control Register (PHYCR), address 19h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Table 39. 10Base-T Status/Control Register (10BTSCR), address 1Ah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Table 40. CD Test and BIST Extensions Register (CDCTRL1), address 1Bh . . . . . . . . . . . . . . . . . . . . . . . . . .68

Table 41. Phy Control Register 2 (PHYCR2), address 1Ch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Table 42. Energy Detect Control (EDCR), address 1Dh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Table 43. 100Mb Length Detect Register (LEN100_DET), address 14h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Table 44. 100Mb Frequency Offset Indication Register (FREQ100), address 15h . . . . . . . . . . . . . . . . . . . . . .70

Table 45. TDR Control Register (TDR_CTRL), address 16h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Table 46. TDR Window Register (TDR_WIN), address 17h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Table 47. TDR Peak Register (TDR_PEAK), address 18h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Table 48. TDR Threshold Register (TDR_THR), address 19h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Table 49. Variance Control Register (VAR_CTRL), address 1Ah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Table 50. Variance Data Register (VAR_DATA), address 1Bh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Table 51. Link Quality Monitor Register (LQMR), address 1Dh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Table 52. Link Quality Data Register (LQDR), address 1Eh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

DP83849C

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Pin Layout

DP83849C

RX_ER_B/MDIX_EN_B

COL_B

RXD0_B/PHYAD3

RXD1_B/PHYAD4

RXD2_B

COREGND2

PFBIN4

RXD3_B/ED_EN_B

IOGND2

IOVDD2

TX_CLK_B

TX_EN_B

TXD0_B

TXD1_B

TXD2_B

TXD3_B/SNI_MODE_B

PWRDOWN_INT_B

LED_LINK_B/AN0_B

LED_SPEED_B/AN1_B

LED_ACT/LED_COL/AN_EN_B

60595857565554535251504948474645444342

RS_B/CRS_DV_B/LED_CFG_B

RX_DV_B/MII_MODE_B

RX_CLK_B

IOGND3

IOVDD3

MDIO

MDC

CLK2MAC

RESET_N RESERVED RESERVED RESERVED RESERVED RESERVED

IOGND4

IOVDD4

RX_CLK_A

RX_DV_A/MII_MODE_A

61 62 63 64 65 66 67 68 69

71 72 73 74 75 76 77 78 79 80

DP83849CVS

1011121314151617181920

ANAGND4

TPRDM_B

TPRDP_B

CDGND2

TPTDM_B

TPTDP_B

PFBIN3

ANAGND3

RBIAS

PFBOUT

ANA33VDD

ANAGND2

PFBIN2

TPTDP_A

TPTDM_A

CDGND1

TPRDP_A

TPRDM_A

ANAGND1 LED_ACT/LED_COL/AN_EN_A

COL_A

RXD0_A/PHYAD1

RX_ER_A/MDIX_EN_A

CRS_A/CRS_DV_A/LED_CFG_A

COREGND1

RXD1_A/PHYAD2

PFBIN1

IOVDD1

IOGND1

RXD3_A/ED_EN_A

RXD2_A/CLK2MAC_DIS

TXD0_A

TXD1_A

TX_EN_A

TX_CLK_A

TXD2_A

PWRDOWN_INT_A

LED_LINK_A/AN0_A

TXD3_A/SNI_MODE_A

LED_SPEED_A/AN1_A

Top View

NS Package Number VHB80A

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1.0 Pin Descriptions

The DP83849C pins are classified into the following interface categories (each interface is described in the sections that follow):

— Serial Management Interface — MAC Data Interface — Clock Interface — LED Interface — Reset and Power Down — Strap Options — 10/100 Mb/s PMD Interface — Special Connect Pins — Power and Ground pins Note: Strapping pin opti on. Please s ee Section 1.6 for strap

definitions.

1.1 Serial Management Interface

Signal Name Type Pin # Description

MDC I 67 MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO

management data input/output serial interface which may be asyn chronous to transmit and receive clocks. The maximum clock rate is 25 MHz with no minimum clock rate.

MDIO I/O 66 MANAGEMENT DATA I/O: Bi-directional management instruc-

tion/data signal that may be sou rced by the stati on management en tity or the PHY . This pin requires a 1.5 kΩ pullup resistor.

All DP83849C signal pins are I/O cells regardless of the particular use. The defi nition s below define the functiona lit y of the I/O cells for each pin.

Type: I Input Type: O Output Type: I/O Input/Output Type OD Open Drain Type: PD,PU Internal Pulldown/Pullup Type: S Strapping Pin (All strap pins have weak in-

ternal pu ll-ups or pull- downs. If the default strap value is to be changed then an exter nal 2.2 kΩ resistor should be used. Please see Section 1.6 for details.)

DP83849C

1.2 MAC Data Interface

Signal Name Type Pin # Description

TX_CLK_A TX_CLK_B

TX_EN_A TX_EN_B

TXD[3:0]_A TXD[3:0]_B

O 12

I 13

I 17,16,15,14

45,46,47,48

MII TRANSMIT CLOCK: 25 MHz Transmit clock output in 100 Mb/s mode or 2.5 MH z in 10 Mb/s m ode derived f rom the 25 MHz reference clock.

Unused in RMII mo de. T he d evi ce uses the X1 reference clock input as the 50 MHz reference for both transmit and receive.

SNI TRANSMIT CLOCK: 10 MHz Transmit cloc k output in 10 Mb SNI mode. The MAC should source TX_EN and TXD_0 using this clock.

MII TRANSMIT ENABLE: Active high input indic ates th e prese nce of valid data inputs on TXD[3:0].

RMII TRANSMIT ENABLE: Active high input indicates the presence of valid data on TXD[1:0].

SNI TRANSMIT ENABLE: Active high input indic ates the presence of valid data on TXD_0.

MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0], that accept data synchronous to the TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in 100 Mb/s mode).

RMII TRANSMIT DATA: Transmit data RMII input pins, TXD[1:0], that accept data synchronous to the 50 MHz reference clock.

SNI TRANSMIT DATA: Transmit data SNI input p in, T XD _0, that accept data synch ronous to the TX_CL K (10 MHz in 10 Mb/s SNI mode).

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1.2 MAC Data Interface (Continued)

Signal Name Type Pin # Description

RX_CLK_A RX_CLK_B

RX_DV_A RX_DV_B

RX_ER_A RX_ER_B

RXD[3:0]_A RXD[3:0]_B

CRS_A/CRS_DV_A CRS_B/CRS_DV_B

COL_A COL_B

O 79

O 80

O 2

O 9,8,5,4

53,56,57,58

O 1

O 3

MII RECEIVE CLOCK: Provides the 25 MHz recovered receive clocks for 100 Mb/s mode and 2.5 MHz for 10 Mb/s mode.

Unused in RMII mo de. T he d evi ce uses the X1 reference clock input as the 50 MHz reference for both transmit and receive.

SNI RECEIVE CLOCK: Provides the 10 MHz recovered receive clocks for 10 Mb/s SNI mode.

MII RECEIVE DATA VALID: Asserted high to i ndi ca te th at v al id d ata is present on the corresponding RXD[3:0].

RMII RECEIVE DATA VALID: Asserted high to indicate that valid data is present on the corresponding RXD[1:0]. This signal is not re quired in RMII mode, since CRS_DV includes the RX_DV signal, but is provided to allow simpler recovery of the Receive data.

This pin is not used in SNI mode. MII RECEIVE ERROR: Asserted high synchronously to RX_CLK to

indicate that an invalid symbol has been detected within a received packet in 100 Mb/s mode.

RMII RECEIVE ERROR: Asserted high synchronou sly to X1 when ever an invalid symbo l is detected, and CRS _DV is asserted in 100 Mb/s mode. This pin is als o ass ert ed on d ete cti on of a Fa ls e C arr ier eve nt. This pin is not required to be used by a MAC in RMII mode, s in ce the Phy is required to corrupt data on a receive error.

This pin is not used in SNI mode. MII RECEIVE DATA: Nibble wide receive data signals driven syn-

chronously to the RX_CLK, 25 MHz for 100 Mb/s mode, 2.5 MHz for 10 Mb/s mode). RXD[3:0] signals contain valid data when RX_DV is asserted.

RMII RECEIVE DATA: 2-bits receive data signals, RXD[1:0], driven synchronousl y to the X1 clock, 50 MHz.

SNI RECEIVE DATA: Receive data signal, RXD_0, driven synchronously to the RX_CLK. RXD_0 contains valid data when CRS is asserted. RXD[3:1] are not used in this mode.

MII CARRIER SENSE: Asserted high to indicate th e receive me dium is non-idle.

RMII CARRIER SENSE/RECEIVE DATA VALID: This signal combines the RMII Carrier and Receive Data Valid indications. For a detailed description of this signal, see the RMII Specification.

SNI CARRIER SENSE: Asserted high to in dicate the receive medium is non-idle. It is used to fra me valid receive data on the RXD _0 sign al.

MII COLLISION DETECT: Asserted high to indicate detection of a collision condition (simultaneous transmit and receive activity) in 10 Mb/s and 100 Mb/s Half Duplex Modes.

While in 10BASE-T Half Duplex mode with heartbeat enabled this pin is also asserted for a duration of approximately 1µs at the end of transmission to indicate heartbeat (SQE test).

In Full Duplex M ode, fo r 10 M b/s or 100 Mb /s op eration , this signa l is always logic 0. There is no heartbeat function during 10 Mb/s full du plex operation.

RMII COLLISION DETECT: Per the RMII Specification, no COL signal is required. The MAC will recover CRS from the CRS_DV signal and use that along with its TX_EN signal to determine collision.

SNI COLLISION DETECT: Asserted high to indicate detection of a collision condition (simultaneous transmit and receive activity) in 10 Mb/s SNI mode.

DP83849C

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1.3 Clock Interface

Signal Name Type Pin # Description

X1 I 70 CRYSTAL/OSCILLATOR INPUT: This pin i s the primary clock

X2 O 69 CRYSTAL OUTPUT: This pin is the primary clock reference out-

CLK2MAC O 68 CLOCK TO MAC:

reference input fo r the DP83849C and must be co nnected to a 25 MHz 0.005% ( either an external crys tal resonator connecte d across pins X1 and X2, or an external CMO S-level oscil lator sourc e connec ted to pin X1 only.

RMII REFERENCE CLOCK: This pin is the primary clock reference input for the RMII mode and mu st be connected to a 50 MHz

0.005% (

put to connect to an external 25 MHz crystal resonator device. This pin must be left unconnected if an external C MOS osc ill ator clock source is used.

In MII mode, this pin provides a 25 MHz clock output to the system.

In RMII mode, this pin prov ides a 50 MHz cloc k outpu t to the sys tem.

This allows other devices to use the reference clock from the DP83849C without requiring additional clock sources.

If the system does not require the CLK2MAC signal, the CLK2MAC output should be disabled via the CLK2MAC disable strap.

+50 ppm) clock source. The DP83849C supports

+50 ppm) CMOS-level oscillator source.

DP83849C

1.4 LED Interface

The DP83849C supports three configurable LED pins. The LEDs support two operational modes which are selected by the LED mode s trap an d a thi rd ope rationa l mod e whic h

Signal Name Type Pin # Description

LED_LINK_A LED_LINK_B

LED_SPEED_A LED_SPEED_B

LED_ACT/LED_COL_A LED_ACT/LED_COL_B

I/O 19

I/O 20

I/O 21

LINK LED: In Mode 1, this pin indicates the status of the LINK. The LED will be ON when Link is good.

LINK/ACT LED: In Mode 2 and Mode 3, this pi n indicates tra nsmit and receive activity in addition to the status of the Link. The LED will be ON when Link is good. It will blink when the transmitter or receiver is active.

SPEED LED: The LED is ON when device is i n 100 Mb/s and OFF when in 10 Mb/s. Functionality of this LED is independ ent of mode selected.

ACTIVITY LED: In Mode 1, this pin is the A ctivity L ED which i s ON when activity is present on either Transmit o r Receive.

COLLISION/DUPLEX LED: In Mode 2, this pin by default indicates Collision detection. For Mode 3, this LED output may be programmed to indicate Full-duplex status instead of Collision.

is register configurable. The definitions for the LEDs for each mode are detailed below. Since the LEDs are also used as strap options, the polarity of the LED output is dependent on whether the pin is pulled up or down.

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1.5 Reset and Power Down

Signal Name Type Pin # Description

RESET_N I, PU 71 RESET: Active Low input that initializes or re-initializes the

PWRDOWN_INT_A PWRDOWN_INT_B

I, PU 18

DP83849C. Asserting this pin low for at leas t 1 µs will force a reset process to occur. All internal registers will re-initialize to their de fault states as spe ci fie d for each bit in the Regi st er Bl oc k section. All strap options are re-initialized as well.

The default function of this pin is POWER DOWN. POWER DOWN: The pin is an active low input in this mode and

should be asserted low to put the device in a Power Down mode. INTERRUPT: The pin is an open drain outpu t in this mo de and will

be asserted low when a n in terru pt co nd itio n oc c urs . Alth oug h the pin has a weak internal pull-up, some applications may require an external pull-up resi ster. R egister a ccess i s requi red for th e pin to be used as an in terrupt me chanism. Se e Mechanism for more details on the interrupt mechanisms.

Section 5.5.2 Interrupt

1.6 Strap Options

The DP83849C uses many of the functional pins as strap options. The values of these pins are sampled during reset and used to strap the device into specific modes of opera tion. The strap option pin assignments are defined below. The functional pin name is indicated in parentheses.

A 2.2 kΩ resistor should be used for pull-down or pull-up to change the default strap option. If the default option is required, then there is no need for external pull-up or pull

down resistors. Since these pins may have alternate func

tions after reset is deasserted, they should not be connected directly to VCC or GND.

DP83849C

Signal Name Type Pin # Description

PHYAD1 (RXD0_A) PHYAD2 (RXD1_A) PHYAD3 (RXD0_B) PHYAD4 (RXD1_B)

S, O, PD S, O, PD S, O, PD S, O, PD

58 57

4 5

PHY ADDRESS [4:1]: The DP83849C provides four PHY address pins, the state of w hi ch are la tch ed in to th e PH YCTR L reg ister at system Hardware- Reset. Phy Address[0] se lects between ports A and B.

The DP83849C supports PHY Addr ess strapping for Port A even values 0 (<0000_0>) through 30 (<1111_0>). Port B will be strapped to odd values 1 (<0000_1>) through 31 (<1111_1>).

PHYAD[4:1] pins have weak internal pull-down resistors.

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1.6 Strap Options (Continued)

lex

Signal Name Type Pin # Description

AN_EN (LED_ACT/LED_COL_A)

AN1_A (LED_SPEED_A) AN0_A (LED_LINK_A)

AN_EN (LED_ACT/LED_COL_B)

AN1_B (LED_SPEED_B) AN0_B (LED_LINK_B)

S, O, PU 21

20 19

41 42 43

Auto-Negotiation Enable: When high, this enables Auto-Negoti ation with the cap ability set by AN 0 and AN1 p ins. When low, th is puts the part i nto Force d Mode with the capabili ty set by AN0 an d AN1 pins.

AN0 / AN1: These input pins control the forced or advertised operating mode of the DP83849C according to the following table. The value on these pins is set by connecting the input pins to GND (0) or V

NEVER be connected directly to GND or VCC.

The value set at this input is latched into the DP83849C at Hardware-Reset.

The float/pull-down sta tus of these pin s ar e latch ed into the Bas ic Mode Control Register and the Auto_Negotiation Advertisement Register during Hardware-Reset.

The default is 111 since these pins have internal pull-ups.

(1) through 2.2 kΩ resistors. These pins should

AN_EN AN1 AN0 Forced Mode

0 0 0 10BASE-T, Half-Duplex 0 0 1 10BASE-T, Full-Duplex 0 1 0 100BASE-TX, Half-Duplex 0 1 1 100BASE-TX, Full-Duplex

AN_EN AN1 AN0 Advertised Mode

1 0 0 10BASE-T, Half/Full-Duplex 1 0 1 100BASE-TX, Half/Full-Dup 1 1 0 10BASE-T Half-Duplex

100BASE-TX, Half-Duplex

1 1 1 10BASE-T, Half/Full-Duplex

100BASE-TX, Half/Full-Dup

DP83849C

MII_MODE_A (RX_DV_A) SNI_MODE_A (TXD3_A) MII_MODE_B (RX_DV_B) SNI_MODE_B (TXD3_B)

S, O, PD 80

17 62 45

MII MODE SELECT: This strapping option pair determines the operating mode of the MAC Data Interface. Default operation (No pull-ups) will e nable norma l MII Mod e of op eratio n. Strapp ing MII_MODE high w ill ca use th e devi ce to b e in RMI I or SNI modes of operation, determined by the status of the SNI_MODE strap. Since the pins include internal pull-downs, the default values are

0. Both MAC Data Int erfaces m ust ha ve their RMII Mode settings the same, i.e. both in RMII mode or both not in RMII mode.

The following table details the configurations:

MII_MODE SNI_MODE MAC Interface

Mode

0 X MII Mode 1 0 RMII Mode 1 1 10 Mb SNI Mode

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1.7 10 Mb/s and 100 Mb/s PMD Interface (Continued)

Signal Name Type Pin # Description

LED_CFG_A (CRS_A/CRS_DV_A)

LED_CFG_B (CRS_B/CRS_DV_B)

MDIX_EN_A (RX_ER_A) MDIX_EN_B (RX_ER_B)

ED_EN_A (RXD3_A) ED_EN_B (RXD3_B)

CLK2MAC_DIS (RXD2_A) S, O, PD 8 Clock to MAC Disable: This strapping o ption disables (flo ats) the

S, O, PU 1

S, O, PU 2

S, O, PD 9

LED CONFIGURATION: This strapping option determines the mode of operation of the LED pins . Default is Mode 1. Mode 1 and Mode 2 can be controlled via the s trap opti on. All m odes are con figurable via register access.

See Table 3 on page 20 for LED Mode Selection. MDIX ENABLE: Default is to enable MD I X. This strapping option

disables Auto-MDIX. An external pull-down will disable AutoMDIX mode.

Energy Detect ENABLE: Default is to disable Energy Detect mode. This strapping option enables Energy Detect mode for the port. In Energy Detect mode, the device will initially be in a lowpower state until detec ting activity on the wire. An external pull-up will enable Energy Detect mode.

CLK2MAC pin. Def ault is to en able CLK2MA C output. An external pullup will disable (float) the CLK2MAC pin. If the system doe s not require the CLK2MA C signal, the CLK2MAC output should be d is abled via this strap option.

1.7 10 Mb/s and 100 Mb/s PMD Interface

DP83849C

Signal Name Type Pin # Description

TPTDM_A TPTDP_A TPTDM_B TPTDP_B

TPRDM_A TPRDP_A TPRDM_B TPRDP_B

I/O 26

27 36 35

I/O 23

24 39 38

10BASE-T or 100BASE-TX Transmit Data

In 10BASE-T or 100BASE-TX: Differential common driver transmit output (PMD Ou tput Pair). Th ese different ial ou tputs are a utomatically configured to either 10BASE-T or 100BASE-TX signaling.

In Auto-MDIX mode of opera tion, this pa ir can be used as the Receive Input pair.

These pins require 3.3V bias for operation.

10BASE-T or 100BASE-TX Receive Data

In 10BASE-T or 100BASE-TX: Differenti al receiv e input (PMD In put Pair). These differential in puts are autom atically configured to accept either 100BASE-TX or 10BASE-T signaling.

In Auto-MDIX mode of operation, this pair can be used as the Transmit Output pair.

These pins require 3.3V bias for operation.

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1.8 Special Connections

Signal Name Type Pin # Description

RBIAS I 32 Bias Resistor Connection: A 4.87 kΩ 1% resistor should be con -

nected from RBIAS to GND.

PFBOUT O 31 Power Feedback Output: Parallel caps, 10µ F and 0.1µF, should

PFBIN1 PFBIN2 PFBIN3 PFBIN4

RESERVED I/O 72, 73, 74,

I 7

28 34 54

75, 76

be placed close to the PFBOUT. Connect this pin to PFBIN1 (pin

13), PFBIN2 (pin 27), PFBIN3 (pin35), PFBIN4 (pin 49). See Section 5.4 for proper placement pin.

Power Feedback Input: These pins are fed with power from PFBOUT pin. A small capacitor of 0.1 close to each pin.

Note: Do not supply power to these pins other than from PFBOUT.

RESERVED: These pins must be left unconnected.

µF should be connected

1.9 Power Supply Pins

Signal Name Pin # Description

IOVDD1, IOVDD2, IOVDD3, IOVDD4

IOGND1, IOGND2, IOGND3, IOGND4

COREGND1, COREGND2 6,55 Core Ground CDGND1, CDGND2 25,37 CD Ground ANA33VDD 30 Anal og 3.3V Supply ANAGND1, ANAGND2,

ANAGND3, ANAGND4

11,51,65,78 I/O 3.3V Supply

10,52,64,77 I/O Ground

22,29,33,40 Analog Ground

DP83849C

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1.10 Package Pin Assignments

DP83849C

VHB80A Pin #Pin Name

1 CRS_A/CRS_DV_A/LED_CFG_A 2 RX_ER_A/MDIX_EN_A 3 COL_A 4 RXD0_A/PHYAD1 5 RXD1_A/PHYAD2 6 COREGND1 7 PFBIN1 8 RXD2_A/CLK2MAC_DIS

9 RXD3_A/ED_EN_A 10 IOGND1 11 IOVDD1 12 TX_CLK_A 13 TX_EN_A 14 TXD0_A 15 TXD1_A 16 TXD2_A 17 TXD3_A/SNI_MODE_A 18 PWRDOWN_INT_A 19 LED_LINK_A/AN0_A 20 LED_SPEED_A/AN1_A 21 LED_ACT/LED_COL/AN_EN_A 22 ANAGND1 23 TPRDM_A 24 TPRDP_A 25 CDGND1 26 TPTDM_A 27 TPTDP_A 28 PFBIN2 29 ANAGND2 30 ANA33VDD 31 PFBOUT 32 RBIAS 33 ANAGND3 34 PFBIN3 35 TPTDP_B 36 TPTDM_B 37 CDGND2 38 TPRDP_B 39 TPRDM_B 40 ANAGND4 41 LED_ACT/LED_COL/AN_EN_B 42 LED_SPEED_B/AN1_B

43 LED_LINK_B/AN0_B 44 PWRDOWN_INT_B 45 TXD3_B/SNI_MODE_B 46 TXD2_B 47 TXD1_B 48 TXD0_B 49 TX_EN_B 50 TX_CLK_B 51 IOVDD2 52 IOGND2 53 RXD3_B/ED_EN_B 54 PFBIN4 55 COREGND2 56 RXD2_B 57 RXD1_B/PHYAD4 58 RXD0_B/PHYAD3 59 COL_B 60 RX_ER_B/MDIX_EN_B 61 CRS_B/CRS_DV_B/LED_CFG_B 62 RX_DV_B/MII_MODE_B 63 RX_CLK_B 64 IOGND3 65 IOVDD3 66 MDIO 67 MDC 68 CLK2MAC 69 X2 70 X1 71 RESET_N 72 RESERVED 73 RESERVED 74 RESERVED 75 RESERVED 76 RESERVED 77 IOGND4 78 IOVDD4 79 RX_CLK_A 80 RX_DV_A/MII_MODE_A

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2.0 Configuration

This section in clude s inform atio n on the var ious con figura tion options available with the DP83849C. The configuration options described below include:

— Auto-Negotiation — PHY Address and LEDs — Half Duplex vs. Full Duplex — Isolate mode — Loopback mode —BIST

2.1 Auto-Negotiation

The Auto-Negotiation function provides a mechanism for exchanging configuration information between two ends of a link segment and automatically selecting the highest per formance mode of operation supported by both devices. Fast Link Pulse (FLP) Bursts provide the signalling used to communicate Auto-Negotiation abilities between two devices at each end of a link segment. For further detail regarding Auto-Negotiation, refer to Clause 28 of the IEEE

802.3u specification. The DP83849C supports four differ ent Ethernet protocols (10 Mb/s Half Duplex, 10 Mb/s Full Duplex, 100 Mb/s Half Duplex, and 100 Mb/s Full Duplex), so the inclusion of Auto-Negotiation ensures that the high est performance protocol will be selected based on the advertised ability of the Link Partner. The Auto-Negotiation function within the DP83849C can be controlled either by internal register access or by the use of the AN_EN, AN1 and AN0 pins.

2.1.1 Auto-Negotiation Pin Control

The state of AN_EN, AN0 an d AN1 det ermine s wheth er the DP83849C is forced into a specific mode or Auto-Negotiation will advertise a specific ability (or set of abilities) as given in be selected without requiring internal register access.

The state of AN _EN, AN0 and A N1, upon po wer-up/ reset, determines the state of bits [8:5] of the ANAR register.

The Auto-Negotiation function selected at power-up or reset can be cha nged at any time by writin g to the Basic Mode Contro l Register (BMCR) at addre ss 00h.

Table 1. These pins allow configuration options to

Table 1. Auto-Negotiation Modes

AN_EN AN1 AN0 Forced Mode

0 0 0 10BASE-T, Half-Duplex 0 0 1 10BASE-T, Full-Duplex 0 1 0 100BASE-TX, Half-Duplex 0 1 1 100BASE-TX, Full-Duplex

AN_EN AN1 AN0 Advertised Mo0e

1 0 0 10BASE-T, Half/Full-Duplex 1 0 1 100BASE-TX, Half/Full-Duplex 1 1 0 10BASE-T Half-Duplex

100BASE-TX, Half-Duplex

1 1 1 10BASE-T, Half/Full-Duplex

100BASE-TX, Half/Full-Duplex

2.1.2 Auto-Negotiation Register Control

When Auto-Negotiation is enabled, the DP83849C transmits the abilities programmed into the Auto-Negotiation Advertisement register (ANAR) at address 04h via FLP Bursts. Any combination of 10 Mb/s, 100 Mb/s, HalfDuplex, and Full Duplex modes may be se lected.

Auto-Negotiation Priority Resolution: — (1) 100BASE-TX Full Duplex (Highest Priority)

— (2) 100BASE-TX Half Duplex — (3) 10BASE-T Full Duplex — (4) 10BASE-T Half Duplex (Lowest Priority) The Basic Mode Control Register (BMCR) at address 00h

provides control for enabling, disabling, and restarting the Auto-Negotiation process. When Auto-Negotiation is dis abled, the Speed Selection bit in the BMCR controls switching between 10 Mb/s or 100 Mb/s operation, and the Duplex Mode bit controls switching between full duplex operation and half duplex operation. The Speed Selection and Duplex Mode bits have no effect on the mode of oper ation when the Auto-Negotiation Enable bit is set.

The Link Speed can be examined through the PHY Status Register (PHYSTS) at address 10h after a Link is achieved.

The Basic Mode Status Register (BMSR) indicates the set of available abilities for technology types, Auto-Negotiation ability, and Extended Register Capability. These bits are permanently set to indicate the full functionality of the DP83849C (only the 100BASE-T4 bit is not set since the DP83849C does not support that function).

The BMSR also provides status on: — Whether or not Auto-Negotiation is complete — Whether or not the Link Partner is advertising that a re-

mote fault has occurred — Whether or not valid link has been established — Support for Management Frame Preamble suppression The Auto-Negotiation Advertisement Register (ANAR) indi-

cates the Auto-Negotiation abilities to be advertised by the DP83849C. All available abilities are transmitted by default, but any ability can be suppressed by writing to the

DP83849C

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ANAR. Updating the ANAR to suppress an ability is one way for a management agent to change (restrict) the tech nology that is used.

The Auto-Negotiation Link Partner Ability Register (ANLPAR) at address 05h is used to receive the base link code word as well as all next page code words during the negotiati on. Furthermore, the ANLPAR will be updat ed to either 0081h or 0021h for parallel detection to either 100 Mb/s or 10 Mb/s respectively.

The Auto-Negotiation Expansion Register (ANER) indicates additional Auto-Negotiation status. The ANER provides status on:

— Whether or not a Parallel Detect Fault has occurred — Whether or not the Link Partne r supp orts the Next Pag e

function

— Whether or not the DP83849C supports the Next Page

function

— Whether or not the current page being exchanged by

Auto-Negotiation has been receiv ed

— Whether or not the Link Partner supports Auto-Negotia-

tion

2.1.3 Auto-Negotiation Parallel Detection

The DP83849C supports the Parallel Detection function as defined in the IEEE 802.3u specifi ca tio n. Para lle l De tect io n requires both the 10 Mb/s and 100 Mb/s receivers to moni tor the receive signal and report link status to the AutoNegotiation function. Auto-Negotiation uses this informa tion to configure th e corre ct techno logy i n the e vent th at the Link Partner does not support Auto-Negotiation but is transmitting link signals that the 100BASE-TX or 10BASET PMAs recognize as valid link signa ls .

If the DP83849C completes Auto-Negotiation as a result of Parallel Detection, bits 5 and 7 within the ANLPAR register will be set to reflect the mode of operation present in the Link Partner. Note that bits 4:0 of the ANLPAR will also be set to 00001 based on a successful parallel detection to indicate a valid 802.3 selector field. Software may deter mine that negotiation completed via Parallel Detection by reading a zero in the Link Partn er Au to-N eg oti ati on Ab le b it once the Auto-Negotiat io n Compl ete b it i s s et. I f co nfi gure d for parallel detect mode and any condition other than a sin gle good link occurs then the parallel detect fault bit will be set.

2.1.4 Auto-Negotiation Restart

Once Auto-Negotiation has completed, it may be restarted at any time by setting bit 9 (Res tart Auto- Negotiat ion) of th e BMCR to one. If the mode confi gured b y a su cces sful Au toNegotiation loses a valid link, then the Auto-Negotiation process will resume and attempt to determine the configu ration for the link. This function ensures that a valid configuration is maintained if the cable becomes disconnected.

A renegotiation requ es t fro m any en tity, such as a ma nag e ment agent, will cause the DP83849C to halt any transmit data and link pulse activity until the break_link_timer expires (~1500 ms). Consequently, the Link Partner will go into link fail and normal Auto-Negotiation resumes. The DP83849C will resume Auto-Negotiation after the break_link_timer has expired by issuing FLP (Fast Link Pulse) bursts.

2.1.5 Enabling Auto-Negotiation via Software

It is important t o no te that if the DP83849C has been ini tia l ized upon power-up as a non-auto-negotiating device (forced technology), and it is then requ ire d that Auto-Negotiation or re-Auto-Negotiation be initiated via software,

12 (Auto-Negotiation Enable) of the Basic Mode Control

bit Register (BMCR) must first be cleared and then set for any Auto-Negotiation function to take effect.

2.1.6 Auto-Negotiation Complete Time

Parallel detection and Auto-Negotiation take approximately 2-3 seconds to co mp let e. In addition, Auto-Negotiation wi th next page should take approximately 2-3 seconds to com plete, depending on the number of next pages sent.

Refer to Clause 28 of the IEEE 802.3u standard for a full description of the individual timers related to Auto-Negotiation.

2.2 Auto-MDIX

When enabled, this function utilizes Auto-Negotiation to determine the proper configuration for transmission and reception of data and subsequently selects the appropriate MDI pair for MD I/ MD IX o pe ra ti on. T h e fu nc t io n us es a r an dom seed to control switching of the crossover circuitry. This implementati on co mplie s with the corres po ndi ng IEEE

802.3 Auto-Negotiation and Crossover Specifications. Auto-MDIX is enabled by default and can be confi gu red vi a

strap or via PHYCR (19h) r egister, bits [15:14]. Neither Auto-Negotiation nor Auto-MDIX is required to be

enabled in forcing crossover of the MDI pairs. Forced crossover can be achieved through the FORCE_MDIX bit, bit 14 of PHYCR (19h) register.

Note: Auto-MDIX will not work in a forced mode of operation.

2.3 PHY Address

The 4 PHY address inputs pins are shown below.

Table 2. PHY Address Mapping

Pin # PHYAD Function RXD Function

4 PHYAD1 RXD0_A

5 PHYAD2 RXD1_A 58 PHYAD3 RXD0_B 57 PHYAD4 RXD1_B

The DP83849C provides four address strap pins for determining the PHY addresses for ports A and B of the device. The 4 address strap pins provide the upper four bits of the PHY address. The lowest bit of the PHY address is depen dent on the port. Port A has a value of 0 for the PHY address bit 0 while port B has a value of 1. The PHY address strap input pins are shown in

The PHY address strap information is latched into the PHYCR register (address 19h, bits [4:0]) at device powerup and hardware reset. The PHY Address pins are shared with the RXD pins. Each DP83849C or port sharing an

Table 2.

DP83849C

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MDIO bus in a system must have a unique physical address.

The DP83849C supports PHY Address strapping of Port A to even values 0 (<0000_0>) through 30 (<1111_0>). Port B is strapped to odd values 1 (<0000_1>) through 31 (<1111_1>). Note that Port B address is always 1 greater than Port A address.

For further detail rela ting to the la tch -in timi ng requi rement s of the PHY Address pins, as well as the other hardware configuration pins, refer to the Reset summary in Section 6.0.

Refer to Figure 2 for an exam ple o f a PH YAD connectio n to external components. In this example, the PHYAD strapping results in address 00010 (02h) for Port A and address 00011 (03h) for Port B.

DP83849C

2.3.1 MII Isolate Mode

The DP83849C can be put into MII Isolate mode by writing to bit 10 of the BMCR register.

When in the MII isolate mode, the DP83849C does not respond to packet data present at TXD[3:0], TX_EN inputs and presents a high impedance on the TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL, and CRS outputs. When in Isolate mode, the DP83849C will continue to respond to all management transactions.

While in Isolate mod e, th e PM D ou tput pair will not transmit packet data but will continue to source 100BASE-TX scrambled idles or 10BASE-T normal link pulses.

The DP83849C can Auto-Negotiate or parallel detect to a specific technology depending on the receive signal at the PMD input pair. A valid link can be established for the receiver even when the DP83849C is in Isolate mode.

RXD1_B

PHYAD4= 0

RXD0_B

Figure 2. PHYAD Strapping Example

RXD1_A

PHYAD2 = 0PHY AD3 = 0

RXD0_A

PHYAD1 = 1

2.2kΩ

VCC

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2.4 LED Interface

The DP83849C supports three configurable Light Emitting Diode (LED) pins for each port.

Several functions can be multiplexed onto the three LEDs using three different modes of operation. The LED operation mode can be selected by writing to the LED_CFG[1:0]

Table 3. LED Mode Select

Mode LED_CFG[1] LED_CFG[0] LED_LINK LED_SPEED LED_ACT/LED_COL

1 don’t care 1 ON for Good Link

OFF for No Link

2 0 0 ON for Good Link

BLINK for Activity

3 1 0 ON for Good Link

BLINK for Activity

register bits in the PHY Control Register (PHYCR) at address 19h, bits [6:5]. In addition, LED_CFG[0] for each port can be set by a strap option on the CRS_A and CRS_B pins. LED_CFG[1] is only controllable through reg ister access and cannot be set by as strap pin.

See Table 3 for LED Mode selection.

ON in 100 Mb/s OFF in 10 Mb/s ON in 100 Mb/s OFF in 10 Mb/s ON in 100 Mb/s OFF in 10 Mb/s

ON for Activity OFF for No Activity ON for Collision OFF for No Collision ON for Full Duplex OFF for Half Duplex

DP83849C

The LED_LINK pin in Mode 1 indicates the link status of the port. In 100BASE-T mode, link is established as a result of input receive amplitude compliant with the TPPMD specifications which will result in internal generation of signal detect. A 10 Mb/s Link is est abli shed as a result of the reception of at least seven consecutive normal Link Pulses or the reception of a valid 10BASE-T packet. This will cause the as sertion of LED_LINK. LED_LINK wil l deas sert in accordance with the Link Loss Timer as specified in the IEEE 802.3 specification.

The LED_LINK p in in Mode 1 w i ll be O FF w h en no LI N K is present.

The LED_LINK pin in Mode 2 and Mode 3 will be ON to indicate Link is good and BLINK to indicate activity is present on activity. The BLINK frequency is defined in BLINK_FREQ, bits [7:6] of register LEDCR (18h).

Activity is defined as configured in LEDACT_RX, bit 8 of register LEDCR (18h). If LEDACT_RX is 0, Activity is sig naled for either transmit or receive. If LEDACT_RX is 1, Activity is only signaled for receive.

The LED_SPEED pin indicates 10 or 100 Mb/s data rate of the port. The LED is ON when operating in 100Mb/s mode and OFF when operating in 10Mb/s mode. The functional ity of this LED is independent of mode selected.

The LED_ACT/LED_COL pin in Mo de 1 ind ic ates the pre sence of either transmit or receive activity. The LED will be ON for Activity and OFF for No Activity. In Mode 2, this pin indicates the Collision status of the port. The LED will be ON for Collision and OFF for No Collision.

The LED_ACT/LED_COL pin in Mode 3 indicates Duplex status for 10 Mb/s or 100 Mb/s operation. The LED will be ON for Full Duplex and OFF for Half Duplex.

In 10 Mb/s half duplex mode, the collision LED is based on the COL signal.

Since these LED pins are also used as strap options, the polarity of the LED is dependent on whether the pin is pulled up or down.

2.4.1 LEDs

Since the Auto-Negotiation (AN) strap options share the LED output pins, the external components required for strapping and LED usage must be considered in order to avoid contention.

Specifically, when the LED outputs are used to drive LEDs directly, the active state of each output driver is dependent on the logic level sampled by the corresponding AN input upon power-up/reset. For example, if a given AN input is resistively pulled low then the corresponding output will be configured as an active high driver. Conversely, if a given AN input is resistively pulled high, then the corresponding output will be configured as an active low driver.

Refer to Figure 3 for an example of AN connections to external components at port A. In this example, the AN strapping results in Auto-Negotiation disabled with 100 Full-Duplex forced.

The adaptive nature of the LED outputs helps to simplify potential implemen t ation issue s of th ese du al purp ose p ins.

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LED_ACT/LED_COL_

AN_EN_A = 0

2.2kΩ 165Ω

GND

Figure 3. AN Strapping and LED Loading Example

LED_SPEED_A

AN1_A = 1

165Ω

LED_LINK_A

AN0_A = 1

165Ω

VCC

All modes of operation (100BASE-TX, 10BASE-T) can run either half-duplex or full-duplex. Additionally, other than CRS and Collision reporting, all remaining MII signaling remains the same regardless of the selected duplex mode.

It is important to understand that while Auto-Negotiation with the use of Fast Link Pulse code words can interpret and configure to full-duplex operation, parallel detection can not recognize the difference between full and halfduplex from a fixed 10 Mb/s or 100 Mb/s link partner over twisted pair. As specified in the 802.3u specification, if a far-end link partner is configured to a forced full duplex 100BASE-TX ability, the parallel detection state machine in the partner would be unable to detect the full duplex capa bility of the far-end link partner. This link segment would negotiate to a half duplex 100BASE-TX configuration (same scenario for 10Mb/s).

2.6 Internal Loopback

The DP83849C includes a Loopback Test mode for facilitating system diagnostics. The Loopback mode is selected through bit 14 (Loopback) of the Basic Mode Control Reg ister (BMCR). Writing 1 to this bit enables MII transmit data to be routed to the MII receive outputs. Loopback status may be checked in bit 3 of the PHY Status Register (PHYSTS). While in Loopback mode the data will not be transmitted onto the media. To ensure that the desired operating mode is maintained, Auto-Negotiation should be disabled before selecting the Loopback mode.

DP83849C

2.4.2 LED Direct Control

The DP83849C provides another option to directly control any or all LED outputs throu gh the LED Di rect Contro l Reg ister (LEDCR), address 18h. The register does not provide read access to LEDs.

2.5 Half Duplex vs. Full Duplex

The DP83849C supports both half and full duplex operation at both 10 Mb/s and 100 Mb/s speeds.

Half-duplex relies on the C SMA/C D protoc ol t o handl e colli sions and network access. In Half-Duplex mode, CRS responds to both transmit and receive activity in order to maintain compliance with the IEEE 802.3 specification.

Since the DP83849C is designed to support simultaneous transmit and receiv e act ivi ty it is capabl e of su ppor tin g full duplex switched ap pli ca tio ns with a throughput of up to 200 Mb/s per port when operating in 100BASE-TX. Because the CSMA/CD protocol does not apply to full-duplex opera tion, the DP8384 9C d is abl es its own internal collisio n s en sing and reporting functions and modifies the behavior of Carrier Sense (CRS) such that it indicates only receive activity. This allows a full-duplex capable MAC to operate properly.

2.7 BIST

The DP83849C incorporates an internal Built-in Self Test (BIST) circuit to accommodate in-circuit testing or diagnos

tics. The BIST circuit can be utilized to test the integrity of

the transmit and receive data paths. BIST testing can be performed with the part in the internal loopback mode or externally looped back using a loopback cable fixture.

The BIST is implemented with independent transmit and receive paths, with the tran sm it bl ock gene rati ng a con tin u ous stream of a pseudo random sequence. The user can select a 9 bit or 15 bit pseudo random sequence from the PSR_15 bit in the PHY Control Register (PHYCR). The received data is compared to the generated pseudo-ran dom data by the BIST Linear Feedback Shift Register (LFSR) to determine the BIST pass/fail status.

The pass/fail status of the BIST is stored in the BIST status bit in the PHYCR reg ister. The status bit defaults to 0 (BIST fail) and will transition on a successful comparison. If an error (mis-compare) occurs, the status bit is latched and is cleared upon a subsequent write to the Start/Stop bit.

For transmit VOD testing, the Packet BIST Continuous Mode can be used to allow continuous data transmission, setting BIST_CONT_MODE, bit 5, of CDCTRL1 (1Bh).

The number of BIST errors can be monitored through the BIST Error Count in the CDCTRL1 (1Bh), bits [15:8].

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3.0 MAC Interface

The DP83849C supports several modes of operation using the MII interface pins. The optio ns are defi ned in th e foll ow ing sections and include:

— MII Mode — RMII Mode — 10 Mb Serial Network Interface (SNI) The modes of operation can be selected by strap options

or register control. For RMII mode, it is recommended to use the strap option, since it requires a 50 MHz clock instead of the normal 25 MHz.

In each of these modes, the IEEE 802.3 serial management interface is operational for device configuration and status. The serial management interface of the MII allows for the configuration and control of multiple PHY devices, gathering of status, error information, and the determina tion of the type and capabilities of the attached PHY(s).

3.1 MII Interface

The DP83849C incorporates the Media Independent Interface (MII) as specified in Clause 22 of the IEEE 802.3u standard. This interface may be used to connect PHY devices to a MAC in 10/100 Mb/s systems. This section describes the nibble wide MII data interface.

The nibble wide MII data interface consis t s of a rec ei ve bu s and a transmit bus each with control signals to facilitate data transfer between the PHY and the upper layer (MAC).

transmit cloc k TX_CL K which runs at ei ther 2. 5 MHz or 25 MHz.

Additionally, the MII includes the carrier sense signal CRS, as well as a collision detect signal COL. The CRS signal asserts to indicate the reception of data from the network or as a function of transmit data in Half Duplex mode. The COL signal asse rt s as an indication of a collisio n w hi ch ca n occur during half-duplex operation when both a transmit and receive operation occur simultaneously.

3.1.2 Collision Detect

For Half Duplex, a 10BASE-T or 100BASE-TX collision is detected when the receive and transmit channels are active sim ultaneously. Collisions ar e reported by the CO L signal on the MII.

If the DP83849C is transmitting in 10 Mb/s mode when a collision is dete cted, the collision is not r eported until seven bits have been received while in the collision state. This prevents a collision being reported incorrectly due to noise on the network. The COL signal remains set for the dura tion of the collision.

If a collision occ urs du ring a receive operation, it is immed iately reported by the COL signal.

When heartbeat is enabled (only applicable to 10 Mb/s operation), approximately 1µs after the transmission of each packet, a Si gn al Q u ali ty Error (SQE) signal of approx imately 10 bit times is generated (internally) to indicate successful transmiss io n. SQ E is repo rted as a pul se on th e COL signal of the MII.

DP83849C

3.1.1 Nibble-wide MII Data Interface

Clause 22 of the IEEE 802.3u specification defines the Media Independent Interface. This interface includes a dedicated recei ve bu s an d a dedicated transmit bus. T hes e two data buses, along with various control and status sig nals, allow for the simultaneous exchange of data between the DP83849C and the upper layer agent (MAC).

The receive interface consists of a nibble wide data bus RXD[3:0], a receive error signal RX_ER, a receive data valid flag RX_DV, and a receive clock RX_CLK for syn chronous transfer of the data. The receive clock operates at either 2.5 MHz to support 10 Mb/s operation modes or at 25 MHz to support 100 Mb/s operational modes.

The transmit interface consists of a nibble wide data bus TXD[3:0], a transmit enable control signal TX_EN, and a

3.1.3 Carrier Sense

Carrier Sense (CRS) is asserted due to receive activity, once valid data is detected via the squelch function during 10 Mb/s operation. During 100 Mb/s operation CRS is asserted when a valid link (SD) and two non-contiguous zeros are detected on the line.

For 10 or 100 Mb/s Half Duple x op era tio n, C RS is a sserted during either packet transmission or reception.

For 10 or 100 Mb/s Full Duplex operation, CRS is asserted only due to receive activity.

CRS is deasserted following an end of packet.

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3.2 Reduced MII Interface

The DP83849C incorporates the Reduced Media Independent Interface (RMII) as specified in the RMII specification (rev1.2) from the RMII Consortium. This interface may be used to connect PHY devices to a MAC in 10/100 Mb/s systems using a reduced number of pins. In this mode, data is transferred 2-bits at a time using the 50 MHz RMII_REF clock for both transmit and receive. The follow ing pins are used in RMII mode:

—TX_EN —TXD[1:0] — RX_ER (optional for Mac) — CRS_DV — RXD[1:0] — X1 (RMII Reference clock is 50 MHz) In addition, the RMII mode supplies an RX_DV signal

which allows for a simpler method of recovering receive data without having to separate RX_DV from the CRS_DV indication. This is especially useful for diagnostic testing where it may be desirable to externally loop Receive MII data directly to the transmitter.

The RX_ER output may be used by the MAC to detect error conditions. It is asserted for symbol errors received during a pack et, False Carrier even ts, and also for FIFO underrun or overrun conditions. Since the Phy is required to corrupt receive data on an error, a MAC is not required to use RX_ER.

It is important to note that since both digital channels in the DP83849C share the X1/RMII_REF input, both channels must have RMII mod e enabled or both channels mus t have

RMII mode disabled. Either channel may be in 10Mb or 100Mb mode in RMII or non-RMII mode.

Since the reference clock operates at 10 times the data rate for 10 Mb/s operation, transmit data is sampled every 10 clocks. Likewise, receive data will be generated every 10th clock so that an attached device can sample the data every 10 clocks.

RMII mode requires a 50 MHz oscillator be connected to the device X1 pin. A 50 MHz crystal is not supported.

To tolerate potential frequency differences between the 50 MHz reference clock and the recovered receive clock, the receive RMII function includes a programmable elasticity buffer. The elasticity buffer is programmable to minimize propagation delay based on expected packet size and clock accuracy. This allows for supporting a range of packet sizes including jumbo frames.

The elasticity buffer will force Frame Check Sequence errors for packets which overrun or underrun the FIFO. Underrun and Overrun conditions can be reported in the RMII and Bypass Register (RBR). The following table indi cates how to program the elastic ity buf fer fifo (in 4-bit increments) based on expected max packet size and clock accuracy. It assumes both clocks (RMII Reference clock and far-end Transmitter clock) have the same accuracy.

Packet lengths can be scaled linearly based on accuracy (+/- 25ppm would allows packets twice as large). If the threshold setting must support both 10Mb and 100Mb operation, the setting should be made to support both speeds.

DP83849C

Table 4. Supported packet sizes at +/-50ppm frequency accuracy

Start Threshold

RBR[1:0]

01 (default) 2 bits 8 bits 2,400 bytes 9,600 bytes

10 6 bits 4 bits 7,200 bytes 4,800 bytes 11 10 bits 8 bits 12,000 bytes 9,600 bytes 00 14 bits 12 bits 16,800 bytes 14,400 bytes

Latency Tolerance Recommended Packet Size

at +/- 50ppm

100Mb 10Mb 100Mb 10Mb

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3.3 10 Mb Serial Network Interface (SNI)

The DP83849C incorporates a 10 Mb Serial Network Interface (SNI) which al lo ws a simple serial data in terf ace fo r 10 Mb only devices. This is also referred to as a 7-wire inter face. While there is no defined standard for this interface, it is based on early 10 Mb physical layer devices. Data is clocked serially at 10 MHz using separate transmit and receive paths. The following pins are used in SNI mode:

—TX_CLK —TX_EN —TXD[0] —RX_CLK —RXD[0] — CRS —COL

3.4 802.3u MII Serial Management Interface

3.4.1 Seri al Management Register A ccess

The serial management MII specification defines a set of thirty-two 16-bit status and control registers that are acces sible through the management interface pins MDC and MDIO. The DP83849C implements all the required MII reg isters as well as several optional registers. These registers are fully described in Section 7.0. A descri ption of the seria l management access protocol follows.

3.4.2 Serial Management Access Protocol

The serial co ntrol interface co nsists of two pins, Management Data Clock (MDC) and Management Data Input/Output (MDIO). MDC has a maximum clock rate of 25 MHz and no minimum rate. The MDIO line is bi-directional and may be shared by up to 32 devices. The MDIO frame for mat is shown below in Table 5.

In addition, the MDIO pin requires a pull-up resistor (1.5

Ω) which, during IDLE and turnaround, will pull MDIO

k high. In order to initialize the MDIO interface, the station

management entity sends a sequence of 32 contiguous logic ones on MDIO to provide the DP83849C with a sequence that can be used to establish synchronization. This preamble may be generated either by driving MDIO

high for 32 consecutive MDC clock cycles, or by simply allowing the MDIO pu ll-up re sisto r to pull th e MDIO p in hig h during which time 32 MDC clock cycles are provided. In addition 32 MDC clock cycles should be used to re-sync the device if an invalid start, opcode, or turnaround bit is detected.

The DP83849C waits until it has received this preamble sequence before responding to any other transaction. Once the DP83849C serial management port has been ini tialized no further preamble sequencing is required until after a power-on/reset, invalid Start, invalid Opcode, or invalid turnaround bit has occurred.

The St art co de is indicated by a <01> pattern. This assure s the MDIO line transitions from the default idle line state.

Turnaround is defined as an idle bit time inserted between the Register Address field and the Data field. To avoid con tention during a read transaction, no device shall actively drive the MDIO signal during the first bit of Turnaround. The addressed DP83849C drives the MDIO with a zero for the second bit of turnaround and follows this with the

required data. between MDC and th e MDIO as dr iven/re ceiv ed by the Sta-

tion (STA) and the DP83849C (PHY) for a typical register read access .

For write transactions, the station management entity writes data to the addressed DP83849C thus eliminating the requirement for MDIO Turnaround. The Turnaround time is filled by the management entity by inserting <10>. Figure 5 shows the timing relationship for a typical MII register write access.

Figure 4 shows the timing relationship

DP83849C

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Table 5. Typical MDIO Frame Format

DP83849C

MII Management

Serial Protocol

Read Operation <idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle> Write Operation <idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle>

MDC

MDIO

(STA)

MDIO

(PHY)

00011 110000000

Idle Start

Opcode

(Read)

PHY Address

(PHYAD = 0Ch)

(00h = BMCR)

0 0 011000100000000

Figure 4. Typical MDC/MDIO Read Operation

Idle

MDC

MDIO

(STA)

00011110000000

Idle Start

Opcode

(Write)

PHY Address

(PHYAD = 0Ch)

(00h = BMCR)

Figure 5. Typical MDC/MDIO Write Operation

3.4.3 Serial Management Preamble Suppression

The DP83849C supports a Preamble Suppression mode as indicated by a one in bit 6 of the Basic Mode Status Register (BMSR, address 01h.) If the station management entity (i.e. MAC or other management controller) deter

mines that all PHYs in the system support Preamble Suppression by returning a one in this bit, then the station management entity need not generate preamble for each management transaction.

The DP83849C requires a single initialization sequence of 32 bits of preamble fol lo w ing hard ware/s oftware reset. This requirement is generally met by the mandatory pull-up resistor on MD I O in co nj unc ti o n wi th a co nt i nuo us MD C, or the management access made to determine whether Pre

amble Suppression is supported.

0 0 0 000 00000000

1000

Idle

While the DP83849C requires an initial preamble sequence of 32 bits for management initialization, it does not require a full 32-bit sequence between each subse quent transaction. A minimum of one idle bit between man- agement transactions is required as specified in the IEEE

802.3u specification.

3.4.4 Simultaneous Register Write

The DP83849C incorporates a mode which allows simultaneous write access to both Port A and B register blocks at the same time. This mode is selected by setting bit 15 of RMII and By pass Register (RBR, address 17h) in Port A.

As long as this bit remains set, subsequent writes to Port A will write to registers in both ports. Register reads are unaf fected. Each port must still be read individually.

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4.0 Architecture

This section describes the operations within each transceiver module, 100BASE-TX and 10BASE-T. Each operation consists of several functional blocks and described in the following:

— 100BASE-TX Transmitter — 100BASE-TX Receiver — 10BASE-T Transceiver Module

4.1 100BASE-TX TRANSMITTER

The 100BASE-TX transmitter consists of several functional blocks which conver t sy nchronous 4-bit ni bble d at a, as p ro vided by the MII, to a scrambled MLT-3 125 Mb/s serial data stream. Because the 100BASE-TX TP-PMD is integrated, the differential output pins, PMD Output Pair, can be directly routed to the magnetics.

The block diagram in Figure 6. provides an overview of each functional block within the 100BASE-TX transmit section.

The Transmitter section consists of the following functional blocks:

— Code-group Encoder and Injection block — Scrambler block (bypass option) — NRZ to NRZI encoder block — Binary to MLT-3 converter / Common Driver The bypass option for the functional blocks within the

100BASE-TX transmitter provides flexibility for applications where data conversion is not always required. The DP83849C implements the 100BASE-TX transmit state

machine diagram as specified in the IEEE 802.3u Stan dard, Clause 24.

DP83849C

125MHZ CLOCK

BP_SCR

100BASE-TX

LOOPBACK

TX_CLK

DIVIDE

BY 5

MLT[1:0]

TXD[3:0] /

TX_EN

4B5B CODE-

GROUP

ENCODER &

5B PARALLEL

TO SERIAL

SCRAMBLER

MUX

NRZ TO NRZI

ENCODER

BINARY

TO MLT-3 /

COMMON

DRIVER

PMD OUTPUT PAIR

Figure 6. 100BASE-TX Transmit Block Diagram

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Table 13. 4B5B Code-Group Encoding/Decoding

DATA CODES

0 11110 0000 1 01001 0001 2 10100 0010 3 10101 0011 4 01010 0100 5 01011 0101 6 01110 0110 7 01111 0111 8 10010 1000 9 10011 1001 A 10110 1010

B 10111 1011 C 11010 1100 D 11011 1101 E 11100 1110 F 11101 1111

IDLE AND CONTROL CODES

H 00100 HALT code-group - Error code

I 11111 Inter-Packet IDLE - 0000 (Note 1)

J 11000 First Start of Packet - 0101 (Note 1) K 10001 Second Start of Packet - 0101 (Note 1) T 01101 First End of Packet - 0000 (Note 1) R 00111 Second End of Packet - 0000 (Note 1)

INVALID CODES

V 00000 V 00001 V 00010 V 00011 V 00101 V 00110 V 01000 V 01100

Note: Control code-groups I, J, K, T and R in data fields will be mapped as invalid codes, together with RX_ER asserted.

DP83849C

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4.1.1 Code-group Encoding and Injection

The code-group encoder converts 4-bit (4B) nibble data generated by the MAC into 5-bit (5B) code-groups for transmission. This conversion is required to allow control data to be combined with packet data code-groups. Refer

Table 13 for 4B to 5B code-group mapping details.

to The code-group encoder substitutes the first 8-bits of the

MAC preamble with a J/K code-group pair (11000 10001) upon transmission. The code-group encoder continues to replace subsequent 4B preamble and data nibbles with corresponding 5B code-groups. At the end of the transmit packet, upon the deassertion of Transmit Enable signal from the MAC, the code-group encoder injects the T/R code-group pair (01101 00111) indicating the end of the frame.

After the T/R code-group pair, the code-group encoder continuously injects IDLEs into the transmit data stream until the next transmit packet is detected (reassertion of Transmit Enable).

4.1.2 Scrambler

The scrambler is required to control the radiated emissions at the media connector and on the twisted pair cable (for 100BASE-TX applications). By scrambling the data, the total energy launched onto the cable is randomly distrib uted over a wide frequency range. Without the scrambler, energy levels at the PMD and on the cable could peak beyond FCC limitations at frequencies related to repeating 5B sequences (i.e., continuous transmission of IDLEs).

The scrambler is configured as a closed loop linear feedback shift register (LFSR) with an 11-bit polynomial. The output of the closed loop LFSR is X-ORd with the serial NRZ data from the code-group encoder. The result is a scrambled data stream with sufficient randomization to decrease radiated emissions at certain frequencies by as much as 20 dB. The DP83849C uses the PHY_ID (pins PHYAD [4:1]) to set a unique seed value.

transmit transformer primary winding, resulting in a MLT-3 signal.

The 100BASE-TX MLT-3 signal sourced by the PMD Output Pair common driver is slew rate controlled. This should be considered when selecting AC coupling magnetics to ensure TP-PMD Standard compliant transition times (3 ns < Tr < 5 ns).

The 100BASE-TX transmit TP-PMD function within the DP83849C is capable of sourcing only MLT-3 encoded data. Binary output from the PMD Output Pair is not possi ble in 100 Mb/s mode.

4.2 100BASE-TX RECEIVER

The 100BASE-TX receiver consists of several functional blocks which convert the scrambled MLT-3 125 Mb/s serial data stream to synchronous 4-bit nibble data that is pro vided to the MII. Because the 100BASE-TX TP-PMD is integrated, the differential input pins, RD±, can be directly routed from the AC coupling magnetics.

See Figure 7 for a block diagram of the 100BASE-TX receive function. This provides an overview of each functional block within the 100BASE-TX receive section.

The Receive section consists of the following functional blocks:

— Analog Front End — Digital Signal Processor — Signal Detect — MLT-3 to Binary Decoder — NRZI to NRZ Decoder — Serial to Parallel — Descrambler — Code Group Alignment —4B/5B Decoder — Link Integrity Monitor — Bad SSD Detection

DP83849C

4.1.3 NRZ to NRZI Encoder

After the transmit data stream has been serialized and scrambled, the data must be NRZI encoded in order to comply with the TP-PMD standard for 100BASE-TX trans mission over Category-5 Unshielded twisted pair cable.

4.1.4 Binary to MLT-3 Convertor

The Binary to MLT-3 conversion is accomplished by converting the serial binary data stream output from the NRZI encoder into two binary data streams with alternately phased logic one events. These two binary streams are then fed to the twisted pa ir out put dri ve r whic h co nverts the voltage to current and alternately drives either side of the

4.2.1 Analog Front End

In addition to the Digital Equalization and Gain Control, the DP83849C includes Analog Equalization and Gain Control in the Analog Front End. The Analog Equalization reduces the amount of Digital Equalization required in the DSP.

4.2.2 Digital Signal Processor

The Digital Signal Processor includes Adaptive Equalization with Gain Control and Base Line Wander Compensation.

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DP83849C

RX_DV/CRS

RX_DATA VALID

SSD DETECT

RX_CLK RXD[3:0] / RX_ER

4B/5B DECODER

SERIAL TO PARALLEL

CODE GROUP

ALIGNMENT

DESCRAMBLER

NRZI TO NRZ

DECODER

MLT - 3 TO BINARY

DECODER

LINK

INTEGRITY

MONITOR

SIGNAL

DETECT

DIGITAL

SIGNAL

PROCESSOR

ANALOG

FRONT

END

RD +/−

Figure 7. 100BASE-TX Receive Block Diagram

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