Datasheet CLC5612IN, CLC5612IMX, CLC5612IM Datasheet (NSC)

Features

■

130mA output current

■

0.15%, 0.02° differential gain, phase

■

1.5mA/ch supply current

■

90MHz bandwidth (Av= +2)

■

-87/-93dBc HD2/HD3 (1MHz)

■

17ns settling to 0.05%

■

290V/µs slew rate

■

Stable for capacitive loads up to 1000pf

■

Single 5V to ±5V supplies

Applications

■

Video line driver

■

Coaxial cable driver

■

Twisted pair driver

■

Transformer/coil driver

■

High capacitive load driver

■

Portable/battery-powered applications

■

A/D driver

Typical Application

Differential Line Driver with Load Impedance Conversion

Pinout

DIP & SOIC

General Description

The CLC5612 is a dual, low-cost, high-speed (90MHz) buffer which features user-programmable gains of +2, +1, and

-1V/V. The CLC5612 also has a new output stage that delivers high output drive current (130mA), but consumes minimal quiescent supply current (1.5mA/ch) from a single 5V supply. Its current feedback architecture, fabricated in an advanced complementary bipolar process, maintains consistent performance over a wide range of gains and signal levels, and has a linear-phase response up to one half of the -3dB frequency.

The CLC5612 offers 0.1dB gain flatness to 18MHz and differential gain and phase errors of 0.15% and 0.02°. These features are ideal for professional and consumer video applications.

The CLC5612 offers superior dynamic performance with a 90MHz small-signal bandwidth, 290V/µs slew rate and 6.2ns rise/fall times (2V

step

). The combination of low quiescent power, high output current drive, and high-speed performance make the CLC5612 well suited for many battery-powered personal communication/computing systems.

The ability to drive low-impedance, highly capacitive loads, makes the CLC5612 ideal for single ended cable applications. It also drives low impedance loads with minimum distortion. The CLC5612 will drive a 100Ω load with only -74/-86dBc second/third harmonic distortion (Av= +2, V

out

= 2Vpp, f = 1MHz).

With a 25Ω load, and the same conditions, it produces only -70/

-67dBc second/third harmonic distortion. It is also optimized for driving high currents into single-ended transformers and coils.

When driving the input of high-resolution A/D converters, the CLC5612 provides excellent -87/-93dBc second/third harmonic distortion (Av= +2, V

out

= 2Vpp, f = 1MHz, RL= 1kΩ) and fast

settling time.

CLC5612 Dual, High Output, Programmable Gain Buffer

N

June 1999

CLC5612

Dual, High Output, Programmable Gain Buffer

Printed in the U.S.A.

Maximum Output Voltage vs. R

10

9

)

8

pp

7 6 5 4 3

Output Voltage (V

2 1

10

VCC = ±5V

Vs = +5V

100

RL (Ω)

L

1000

R

m/2

1:n

R

eq

V

d/2

1

2

V

in

3

R

t

4

1kΩ

CLC5612

8

R

-

7

+

6

1kΩ

-

+

5

m/2

-V

d/2

R

t2

Note: Supplies and bypassing not shown.

Z

UTP

o

I

o

+

R

V

L

o

-

OUT1

-IN1

+IN1

-V

CC

1kΩ

-

+

1kΩ

-

+

+V

CC

OUT2

-IN2 +IN2

http://www.national.com 2

PARAMETERS CONDITIONS TYP MIN/MAX RATINGS UNITS NOTES Ambient Temperature CLC5612IN/IM +25°C +25°C 0 to 70°C -40 to 85°C

FREQUENCY DOMAIN RESPONSE

-3dB bandwidth V

o

= 0.5V

pp

75 50 50 50 MHz

V

o

= 2.0V

pp

62 57 54 52 MHz

-

0.1dB bandwidth Vo= 0.5V

pp

18 13 11 11 MHz

gain peaking <200MHz, V

o

= 0.5V

pp

0 0.5 0.9 1.2 dB

gain rolloff <30MHz, V

o

= 0.5V

pp

0.2 0.9 1.0 1.0 dB

linear phase deviation <30MHz, V

o

= 0.5V

pp

0.1 0.4 0.5 0.5 deg

differential gain NTSC, R

L

= 150Ω to -1V 0.09 – – – %

differential phase NTSC, R

L

= 150Ω to -1V 0.14 – – – deg

TIME DOMAIN RESPONSE

rise and fall time 2V step 5.5 9.0 9.7 10.5 ns settling time to 0.05% 1V step 20 28 45 70 ns overshoot 2V step 3 6.5 14 14 % slew rate 2V step 185 150 130 120 V/µs

DISTORTION AND NOISE RESPONSE

2

nd

harmonic distortion 2Vpp, 1MHz -74 -70 -67 -67 dBc

2V

pp

, 1MHz; RL= 1kΩ -79 -77 -72 -72 dBc

2V

pp

, 5MHz -65 -58 -58 -58 dBc

3

rd

harmonic distortion 2Vpp, 1MHz -86 -82 -79 -79 dBc

2V

pp

, 1MHz; RL= 1kΩ -81 -79 -76 -76 dBc

2V

pp

, 5MHz -60 -55 -53 -53 dBc

equivalent input noise

voltage (e

ni

) >1MHz 3.4 4.4 4.9 4.9 nV/√Hz

non-inverting current (i

bn

) >1MHz 6.3 8.2 9.0 9.0 pA/√Hz

inverting current (i

bi

) >1MHz 8.7 11.3 12.4 12.4 pA/√Hz

crosstalk (input referred) 10MHz, 1V

pp

-80 – – – dB

STATIC DC PERFORMANCE

input offset voltage 8 30 35 35 mV A

average drift 80 – – – µV/˚C

input bias current (non-inverting) 3 14 18 18 µAA

average drift 25 – – – nA/˚C

gain accuracy ±0.3 ±1.5 ±2.0 ±2.0 % A

internal resistors (R

f

, Rg) 1000 ±20% ±26% ±30% Ω power supply rejection ratio DC 48 45 43 43 dB common-mode rejection ratio DC 47 45 43 43 dB supply current (per amplifier) R

L

= ∞ 1.5 1.7 1.8 1.8 mA A

MISCELLANEOUS PERFORMANCE

input resistance (non-inverting) 0.41 0.29 0.26 0.26 MΩ input capacitance (non-inverting) 2.2 3.3 3.3 3.3 pF input voltage range, High 4.2 4.1 4.0 4.0 V input voltage range, Low 0.8 0.9 1.0 1.0 V output voltage range, High R

L

= 100Ω 4.0 3.9 3.8 3.8 V

output voltage range, Low R

L

= 100Ω 1.0 1.1 1.2 1.2 V

output voltage range, High R

L

= ∞ 4.1 4.0 4.0 3.9 V

output voltage range, Low R

L

= ∞ 0.9 1.0 1.0 1.1 V output current 100 80 65 40 mA output resistance, closed loop DC 400 600 600 600 mΩ

Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters.

+5V Electrical Characteristics

(Av= +2, RL= 100Ω,Vs= +5V1,Vcm= VEE+ (Vs/2), RLtied to Vcm, unless specified)

Absolute Maximum Ratings

supply voltage (VCC- VEE)

+

14V output current (see note C) 140mA common-mode input voltage

VEEto

V

CC

maximum junction temperature +150°C storage temperature range -65°C to +150°C lead temperature (soldering 10 sec) +300°C

Notes

A) J-level:spec is 100% tested at +25°C. B)The short circuit current can exceed the maximum safe

output current.

1) V

s

= VCC- V

EE

Reliability Information

Transistor Count 98 MTBF (based on limited test data) 285Mhr

3 http://www.national.com

PARAMETERS CONDITIONS TYP GUARANTEED MIN/MAX UNITS NOTES Ambient Temperature CLC5612IN/IM +25°C +25°C 0 to 70°C -40 to 85°C

FREQUENCY DOMAIN RESPONSE

-3dB bandwidth V

o

= 1.0V

pp

90 75 65 65 MHz

V

o

= 4.0V

pp

49 43 40 38 MHz

-

0.1dB bandwidth Vo= 1.0V

pp

17 12 10 10 MHz

gain peaking <200MHz, V

o

= 1.0V

pp

0 0.5 0.9 1.0 dB

gain rolloff <30MHz, V

o

= 1.0V

pp

0.2 0.5 0.7 0.7 dB

linear phase deviation <30MHz, V

o

= 1.0V

pp

0.2 0.4 0.5 0.5 deg

differential gain NTSC, R

L

=150Ω 0.15 0.4 – – %

differential phase NTSC, R

L

=150Ω 0.02 0.06 – – deg

TIME DOMAIN RESPONSE

rise and fall time 2V step 6.2 6.9 7.3 7.7 ns settling time to 0.05% 2V step 17 19 35 55 ns overshoot 2V step 10 16 18 18 % slew rate 2V step 290 250 220 200 V/µs

DISTORTION AND NOISE RESPONSE

2

nd

harmonic distortion 2Vpp, 1MHz -74 -70 -67 -67 dBc

2V

pp

, 1MHz; RL= 1kΩ -87 -80 -77 -77 dBc

2V

pp

, 5MHz -67 -61 -59 -59 dBc

3

rd

harmonic distortion 2Vpp, 1MHz -86 -82 -79 -79 dBc

2V

pp

, 1MHz; RL= 1kΩ -93 -88 -85 -85 dBc

2V

pp

, 5MHz -63 -59 -56 -56 dBc

equivalent input noise

voltage (e

ni

) >1MHz 3.4 4.4 4.9 4.9 nV/√Hz

non-inverting current (i

bn

) >1MHz 6.3 8.2 9.0 9.0 pA/√Hz

inverting current (i

bi

) >1MHz 8.7 11.3 12.4 12.4 pA/√Hz

crosstalk (input referred) 10MHz, 1V

pp

-80 – – – dB

STATIC DC PERFORMANCE

output offset voltage 3 30 35 35 mV

average drift 80 – – – µV/˚C

input bias current (non-inverting) 5 12 16 17 µA

average drift 40 – – – nA/˚C

gain accuracy ±0.3 ±1.5 ±2.0 ±2.0 %

internal resistors (R

f

, Rg) 1000 ±20% ±26% ±30% Ω power supply rejection ratio DC 48 45 43 43 dB common-mode rejection ratio DC 48 46 44 44 dB supply current (per amplifier) R

L

= ∞ 1.6 1.9 2.0 2.0 mA

MISCELLANEOUS PERFORMANCE

input resistance (non-inverting) 0.52 0.38 0.34 0.34 MΩ input capacitance (non-inverting) 1.9 2.85 2.85 2.85 pF common-mode input range

±

4.2

±

4.1

±

4.1

±

4.0 V

output voltage range R

L

= 100Ω

±

3.8

±

3.6

±

3.6

±

3.5 V

output voltage range R

L

= ∞

±

4.0

±

3.8

±

3.8

±

3.7 V output current 130 100 80 50 mA B output resistance, closed loop DC 400 600 600 600 mΩ

±5V Electrical Characteristics

(Av= +2, RL= 100Ω,VCC= ±5V, unless specified)

Notes

B)The short circuit current can exceed the maximum safe

output current.

Ordering Information

Model Temperature Range Description

CLC5612IN -40°C to +85°C 8-pin PDIP CLC5612IM -40°C to +85°C 8-pin SOIC CLC5612IMX -40°C to +85°C 8-pin SOIC tape and reel

Pac kage Thermal Resistance

Package

θθ

JC

θθ

JA

Plastic (IN) 65°C/W 130°C/W Surface Mount (IM) 50°C/W 145°C/W

http://www.national.com 4

+5V T ypical Performance

(Av= +2, RL= 100Ω,Vs= +5V1,Vcm= VEE+ (Vs/2), RLtied to Vcm, unless specified)

Non-Inverting Frequency Response

Vo = 0.5V

pp

Gain

Phase

Av = -1

Av = +2

Normalized Magnitude (1dB/div)

1M

10M

Frequency (Hz)

Frequency Response vs. Vo (Av = 2)

Vo = 0.1V

Vo = 1V

Vo = 2V

pp

Vo = 2.5V

pp

Magnitude (1dB/div)

1M

10M

100M

Frequency (Hz)

PSRR & CMRR

60

CMRR

50

PSRR

40

30

20

PSRR & CMRR (dB)

10

0

1k 10k 100M

100k 1M 10M

Frequency (Hz)

2nd & 3rd Harmonic Distortion, RL = 25Ω

-30

-40

3rd, 10MHz

Av = +1

100M

pp

Phase (deg)

0

-90

-180

-270

-360

-450

Frequency Response vs. R

Vo = 0.5V

pp

Gain

Phase

RL = 25Ω

Magnitude (1dB/div)

1M

10M

L

RL = 100Ω

Frequency (Hz)

Frequency Response vs. Vo (Av = 1)

Vo = 0.1V

pp

Vo = 2V

pp

Vo = 2.5V

pp

Magnitude (1dB/div)

1M

10M

Frequency (Hz)

Equivalent Input Noise

3.6

3.5

3.4

3.3

Inverting Current 10.8pA/√Hz

Non-Inverting Current 7.6pA/√Hz

3.2

3.1

Noise Voltage (nV/√Hz)

3.0 10k 100k 1M 10M

Voltage 3.1nV/√Hz

Frequency (Hz)

2nd & 3rd Harmonic Distortion, RL = 100Ω

-40

-50

3rd, 10MHz

RL = 1kΩ

100M

Vo = 1V

100M

pp

Phase (deg)

0

-90

-180

-270

-360

-450

15

Noise Current (pA/√Hz)

11

7

3

Gain Flatness & Linear Phase

Gain

Phase

Magnitude (0.1dB/div)

0

10

20

Frequency (MHz)

Frequency Response vs. Vo (Av = -1)

Vo = 0.1V

pp

Vo = 2V

pp

Vo = 2.5V

pp

Magnitude (1dB/div)

1M

10M

Frequency (Hz)

2nd & 3rd Harmonic Distortion

-50

Vo = 2V

pp

-60

3rd

RL = 1kΩ

-70

2nd

RL = 1kΩ

-80

Distortion (dBc)

-90

3rd

-100

RL = 100Ω

1M

Frequency (Hz)

2nd & 3rd Harmonic Distortion, RL = 1kΩ

-50

-60

3rd, 10MHz

Vo = 1V

100M

2nd

RL = 100Ω

30

pp

10M

0.4

0.3

0.2

Phase (deg)

0.1 0

-0.1

-0.2

-0.3

-50

-60

Distortion (dBc)

-70

2nd, 10MHz

3rd, 1MHz

2nd, 1MHz

-80 0 0.5 1 1.5 2 2.5

Output Amplitude (Vpp)

Large & Small Signal Pulse Response

Large Signal

Small Signal

-60

-70

Distortion (dBc)

-80

-90 0 0.5 1 1.5 2 2.5

Output Amplitude (Vpp)

Closed Loop Output Resistance

100

VCC = ±5V

10

1

0.1

Output Voltage (0.02V/div)

Time (10ns/div)

Output Resistance (Ω)

0.01 10k 100k 1M 10M

Frequency (Hz)

2nd, 10MHz

2nd, 1MHz

3rd, 1MHz

100M

-70

-80

2nd, 10MHz

2nd, 1MHz

Distortion (dBc)

-90

-100 0 0.5 1 1.5 2 2.5

3rd, 1MHz

Output Amplitude (Vpp)

IBN & VIO vs. Temperature

1.5

1

(mV)

0.5 -0.2

IO

0 -0.3

-0.5 -0.4

-1 -0.5

Offset Voltage V

V

IO

I

BN

-1.5

-60 -40 -20 0 20 40 60 80 100

Temperature (°C)

0

-0.1

-0.6

I

BN

(µA)

5 http://www.national.com

±5V T ypical Performance

(Av= +2, RL= 100Ω,VCC= ± 5V, unless specified)

Frequency Response

Vo = 1.0V

Gain

Phase

pp

Av = -1

Av = +1

Av = +2

Normalized Magnitude (1dB/div)

1M

10M

Frequency (Hz)

Frequency Response vs. Vo (Av = 2)

Vo = 0.1V

Vo = 1V

Vo = 5V

pp

Vo = 2V

pp

Magnitude (1dB/div)

1M

10M

Frequency (Hz)

Large & Small Signal Pulse Response

Large Signal

Small Signal

Output Voltage (0.5V/div)

Time (20ns/div)

2nd & 3rd Harmonic Distortion, RL = 25Ω

-30

-40

-50

3rd, 10MHz

2nd, 10MHz

-60

Distortion (dBc)

-70

3rd, 1MHz

2nd, 1MHz

-80 012345

Output Amplitude (Vpp)

Short Term Settling Time

0.2

0.15

0.1

0.05 0

-0.05

(% Output Step)

o

-0.1

V

-0.15

-0.2

1 10 100 1000 10000

Time (ns)

100M

Phase (deg)

0

-45

-90

-135

-180

-225

Frequency Response vs. R

Vo = 1.0V

pp

Gain

Phase

Magnitude (1dB/div)

1M

RL = 100Ω

RL = 25Ω

10M

L

Phase (deg)

RL = 1kΩ

0

-90

-180

-270

-360

-450

100M

Frequency (Hz)

Frequency Response vs. Vo (Av = 1)

Vo = 0.1V

Vo = 1V

Vo = 2V

pp

Vo = 5V

pp

Magnitude (1dB/div)

100M

1M

10M

100M

Frequency (Hz)

Differential Gain & Phase

0.1

Gain Pos Sync

Phase Neg Sync

0.2

0.150

0.1-0.1

0.05-0.2 0-0.3

Gain (%)

Phase Pos Sync

-0.7 1234

Gain Neg Sync

-0.05-0.4

-0.1-0.5

-0.15-0.6

-0.2

Number of 150 Ω Loads

2nd & 3rd Harmonic Distortion, RL = 100Ω

-40

-50

3rd, 10MHz

-60

2nd, 10MHz

-70

Distortion (dBc)

3rd, 1MHz

-80

2nd, 1MHz

-90 0 0.5 1 1.5 2 2.5

Output Amplitude (Vpp)

Long Term Settling Time

0.2

0.15

0.1

0.05 0

-0.05

(% Output Step)

o

-0.1

V

-0.15

-0.2 1µ10µ100µ1m 100m

10m

Time (s)

Gain Flatness & Linear Phase

Gain

Phase

0.2 0

-0.2

Phase (deg)

-0.4

-0.6

-0.8

Magnitude (0.1dB/div)

-1.0

-1.2

0

10 15 20 30

5

25

Frequency (MHz)

Frequency Response vs. Vo (Av = -1)

Vo = 1V

pp

Vo = 0.1V

pp

Vo = 5V

pp

Vo = 2V

pp

Magnitude (1dB/div)

1M

10M

100M

Frequency (Hz)

2nd & 3rd Harmonic Distortion vs. Frequency

-50

Vo = 2V

pp

-60

3rd

RL = 100Ω

Phase (deg)

-70

2nd

RL = 100Ω

-80

-90

Distortion Level (dBc)

-100

3rd

RL = 1kΩ

2nd

RL = 1kΩ

110

Frequency (MHz)

2nd & 3rd Harmonic Distortion, RL = 1kΩ

-50

-60

-70

3rd, 10MHz

2nd, 10MHz

-80

-90

Distortion (dBc)

2nd, 1MHz

3rd, 1MHz

-100

-110 012345

Output Amplitude (Vpp)

IBN & VOS vs. Temperature

91

80

(mV)

OS

7-1

6-2

5-3

Offset Voltage V

I

BN

V

OS

4

I

BN

(µA)

-4

-60 -20 20 60 100 140

Temperature (°C)

http://www.national.com 6

±5V Typical Channel Matching Performance

(Av= +2, RL= 100Ω,VCC= ± 5V, unless specified)

CLC5612 Operation

The CLC5612 is a current feedback buffer built in an advanced complementary bipolar process. The CLC5612 operates from a single 5V supply or dual ±5V supplies. Operating from a single 5V supply, the CLC5612 has the following features:

■

Gains of +1, -1, and 2V/V are achievable without external resistors

■

Provides 100mA of output current while consuming only 7.5mW of power

■

Offers low -79/-81dBc 2nd and 3rd harmonic distortion

■

Provides BW > 50MHz and 1MHz distortion < -75dBc at Vo= 2V

pp

The CLC5612 performance is further enhanced in ±5V supply applications as indicated in the

±5V Electrical

Characteristics

table and

±5V Typical Performance

plots.

If gains other than +1, -1, or +2V/V are required, then the CLC5602 can be used. The CLC5602 is a current feedback amplifier with near identical performance and allows for external feedback and gain setting resistors.

Current Feedback Amplifiers

Some of the key f eatures of current feedbac k technology are:

■

Independence of AC bandwidth and voltage gain

■

Inherently stable at unity gain

■

Adjustable frequency response with feedbac k resistor

■

High slew rate

■

Fast settling

Current feedback operation can be described using a simple equation. The voltage gain for a non-inverting or inverting current feedback amplifier is approximated by Equation 1.

Equation 1

where:

■

Avis the closed loop DC voltage gain

■

Rfis the feedback resistor

■

Z(jω) is the CLC5612’s open loop transimpedance gain

■

is the loop gain

The denominator of Equation 1 is approximately equal to 1 at low frequencies. Near the -3dB corner frequency, the interaction between Rfand Z(jω) dominates the circuit performance. The value of the feedback resistor has a large affect on the circuits performance. Increasing R

f

has the following affects:

■

Decreases loop gain

■

Decreases bandwidth

■

Reduces gain peaking

■

Lowers pulse response overshoot

■

Affects frequency response phase linearity

V V

A

1

R

Z(j )

o

in

v

f

=

+

ω

ZjRω

()

CLC5612 Design Information

Closed Loop Gain Selection

The CLC5612 is a current feedback op amp with Rf = Rg = 1kΩ on chip (in the package). Select from three closed loop gains without using any external gain or feedback resistors. Implement gains of +2, +1, and -1V/V by connecting pins 2 and 3 (or 5 and 6) as described in the chart below.

Gain

Input Connections

A

v

Non-Inverting (pins 3,5) Inverting (pins 2,6)

-1V/V ground input signal +1V/V input signal NC (open) +2V/V input signal ground

Channel Matching

Channel 2

Magnitude (0.5dB/div)

1M 10M 100M

Channel 1

Frequency (Hz)

Input Referred Crosstalk

-20

Vo = 1V

pp

-40

-60

-80

Magnitude (dB)

-100

-120 1M

Frequency (Hz)

Pulse Crosstalk

Active Output

Channel

Inactive Output

Channel

Active Channel

Amplitude (0.2V/div)

10M 100M

Time (10ns/div)

Amplitude (20mV/div)

Inactive Channel

7 http://www.national.com

The gain accuracy of the CLC5612 is excellent and stable over temperature change. The internal gain setting resistors, Rfand Rgare diffused silicon resistors with a process variation of ± 20% and a temperature coefficient of ˜ 2000ppm/°C. Although their absolute values change with processing and temperature, their ratio (Rf/Rg) remains constant. If an external resistor is used in series with Rg, gain accuracy over temperature will suffer.

Single Supply Operation (VCC= +5V, VEE= GND)

The specifications given in the

+5V Electrical Character-

istics

table for single supply operation are measured with a common mode voltage (Vcm) of 2.5V. Vcmis the voltage around which the inputs are applied and the output voltages are specified.

Operating from a single +5V supply, the Common Mode Input Range (CMIR) of the CLC5612 is typically +0.8V to +4.2V. The typical output range with RL=100Ω is +1.0V to +4.0V.

For single supply DC coupled operation, keep input signal levels above 0.8V DC. For input signals that drop below 0.8V DC, AC coupling and level shifting the signal are recommended. The non-inverting and inverting configurations for both input conditions are illustrated in the following 2 sections.

DC Coupled Single Supply Operation

Figures 1, 2, and 3 on the following page, show the recommended configurations for input signals that remain above 0.8V DC.

Figure 1: DC Coupled, Av= -1V/V Configuration

Figure 2: DC Coupled, Av= +1V/V Configuration

Figure 3: DC Coupled, Av= +2V/V Configuration

AC Coupled Single Supply Operation

Figures 4, 5, and 6 show possible non-inv erting and inverting configurations for input signals that go below 0.8V DC.

Figure 4: AC Coupled, Av= -1V/V Configuration

The input is AC coupled to prevent the need for level shifting the input signal at the source. The resistive voltage divider biases the non-inverting input to VCC÷2 = 2.5V (For VCC= +5V).

Figure 5: AC Coupled, Av= +1V/V Configuration

V

CC

Note: Rb provides DC bias for the non-inverting input.

R

, RL and Rt are tied to Vcm for minimum power

b

consumption and maximum output swing.

Channel 2 not shown.

V

o

R

L

V

in

V

cm

R

t

R

V

cm

b

V

cm

1 2 3

1kΩ

4

8

-

7

+

6

1kΩ

-

+

5

CLC5612

Select Rt to yield desired Rin = Rt||Rg, where Rg = 1kΩ.

6.8µF

+

0.1µF

V

CC

6.8µF

Note: Rt and RL are tied to Vcm for minimum power consumption and maximum output swing.

Channel 2 not shown.

V

o

R

L

V

cm

V

in

R

V

1 2 3

t

4

cm

1kΩ

-

+

1kΩ

-

+

CLC5612

1kΩ

8

7 6 5

+

0.1µF

V

CC

6.8µF

Note: Rt, RL and Rg are tied to Vcm for minimum power consumption and maximum output swing.

Channel 2 not shown.

V

o

R

L

V

cm

V

cm

V

in

R

V

1

1kΩ

2 3

t

4

CLC5612

cm

1kΩ

+

-

+

8

-

7 6

1kΩ

5

+

0.1µF

V

CC

6.8µF

Note: Channel 2 not shown.

V

o

V

CC

C

V

in

R

1 2 3

4

1kΩ

-

+

1kΩ

-

+

CLC5612

8 7 6

1kΩ

5

V V 2.5 Low frequency cutoff

where Rg = 1kΩ.

=− +

o

+

0.1µF

in

=

2RC

1

,

π

g

C

V

CC

6.8µF

Note: Channel 2 not shown.

V

o

V

CC

R

C

V

in

R

1 2

3

4

1kΩ

-

+

1kΩ

-

+

CLC5612

8 7 6

1kΩ

5

V V 2.5

=+

o

Low frequency cutoff whereR

in

+

0.1µF

1

=

2RC

π

RR

in

source

R

=>>

2

,

C

http://www.national.com 8

Figure 6: AC Coupled, Av= +2V/V Configuration

Dual Supply Operation

The CLC5612 operates on dual supplies as well as single supplies. The non-inverting and inverting configurations are shown in Figures 7, 8 and 9.

Figure 7: Dual Supply, Av= -1V/V Configuration

Figure 8: Dual Supply, Av= +1V/V Configuration

Figure 9: Dual Supply, A

v

= +2V/V Configuration

Load Termination

The CLC5612 can source and sink near equal amounts of current. For optimum performance, the load should be tied to Vcm.

Driving Cables and Capacitive Loads

When driving cables, double termination is used to prevent reflections. For capacitive load applications, a small series resistor at the output of the CLC5612 will improve stability and settling performance. The

Frequency Response vs. C

L

plot, shown below in Figure 10, gives the recommended series resistance value for optimum flatness at var ious capacitive loads.

Figure 10: Frequency Response vs. C

L

Transmission Line Matching

One method for matching the characteristic impedance (Zo) of a transmission line or cable is to place the appropriate resistor at the input or output of the amplifier. Figure 11 shows typical inverting and non-inverting circuit configurations for matching transmission lines.

Note: Channel 2 not shown.

y

V

CC

6.8µF

+

V

CC

6.8µF

+

V

o

V

CC

R

C

V

in

R

1 2

C

3 4

1kΩ

-

+

-

+

CLC5612

8 7 6

1kΩ

5

V 2V 2.5

=+

o

Low frequency cutoff whereR

0.1µF

in

=

R

RR

=>>

2

1

2RC

π

in

source

,

C

V

CC

6.8µF

+

V

o

1

V

in

R

t

R

b

2 3 4

0.1µF

1kΩ

CLC5612

+

1kΩ

+

-

6.8µF

V

EE

8

-

7 6

1kΩ

+

5

Note: Rb provides DC bias for the non-inverting input. Select Rt to yield desired Rin = Rt||1kΩ.

Channel 2 not shown.

0.1µF

V

CC

6.8µF

+

V

o

1

2

V

in

R

t

3 4

0.1µF

1kΩ

CLC5612

+

1kΩ

-

+

-

+

8 7

6

1kΩ

5

Note: Channel 2 not shown.

6.8µF

V

EE

0.1µF

V

o

1 2

V

in

R

t

3

4

0.1µF

1kΩ

CLC5612

+

1kΩ

+

-

8

-

7 6

1kΩ

+

5

Note: Channel 2 not shown.

0.1µF

6.8µF

V

EE

Vo = 1V

pp

CL = 10pF

Rs = 49.9Ω

CL = 100pF Rs = 17.4Ω

CL = 1000pF

Rs = 6.7Ω

+

-

Magnitude (1dB/div)

1k

1M

R

s

C

1k

L

1k

10M

100M

Frequency (Hz)

9 http://www.national.com

Non-inverting gain applications:

■

Connect pin 2 as indicated in the table in the

Closed Loop Gain Selection

section.

■

Make R1, R2, R6, and R7equal to Zo.

■

Use R3to isolate the amplifier from reactive loading caused by the transmission line, or by parasitics.

Inverting gain applications:

■

Connect R3directly to ground.

■

Make the resistors R4, R6, and R7equal to Zo.

■

Make R5II Rg= Zo.

The input and output matching resistors attenuate the signal by a factor of 2, therefore additional gain is needed. Use C6to match the output transmission line over a greater frequency range. C6compensates for the increase of the amplifier’s output impedance with frequency.

Figure 11:Transmission Line Matching

Power Dissipation

Follow these steps to determine the power consumption of the CLC5612:

1. Calculate the quiescent (no-load) power: P

amp

= ICC(VCC- VEE)

2. Calculate the RMS power at the output stage: Po= (VCC- V

load

) (I

load

), where V

load

and I

load

are the RMS voltage and current across the external load.

3. Calculate the total RMS power: Pt= P

amp

+ P

o

The maximum power that the DIP and SOIC, packages can dissipate at a given temperature is illustrated in Figure 12. The power derating curve for any CLC5612 package can be derived by utilizing the following equation:

where T

amb

= Ambient temperature (°C)

θJA= Thermal resistance, from junction to ambient,

for a given package (°C/W)

Figure 12: Power Derating Curve

Layout Considerations

A proper printed circuit layout is essential for achieving high frequency performance. Comlinear provides evaluation boards for the CLC5612 (CLC730038-DIP, CLC730036-SOIC) and suggests their use as a guide for high frequency layout and as an aid f or de vice testing and characterization.

General layout and supply bypassing play major roles in high frequency performance. Follow the steps below as a basis for high frequency layout:

■

Include 6.8µF tantalum and 0.1µF ceramic capacitors on both supplies.

■

Place the 6.8µF capacitors within 0.75 inches of the power pins.

■

Place the 0.1µF capacitors less than 0.1 inches from the power pins.

■

Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance.

■

Minimize all trace lengths to reduce series inductances.

■

Use flush-mount printed circuit board pins for prototyping, never use high profile DIP sockets.

Evaluation Board Information

A data sheet is available f or the CLC730038/ CLC730036 evaluation boards .The evaluation board data sheets provide:

■

Evaluation board schematics

■

Evaluation board lay outs

■

General information about the boards

The evaluation boards are designed to accommodate dual supplies. The boards can be modified to provide single supply operation. For best performance; 1) do not connect the unused supply, 2) ground the unused supply pin.

(175 T

amb

JA

°− )

θ

Z

R

Z

R

+

V

1

-

R

+

V

2

-

0

4

R

Z

0

1

R

1

1kΩ

-

2

5

R

3

2

3 4

+

1kΩ

-

+

CLC5612

1kΩ

C

8 7 6 5

Note: Channel 2 not shown.

0

6

V

o

R

7

1.0

IN

0.8

0.6

0.4

Power (W)

0.2

0

-40 -20 0 20 40 60 80 100 120 180

IM

140 160

Ambient Temperature (°C)

http://www.national.com 10

Special Evaluation Board Considerations for the CLC5612

To optimize off-isolation of the CLC5612, cut the Rftrace on both the CLC730038 and the CLC730036 evaluation boards. This cut minimizes capacitive feedthrough between the input and the output. Figure 13 shows where to cut both evaluation boards for improved off-isolation.

Figure 13: Evaluation Board Changes

SPICE Models

SPICE models provide a means to evaluate amplifier designs. Free SPICE models are available for Comlinear’s monolithic amplifiers that:

■

Support Berkeley SPICE 2G and its many derivatives

■

Reproduce typical DC, AC, Transient, and Noise performance

■

Support room temperature simulations

The

readme

file that accompanies the diskette lists released models, and provides a list of modeled parameters. The application note OA-18, Simulation SPICE Models for Comlinear’s Op Amps, contains schematics and a reproduction of the readme file.

Single Supply Cable Driver

Figure 14 below shows the CLC5612 driving 10m of 75Ω coaxial cable. The CLC5612 is set for a gain of +2V/V to compensate for the divide-by-two voltage drop at Vo. The response after 10m of cable is illustrated in Figure 15.

Figure 14: Single Supply Cable Driver

Figure 15: Response After 10m of Cable

Differential Line Driver With Load Impedance Conversion

The circuit shown in the

Typical Application

schematic on the front page and in Figure 16, operates as a differential line driver. The transformer converts the load impedance to a value that best matches the CLC5612’s output capabilities. The single-ended input signal is converted to a differential signal by the CLC5612. The line’s characteristic impedance is matched at both the input and the output. The schematic shows Unshielded Twisted Pair for the transmission line;other types of lines can also be driven.

Application Circuits

730036 Bottom

CLC730038 REV C

Cut traces here

730036 Top

+Vcc

+

-Vcc

OUT1

ROUT1

C1 C2

RF1

C3

+C4

RF2

OUT2

ROUT2

RIN1

RG1

RG2

GND

IN2

RIN2

10m of 75Ω

Coaxial Cable

V

o

75Ω

V

NOTE: Channel 2 not shown

Vin = 10MHz, 0.5V

100mV/div

in

0.1µF

75Ω

+5V

0.1µF

5kΩ

0.1µF

5kΩ

pp

1 2 3

4

1kΩ

-

+

1kΩ

-

+

CLC5612

1kΩ

+5V

6.8µF

+

0.1µF

8 7 6 5

(970) 226-0500

IN1

Cut traces here

20ns/div

11 http://www.national.com

Figure 16: Differential Line Driver with

Load Impedance Conversion

Set up the CLC5612 as a difference amplifier:

■

Set the Channel 1 amplifier to a gain of +1V/V

■

Set the Channel 2 amplifier to a gain of -1V/V

Make the best use of the CLC5612’s output drive capability as follows:

where Reqis the transformed value of the load impedance, V

max

is the Output Voltage Range, and I

max

is the

maximum Output Current. Match the line’s characteristic impedance:

Select the transformer so that it loads the line with a value very near Zoover frequency range. The output impedance of the CLC5612 also affects the match. With an ideal transformer we obtain:

where Z

o(5612)

(jω) is the output impedance of the

CLC5612 and |Z

o(5612)

(jω)| << Rm.

The load voltage and current will fall in the ranges:

The CLC5612’s high output drive current and low distortion make it a good choice for this application.

Differential Input/Differential Output Amplifier

Figure 17 below illustrates a differential input/differential output configuration. The bypass capacitors are the only external components required.

Figure 17: Differential Input/Differential

Output Amplifier

VnV

I

n

o

≤⋅

≤

max

R

m/2

1:n

R

V

d/2

1

1kΩ

2

V

in

3

1kΩ

R

t

4

CLC5612

1kΩ

8

-

7

+

6

1kΩ

-

+

5

eq

R

m/2

-V

d/2

R

t2

Note: Supplies and bypassing not shown.

Z

UTP

o

I

o

R

L

2V

⋅

RR

+=

meq

I

max

2

nZ j

ReturnLoss 20 log

=− ⋅

⋅

10

o 5612

()

Z

o

ω

()

,dB

Vin2

0.1µF

-5V

6.8µF

RZ

=

Lo

RR

=

meq

R

n

L

=

R

eq

+5V

1kΩ

V

1 – V

2 = (Vin1 – Vin2) x 2

out

6.8µF

CLC5612

V

1

in

0.1µF

1kΩ

V

2

out

V

1

out

CLC5612

Dual, High Output, Programmable Gain Buffer

http://www.national.com 12

Customer Design Applications Support

National Semiconductor is committed to design excellence. For sales, literature and technical support, call the National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018.

Life Support Policy

National’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of National Semiconductor Corporation. As used herein:

1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or sustain life, and whose failure to perfor m, when proper ly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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1111 West Bardin Road Fax: (+49) 0-180-530 85 86 2501 Miramar Tower Tel: 81-043-299-2309 Arlington, TX 76017 E-mail: europe.support.nsc.com 1-23 Kimberley Road Fax: 81-043-299-2408 Tel: 1(800) 272-9959 Deutsch Tel: (+49) 0-180-530 85 85 Tsimshatsui, Kowloon Fax:1(800) 737-7018 English Tel:(+49) 0-180-532 78 32 Hong Kong

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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

N

Datasheet CLC5612IN, CLC5612IMX, CLC5612IM Datasheet (NSC)

Specifications and Main Features

Frequently Asked Questions

User Manual