NSC CGS74C2525N, CGS74C2525MX, CGS74C2525M Datasheet
TL/F/10684
CGS74C2525
#
CGS74CT2525
#
CGS74C2526
#
CGS74CT2526
1-to-8 Minimum Skew Clock Driver
September 1995
CGS74C2525#CGS74CT2525
CGS74C2526
#
CGS74CT2526
1-to-8 Minimum Skew Clock Driver
The CGS ’C/CT2525 is a minimum skew clock driver with
one input driving eight outputs specifically designed for signal generation and clock distribution applications. The ’2525
is designed to distribute a single clock to eight separate
receivers with low skew across all outputs during both the
t
PLH
and t
PHL
transitions. The ’2526 is similar to the ’2525
but contains a multiplexed clock input to allow for systems
with dual clock speeds or systems where a separate test
clock has been implemented.
Features
Y
These CGS devices implement National’s FACT
TM
family
Y
Ideal for signal generation and clock distribution
Y
Guaranteed pin to pin and part to part skew
Y
Multiplexed clock input (’2526)
Y
Guaranteed 2 kV minimum ESD protection
Y
Symmetric output current drive of 24 mA for IOL/I
OH
Y
’CT has TTL-compatible inputs
Y
These products are identical to 74AC/ACT2525 and
2526
Y
Available as Mil/Aero versions
54AC/ACT2525
54AC/ACT2526
Logic Symbols
’2525
TL/F/10684– 1
’2526
TL/F/10684– 2
Connection Diagrams
Pin Assignment
for DIP and SOIC
’2525
TL/F/10684– 3
’2526
TL/F/10684– 4
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
FACT
TM
is a trademark of National Semiconductor Corporation.
C
1996 National Semiconductor Corporation RRD-B30M106/Printed in U. S. A.
http://www.national.com
Functional Description
On the multiplexed clock device, the SEL pin is used to
determine which CLKn input will have an active effect on
the outputs of the circuit. When SEL
e
1, the CLK1 input is
selected and when SEL
e
0, the CLK0 input is selected.
The non-selected CLKn input will not have any effect on the
logical output level of the circuit. The output pins act as a
single entity and will follow the state of the CLK or
CLK1/CLK0 pins when either the multiplexed (’2526) or the
straight (’2525) clock distribution chip is selected.
Pin Description
Pin Names Description
CLK Clock Input (’2525)
CLK0, CLK1 Clock Inputs (’2526)
O
0–O7
Outputs
SEL Clock Select (’2526)
Truth Tables
’2525
Inputs Outputs
CLK O0–O
7
LL
HH
’2526
Inputs Outputs
CLK0 CLK1 SEL O0–O
7
LXL L
HXL H
XLH L
XHH H
L
e
Low Voltage Level
H
e
High Voltage Level
X
e
Immaterial
’2525
TL/F/10684– 7
’2526
TL/F/10684– 8
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
CC
)
b
0.5V toa7.0V
DC Input Diode Current (IIK)
V
I
eb
0.5V
b
20 mA
V
I
e
V
CC
a
0.5V
a
0.2 mA
DC Input Voltage (VI)
b
0.5V to (V
CC
a
0.5V)
DC Output Diode Current (IOK)
V
O
e
0.5V
b
20 mA
V
O
e
V
CC
a
0.5V
a
20 mA
DC Output Voltage (VO)
b
0.5V to (V
CC
a
0.5V)
DC Output Source
or Sink Current (I
O
)
g
50 mA
DC VCCor Ground Current
per Output Pin (I
CC
or I
GND
)
g
50 MA
Storage Temperature (T
STG
)
b
65§Ctoa150§C
Junction Temperature (i
JA
)
Plastic (N) 14-Lead 102
§
C/W
Plastic (M) 14-Lead 128
§
C/W
Plastic (N) 16-Lead 97
§
C/W
Plastic (M) 16-Lead 124
§
C/W
Recommended Operating
Conditions
Supply Voltage (VCC)
‘C’ 2.0V to 6.0V
‘CT’ 4.5V to 5.5V
Input Voltage (V
I
) 0VtoV
CC
Output Voltage (VO) 0VtoV
CC
Operating Temperature (TA)
CGS74C/CT
b
40§Ctoa85§C
54AC/ACT
b
55§Ctoa125§C
Input Rise and Fall Times Devices
(30% to 70% of V
CC
)
V
CC
e
3.3V 10.5 ns max
4.5V 14.4 ns max
5.5V 17.6 ns max
Input Rise and Fall Times Devices
(0.8V to 2.0V) 9.6 ns max
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of CGS circuits outside databook specifications.
DC Electrical Characteristics for CGS74C and 54AC Family Devices
Over recommended operating conditions unless specified otherwise.
CGS74C 54AC CGS74C
Symbol Parameter
V
CC
T
A
ea
25§C
T
A
e
T
A
e
Units Conditions
(V)
b
55§Ctoa125§Cb40§Ctoa85§C
Typ Guaranteed Limits
V
IH
Minimum High Level 3.0 1.5 2.1 2.1 2.1 V
OUT
e
0.1V
Input Voltage 4.5 2.25 3.15 3.15 3.15 V or V
CC
b
0.1V
5.5 2.75 3.85 3.85 3.85
V
IL
Maximum Low Level 3.0 1.5 0.9 0.9 0.9 V
OUT
e
0.1V
Input Voltage 4.5 2.25 1.35 1.35 1.35 V or V
CC
b
0.1V
5.5 2.75 1.65 1.65 1.65
V
OH
Minimum High Level 3.0 2.99 2.9 2.9 2.9 I
OUT
eb
50 mA
Output Voltage 4.5 4.49 4.4 4.4 4.4 V
(Note 2) 5.5 5.49 5.4 5.4 5.4
V
IN
e
VILor V
IH
3.0 2.56 2.4 2.46
b
12 mA
4.5 3.86 3.7 3.76 V I
OH
b
24 mA
5.5 4.86 4.7 4.76
b
24 mA
V
OL
Maximum Low Level 3.0 0.002 0.1 0.1 0.1 I
OUT
e
50 mA
Output Voltage 4.5 0.001 0.1 0.1 0.1 V
(Note 2) 5.5 0.001 0.1 0.1 0.1
V
IN
e
VILor V
IH
3.0 0.36 0.40 0.44 12 mA
4.5 0.36 0.50 0.44 V
I
OL
24 mA
5.5 0.36 0.50 0.44 24 mA
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