NSC CGS701AV Datasheet

December 1995

CGS701AV
Commercial Low Skew PLL 1 to 8 CMOS Clock Driver
CGS701ATV
Industrial Low Skew PLL 1 to 8 CMOS Clock Driver

General Description

CGS701A is an off the shelf clock driver specifically de­signed for today’s high speed designs. It provides low skew
outputs which are produced at different frequencies from
three fixed input references. The XTALIN input pin is de­signed to be driven from a 25 MHz–40 MHz crystal oscilla­tor.

The PLL, using a charge pump and an internal loop filter,
multiplies this input frequency to create a maximum output
frequency of four times the input.

The device includes a TRI-STATE
the outputs. This feature allows for low frequency functional
testing and debugging.

Also included, is an EXTSEL pin to allow testing the chip via
an external source. The EXTSEL pin, once set to high, caus­es the External-ClockÐMUX to change its input from the
output of the VCO and Counter to the external clock signal
provided via SKWTST input pin. (continued)

control pin to disable

É

Features

Y

Guaranteed:
400 ps pin-to-pin skew (t
outputs.

Y

PentiumÉand PowerPCTMcompatible

Y

g

300 ps propagation delay

Y

Output buffer of eight drivers for large fanout

Y

25 MHz–160 MHz output frequency range

Y

Outputs operating at 4X, 2X, 1X of the reference fre­quency for multifrequency bus applications

Y

Selectable output frequency

Y

Internal loop filter to reduce noise and jitter

Y

Separate analog and digital VCCand ground pins

Y

Low frequency test mode by disabling the PLL

Y

Implemented on National’s Core CMOS process

Y

Symmetric output current drive:a30/b30 mA IOL/I

Y

Industrial temperature ofb40§Ctoa85§C

Y

28-pin PLCC for optimum skew performance

Y

Guaranteed 2k volts ESD protection

OSHL

and t

OSLH

)on1X

OH

CGS701AV Commercial Low Skew PLL 1 to 8 CMOS Clock Driver

CGS701ATV Industrial Low Skew PLL 1 to 8 CMOS Clock Driver

Connection Diagram

Pin Description

PLCC Package

Pin Assignment for PLCC

TL/F/11920– 1

TRI-STATE

is a registered trademark of National Semiconductor Corporation.

É

PentiumÉis a registered trademark of Intel Corporation.

TM

PowerPC

is a trademark of International Business Machines Corporation.

C

1996 National Semiconductor Corporation RRD-B30M106/Printed in U. S. A.

TL/F/11920

Pin Name Description

1V
2 FBK IN Feedback Input Pin
3 CLK4 4X Clock Output
4V
5 XTALIN Crystal Oscillator Input
6 GND Digital Ground
7 FBK OUT Feedback Output Pin
8V

9 CLK1Ðl 1X Clock Output
10 GND Digital Ground
11 CLK1Ð2 1X Clock Output
12 TRI-STATE Output TRI-STATE Control
13 SKWTST Skew Testing Pin
14 CLK1Ð3 1X Clock Output
15 GND Digital Ground
16 CLK1Ð4 1X Clock Output
17 V
18 SKWSEL Skew Test Selector Pin
19 GNDA Analog Ground
20 V
21 EXTSEL External Clock MUX Selector
22 GND Digital Ground
23 CLK1Ð5 1X Clock Output
24 V
25 CLK1Ð0 1X Clock Output
26 CLK1SEL CLK1 Multiplier Selector
27 GND Digital Ground
28 CLK2 2X Clock Output

CC

CC

CC

CC

CCA

CC

Digital V

CC

Digital V

CC

Digital V

CC

Digital V

CC

Analog V

CC

Digital V

CC

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CGS701A

General Description

CLK1SEL pin changes the output frequency of the
CLK1Ð0 thru CLK1Ð5 outputs. During normal operation,
when CLK1SEL pin is high, these outputs are at the same
frequency as the input crystal oscillator, while CLK2 and
CLK4 outputs are at twice and four times the input frequen­cy respectively.

Once CLK1SEL pin is set to a low logic level, the CLK1
outputs will be at twice the input frequency, the same as the
CLK2 output, with CLK4 output still being at four times the
input frequency.

(Continued)

Block Diagram

In addition, another pin is added for increasing the test ca­pability. SKWSEL pin allows testing of the counter’s output
and skew of the output drivers by bypassing the VCO. In this
test mode CLK4 frequency is the same as SKWTST input
frequency, while CLK2 is 1/2 and CLK1 frequencies are 1/4
respectively (refer to the Truth Table). In addition CLK1SEL
functionality is also true under this test condition.

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TL/F/11920– 2

Truth Table

CLK1 EXT EXT SKW SKW

SEL SEL CLK SEL TST

*H L X L X H 4xfin 2xfin fin

*L L X L X H 4xfin 2xfin 2xfin

XHÉXX H ÉÉ É

HLXHÉ H 1xftst (/2 x f tst (/4 x f tst

LLXHÉ H 1xftst (/2 x f tst (/2 x f tst

XXXXX L Z Z Z

*Steady state phase, frequency lock

Typical Application

CGS701A

Input Output

TRI-STATE CLK4 CLK2 CLK1

TL/F/11920– 3

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