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CGS410V
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NSC CGS410V Datasheet

TL/F/11919
CGS410 Programmable Clock Generator
September 1995
CGS410 Programmable Clock Generator
General Description
The CGS410 is a programmable clock generator which pro­duces a variable frequency clock output for use in graphics, disk drives and clock synchronizing applications. The CGS410 produces output clocks in CMOS and differential formats. The user is able to program the differential output levels to best suit the levels of the interfacing device. A common configuration allows PCLK to emulate positive ECL logic levels, eliminating the need for TTL to ECL translation.
The CGS410 is referenced off the XTLIN input which can be configured for either external crystal or external oscillator support. All internal frequency generation is referenced from the XTLIN input. The CGS410 can also be driven by EXTCLK as desired. EXTCLK may serve as the source from a fixed clock (for passthru mode), or as an external VCO input.
The primary loop structure of the CGS410 consists of pro­grammable N and R dividers. Both are contiguous; N can be any value between 2 and 16383, and R can be any value between 1 and 1023. Additional dividers of the internal VCO allow individual programmability for the PCLK, CMOSÐPCLK, and LCLK outputs.
An additional advantage of the CGS410 is its ability to per­form smooth, glitch-free clock output changes as the user selects passthru clock sources or changes the VCO frequency. A real-time synchronous load clock enable (LCLKÐEN) control input allows for the enabling and dis­abling of the LCLK output. This is suitable for applications which require the removal of an active LCLK during the blanking portion of a screen refresh.
On power-up the XTLIN frequency is internally divided by two and routed to the PCLK outputs, providing a known power-up output frequency with a 50% duty cycle. The CGS410 is programmed by a serial stream of data. A serial bit read can verify the contents of the register.
Features
Y
Fully programmable frequency generator
Y
Provides frequencies to 135 MHz
Y
Configurable high-speed complementary clock outputs
Y
CMOS output clocks
Y
Glitch-free transitions for clock changes
Y
Powers up in a known state
Y
Single supply (a5V) operation
Y
Low current draw, ideal for battery applications
Y
Read/write control register
Y
Internal VCO and loop filters
Connection Diagram
TL/F/11919– 1
Important Note: This device is sensitive to noise on certain pins, especially FREQCTL, FILTER, AVDD, and AGND. Special care must be taken with board layout for optimum performance.
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.
Table of Contents
1.0 FUNCTIONAL DESCRlPTION
2.0 PIN DEFlNlTIONS
3.0 CIRCUIT OPERATION
3.1 Internal VCO Operation
3.1.1 VCO Tuning Characteristics
3.2 Crystal Oscillator Operation
3.3 Phase Comparator Operation
3.4 Programmable Divider Operation
3.5 Control Register Operation
3.5.1 System Loading Sequence
3.5.2 Structure of the Internal Serial Control Register
3.5.3 Power-up conditions
3.6 Loop Filter Characteristics
3.6.1 Loop FiIter Calculations
3.7 Clock Deglitching Considerations
3.8 Configurable Differential Output Buffers
3.9 Termination Considerations
3.10 System Interface Considerations
3.11 Applications
3.12 Input/Output Structures
4.0 DEVICE SPEClFICATIONS
4.1 Absolute Maximum Ratings
4.2 Recommended Operating Conditions
4.3 DC Electrical Characteristics
4.4 AC EIectrical Characteristics
4.5 Timing Issues
LIST OF FIGURES
Connection Diagram
CGS410 Block Diagram
Figure 3-1 Linear Operating Range
Figure 3-2 Phase Comparator Charge/Pump
Figure 3-3 Control Register Read Operations
Figure 3-4 Control Register Write Operations
Figure 3-5 Control Register Architecture
Figure 3-6 Bode Plot of Loop Filter Response
Figure 3-7 External Low Pass Filter
Figure 3-8 Termination
Figure 3-9 Pull-up/Pull-down DC Termination
Figure 3-10 Typical Termination (Bit 1
e
0)
Figure 3-11 PCLK/PCLKB Load vs. Frequency
Figure 3-12 Serial Interface Example
Figure 3-13 Minimum Cost,
k
80 MHz CGS410
Implementation
Figure 3-14 Common Video Application
Figure 3-15 Primary Loop GENLOCK Configuration
Figure 3-16 Crystal Configuration
Figure 3-17 CGS410 Using an External Loop Filter and
VCO
Figure 3-18 External XTLIN Drive Options
Figure 4-1 System Read Timing Specification
Figure 4-2 System Write Timing Specification
Figure 4-3 LCLKÐEN Timing Specification
Figure 4-4 CMOS PCLK Output Skew Timing Specification
Figure 4-5 DIFF PCLK Output Skew Timing Specification
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1.0 Functional Description
The CMOS clock outputs are generated by a phase lock loop (PLL). The internal voltage controlled oscillator (VCO) derives a reference frequency from the crystal input (XTLIN) and produces a synthesized output. A programmable 1 to 16 divider and a passthru mux are positioned between the VCO and clock outputs, allowing a wide range of output frequencies without having to band switch the VCO. A load clock (LCLK) is also available. A synchronous LCLK control simplifies system frame buffer design.
With the CGS410 programmed to run in internal LPF mode, no external low pass filter components are required. There are three internal filters. If an external loop filter is desired, or if precise LPF parameters are required, the CGS410 can be programmed to use the external filter pin. The external filter requires two capacitors and one resistor. No external devices such as inductors or varactors are necessary. Fre­quency configuration is programmed through the internal N, R, P, and L dividers and the 3-to-1 MUX.
CGS410 Block Diagram
TL/F/11919– 2
2.0 Pin Definitions
Symbol Pin I/O Function
AGND 13 S Analog Ground. This pin serves as the return for the analog circuitry. AGND should also serve as
the external filter return reference as sourced by FILTER. AGND should be well referenced to DGND.
AVDD 14 S Analog VDD. This pin sources the internal VCO, internal loop filter, and charge pump. Due to the
sensitive nature of this pin, special care should be taken to filter out noise for best performance. AVDD should track DVDD to within
g
5%.
BGND 21 S Buffer Ground. Output buffer supply return. This serves as the return for the CMOSÐPCLK and
LCLK outputs. Best output performance is obtained when the CMOSÐPCLK and LCLK reception devices are referenced to BGND.
BVDD 20 S Buffer VDD. This positive power supply input sources LCLK, CMOSÐPCLK and the differential
PCLK output pair. Care must be taken to properly bypass this input with BGND.
CMOSÐPCLK 22 O CMOS PCLK Output. This single-ended output is typically used to drive devices which require
CMOS input characteristics.
CSB 25 I Clock for Serial Data Input and Output. This input is TTL compatible edge sensitive. In the serial
read or write operation, the falling edge latches the RÐWB and EN states. The rising edge completes the shift and transfer operation.
DATA 26 I/O Data Input/Output. This is a bi-directional I/O pin used to transfer data in and out of the CGS410
in a serial fashion. Data must be valid when each bit is clocked on the rising edge of the CSB input. DATA is TTL compatible for input mode; CMOS compatible for output mode.
DGND 3 S Digital Ground. This pin serves as the return path for the internal CGS410 counter circuitry. This
input should be well referenced to BGND.
3
2.0 Pin Definitions (Continued)
Symbol Pin I/O Function
DIFFÐVOH 15 O Differential High Voltage Load. This output is connected to a load network which is ten times the
value of the load network connected to the differential PCLK pins.
DIFFÐVOL 16 O Differentlal Low Voltage Load. This output is connected to a load network which is ten times the
value of the load network connected to the differential PCLK pins.
DVDD 4 S Digital VDD. This pin serves as the source for the internal CGS410 counter circuitry. This input
should be well referenced to BVDD and bypassed to DGND.
EN 28 I An Active-High, Level-Sensltlve TTL Compatible Input. This input is sampled on the falling edge
of CSB, EN high allows data to be transferred to the shadow register in the write mode or to the shift register in the read mode.
EXTCLK 2 I External Clock. When the internal multiplexer is set to EXTCLK mode, the crystal and phase-locked
loop are bypassed, and this TTL compatible input will drive the PCLK outputs and the L divider input. If the external VCO mode is invoked, EXTCLK drives the P and N dividers. When this input is not selected, it should be driven to a high or low to avoid oscillations.
FILTER 12 O Filter Output. This current source output is driven from the internal charge pump. This output is left
floating in applications where only the internal low pass filters are used. FILTER is used for applications which require passive or active external LPF networks. For passive LPF networks, this output should be connected directly to FREQCTL input and the LPF network (see
Figure 3-7
).
FREQCTL 11 I Frequency Control. FREQCTL is the VCO voltage control input. When in external loop filter mode,
the voltage present on this input determines the VCO frequency. For applications which require only the internal filters, this input is left unconnected. This input is used for applications which require external networks for loop filtering. The input voltage range should not exceed AVDD, and not go below the AGND reference.
LCLK 23 O Load Clock Output. This CMOS compatible, non-gated output is typically used in video applications
which require a programmable clock to produce lower output frequencies synchronous to PCLK. Typically, this is used to clock video shift registers or RAMDACs.
LCLKÐEN 24 I Load Clock Enable. This synchronous active high TTL compatible input selects whether the LCLK
output is disabled or enabled. A HIGH level enables the LCLK output pin, while a LOW disables activity on the LCLK. In the disabled state LCLK is driven high or low depending on the logic state of the L counter when disabled. Refer to the LCLKÐEN timing specification.
PCLK 18 O DifferentIal PCLK Output. This high speed output is configured to drive a host of devices requiring
differential clock inputs. Output voltage swing is defined by the differential level control bit (Bit 1).
PCLKB 19 O Differential PCLK Output. This high speed output is configured to drive a host of devices requiring
differential clock inputs. Output voltage swing is defined by the differential level control bit (Bit 1).
RÐWB 27 I Read/Write Select. RÐWB is a level sensitive TTL compatible input. When writing values to the
chip, the RÐWB would be sampled low on the falling edge of CSB. Conversely, when reading values, the RÐWB would be sampled high on the falling edge of CSB.
XGND 8 S Crystal Ground. This pin serves as the ground return for the internal oscillator circuitry. All external
oscillator support, be it active or passive, should be tied to XGND for best performance.
XTLIN 6 I Crystal Input. XTLIN is designed to operate with crystal, oscillator or ceramic resonator input. For
crystal input applications, the crystal should be the fundamental parallel mode type. See the applications diagrams for more information.
XTLOUT 7 O Crystal Output. This output is used as the Pierce Oscillator output for use with parallel mode
crystals. An external resistor between XTLOUT and XTLIN will bias this stage to approximately XVDD/2. This output is left floating for applications which directly drive the XTLIN.
XVDD 9 S Crystal VDD. This positive power supply input sources the internal oscillator circuitry. All external
oscillator support, be it active or passive, should be referenced to XVDD for best performance. This supply input must track DVDD to within 5%.
4
3.0 Circuit Operation
The CGS410 programmable clock generator uses a crystal oscillator as a frequency reference to generate clock sig­nals for video applications such as display systems or disk drive constant density recording. The reference may come from any source as long as input specifications are main­tained. Both single-ended (CMOS) and differential clock outputs are generated. Both clock outputs are synchronized to simplify system timing. A unique combination of internal functions (such as the VCO, the crystal oscillator, a phase comparator, various programmable counters, and a read­able 47-bit serial control register) allows for versatility and ease of design.
3.1 INTERNAL VCO OPERATION
No external VCO inductor or capacitor components are re­quired for operation, simplifying PC board layout require­ments. P counter programmability is contiguous from 1 to 16, although a 50% duty cycle will be created only if the P modulus is an even number, or if the P modulus is 1.
3.1.1 VCO Tuning Characteristics
The CGS410 VCO requires an input voltage to set the prop­er operating frequency. The input voltage is the direct result of charge sourced or sinked off the LPF network. The func­tion of the LPF is to convert the charge to voltage (see ‘‘Loop Filter Characteristics’’). The VCO requires the input voltage to be set in the linear portion of the input range. The VCO output frequency is a function of the VCO gain (F
VCO
)
and the range of the input voltage.
Normal, or linear VCO operation will place the input voltage range from AVDD/3 (the lowest frequency response) to ap­proximately AVDD
b
1.5V (the highest frequency re-
sponse). The linear operating range is illustrated in
Figure
3-1
with VCO output frequency (F
VCO
) expressed as a volt-
age filter input (V
FILTER
).
TL/F/11919– 3
FIGURE 3-1. Linear Operating Range
Applying an input voltage beyond the intended range will force the VCO to rail high or low. Input voltages which ex­ceed AVDD, or go negative with respect to AGND, can dam­age the CGS410.
3.2 CRYSTAL OSCILLATOR OPERATION
The XTLIN and XTLOUT pins are used in conjunction with an external crystal, two capacitors, and two resistors to form an external oscillator tank circuit. The crystal should be a fundamental parallel mode type. XTLOUT serves as the driving source to the crystal. Consideration should be given to avoiding crystal overdrive situations. XTLOUT should
show an output waveform well within the XVDD and XGND boundary conditions. The elements forming the crystal tank should be low-leakage devices. Capacitor values (per crys­tal leg) will typically fall within the range of 10 pF –40 pF.
The crystal oscillator divide-by-2 output may be directed to appear at the clock outputs depending on the state of the 3 to 1 MUX. On power up, both differential and CMOSÐPCLK outputs will reflect half the oscillator frequency input. The XTLIN pin can be driven from a variety of sources, including ECL, TTL, or CMOS logic. Attach a coupling capacitor into the XTLIN pin when using a TTL or small-signal source (such as ECL). Please see application diagrams for details. The CGS410 may be used to genlock to an external clock source.
3.3 PHASE COMPARATOR OPERATION
The phase comparator compares the difference in clock edges between the internal N and R counter outputs. The difference results as either a charge source (pump-up), or charge sink (pump-down). The amount of charge is directly proportional to the phase difference (see
Figure 3-2
). The phase comparator controls the VCO by comparing the phase of a derived signal from a known accurate reference source such as a crystal or an external reference signal. In genlocking situations, the reference source may be a con­stant stream of pulses such as an external HSYNC.
TL/F/11919– 4
FIGURE 3-2. Phase Comparator/Charge Pump
The VCO-derived signal is divided by N, and applied to one phase comparator input. The R divider output serves as the other phase comparator reference input. The comparator functions as a three-state machine: providing a pump-up state when R leads N, and a pump-down state when N leads R. This situation exists only when there is a difference between the two input edges. The VCO frequency is then increased or decreased in the closed loop system. At all other times, the phase comparator is in a tri-state condition.
The direction and amount of charge on the FILTER pin is proportional to the difference in the phase comparator input edges. The charge flow is made up of correction pulses. The resulting correction pulses are converted to a voltage as dictated by the LPF network. Selection of LPF compo­nents characterizes the resulting voltage and phase re­sponse.
5
3.0 Circuit Operation (Continued)
The CGS410 allows the user to select the quantity of charge pump current and its direction. Specifying the direction of charge flow is useful in situations where an external filter and/or VCO is incorporated. See the applications section for an example. In situations where external networks lack the charge sensitivity, the amount of charge can be in­creased at the user’s discretion.
3.4 PROGRAMMABLE DIVIDER OPERATION
The CGS410 has four internal dividers (R, N, P, and L) which are programmed serially via the internal control regis­ter.
The R (reference) divider provides a reference frequency from either a crystal or an externally generated clock source. The divisor range is contiguous and varies from 1 to
The internal N divider provides a means of locking the VCO with a constant tuning resolution that is independent of the pixel system. Its contiguous modulus range is 2 to 16383.
The P (postscaling) divider provides a means of generating an output over a wide frequency range from a VCO which has a flxed frequency range. The modulus selections of the P divider range from 1 –16 inclusive. The modulus of this divider is programmed with serial control register bits 16–19. The PCLK outputs are square when the P modulus is 1, 2, 4, 6, 8, 10, 12, 14, or 16. If the P modulus is 3, 5, 7, 9, 11, 13, or 15, the PCLK outputs are low one less count than it is high. For example, dividing by modulus 5 would result in three counts high and two counts low.
The L (load) divider provides a means of generating a load clock by dividing the PCLK by a modulus ranging from 1 –16 inclusive. The modulus of the load divider is programmed with serial control register bits 20 –23. The L clock output is derived from the output of the internal MUX, so whichever output is selected by the mux will be divided by L. The L clock can be asynchronously disabled/enabled by a serial bit. The LCLK outputs are square when the L modulus is 1, 2, 4, 6, 8, 10, 12, 14, or 16. If the L modulus is 3, 5, 7, 9, 11, 13, or 15, the LCLK is high one less count than it is low. For example, dividing by modulus 5 would result in three counts low and two counts high.
After setting the appropriate values of the registers, the CMOS PCLK output frequency can be calculated using the formula below:
F
OUT
e
F
XTALIN
* N
R * P
3.5 CONTROL REGISTER OPERATION
CGS410 parameters. The shadow register allows the user to write a stream of data to the serial shift register, then, for the last bit do a write followed by a transfer operation. The transferring operation allows all parameters to be loaded into the respective target registers in a single clock cycle. This ensures that changes in clocking parameters take place in a uniform manner.
Read operations are performed in the opposite sequence from that of write. Here, data is transferred from the shadow register to the serial shift register on the first bit, and serially shifted out thereafter.
Performing transfer operations is up to the discretion of the system programmer. In many instances the system may only require partial diagnostic information from the internal registers, and hence avoid a full serial transfer. This is easily accomplished by transferring the data, then shifting only that portion required for the task. The sequence can easily be repeated without adverse affects on the shadow register. Bear in mind that the first data bit written will be the first bit read-out.
3.5.1 System Loading Sequence
All system access to the CGS410 takes place relative to the rising or falling edge of CSB. EN and RÐWB must be stable and in the desired state prior to the falling edge of CSB, while data must be present, or sampled by the system CPU during the rising edge of CSB.
Serial write operations consist of setting both ENable and RÐWB low for the first N-1 bits. Transfer of serial data to the latch register occurs when writing the N
th
(last) bit. On the last bit-write bus cycle, set EN high. The CGS410 will shift in the last bit then perform a transfer to the shadow register. Once the transfer takes place the PLL will immedi­ately begin to lock to the new values.
Serial read operations consist of setting ENable low and RÐWB high for all bits. However, if the programmer wishes to refresh the data in the serial shift register, a transfer oper­ation is performed when reading the first bit. On the first bit read bus cycle, set EN high. The CGS410 will transfer all data in the shadow resister to the shift register then shift out the first valid data bit. Note that the contents of the shadow register are unchanged by the read transfer with no effect on the CGS410 internal parameters or output clocks.
The rest of the serial read operation consists of shifting data bits 2 – 47. Each bit becomes valid at the DATA pin after CSB goes low and then shifts on the positive edge of CSB.
3.5.2 Structure of the Internal Serial Control Register
The following describes the bit structure of the Control Reg­ister. Where applicable, all programmable registers values are loaded with the LSB first.
Serial Bit 1
Differential Level control. This bit sets an internal bias level to provide differential ‘‘large’’ (bit 1 high) or ‘‘small’’ (bit 0 low) signal swing. On power-up this bit is low (small signal swing).
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