NSC ADC1175-50CIMT Datasheet

ADC1175-50
8-Bit, 50 MSPS, 125 mW A/D Converter

ADC1175-50 8-Bit, 50 MSPS, 125 mW A/D Converter

January 2000

General Description

The ADC1175-50 is a low power, 50 MSPS analog-to-digital
converter that digitizes signals to 8 bits while consuming just
125 mW (typ). The ADC1175-50 uses a unique architecture
that achieves 6.8 Effective Bits and 25 MHz input and
50 MHz clock frequency. Output formatting is straight binary
coding.

The excellent DC and AC characteristics of this device, to­gether with itslowpowerconsumptionand +5V single supply
operation, make it ideally suited for many video and imaging
applications, including use in portable equipment. Further­more, the ADC1175-50 is resistant to latch-up and the out­puts are short-circuit proof. The top and bottom of the
ADC1175-50’sreference ladder is available for connections,
enabling a wide range of input possibilities. The low input ca­pacitance (7 pF, typical) makes this device easier to drive
than conventional flash converters and the power down
mode reduces power consumption to less than 5 mW.

The ADC1175-50 is offered in SOIC (EIAJ) and TSSOP. It is
designed to operate over the commercial temperature range
of −20˚C to +75˚C.

Features

n Internal Track-and-Hold function
n Single +5V operation
n Internal reference bias resistors

n Industry standard pinout

<

n Power-down mode (

5 mW)

Key Specifications

n Resolution 8 Bits
n Maximum Sampling Frequency 50 MSPS (min)
n THD 54 dB (typ)
n DNL 0.7 LSB (typ)
n ENOB
n Guaranteed No Missing Codes
n Differential Phase 0.5˚ (typ)
n Differential Gain 1.0%(typ)
n Power Consumption 125 mW (typ), 190 mW (max)

@

fIN= 25 MHz 6.8 Bits (typ)

(Excluding Reference Current)

Applications

n Digital Still Cameras
n CCD Imaging
n Electro-Optics
n Medical Imaging
n Communications
n Video Digitization
n Digital Television
n Multimedia

Connection Diagram

DS100896-1

Ordering Information

ADC1175-50CIJM SOIC (EIAJ)
ADC1175-50CIJMX SOIC (EIAJ) (tape and reel)
ADC1175-50CIMT TSSOP
ADC1175-50CIMTX TSSOP (tape and reel)

TRI-STATE®is a registered trademark of National Semiconductor Corporation.

© 2000 National Semiconductor Corporation DS100896 www.national.com

Block Diagram

ADC1175-50

Pin Descriptions and Equivalent Circuits

DS100896-2

Pin
No.

Symbol Equivalent Circuit Description

19 V

16 V

17 V

23 V

RTS

RT

RB

IN

Analog signal input. Conversion range is VRTto

.

V

RB

Reference Top Bias with internal pull up resistor.
Short this pin to V

to self-bias the reference

RT

ladder.

Analog input that is the high (top) side of the
reference ladder of the ADC. Nominal range is 1.0V
to AV

, optimized value of 2.6V. Voltages on V

DD

RT

and VRBinputs define the VINconversion range.
Bypass well. See Section 2.0 for more information.

Analog input that is the low (bottom) side of the
reference ladder of the ADC. Nominal range is 0.0V
to 4.0V, with optimized value of 0.6V. Voltage on

and VRBinputs define the VINconversion

V

RT

range. Bypass well. See Section 2.0 for more
information.

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Pin Descriptions and Equivalent Circuits (Continued)

ADC1175-50

Pin
No.

22 V

Symbol Equivalent Circuit Description

RBS

1PD

Reference Bottom Bias with internal pull down
resistor. Short to V

to self-bias the reference

RB

ladder. Bypass well if not grounded. See Section

2.0 for more information.

CMOS/TTL compatible Digital input that, when high,
puts the ADC1175-50 into a power-down mode
where total power consumption is typically less than
5 mW. With this pin low, the device is in the normal
operating mode.

12 CLK

3 thru

10

D0–D7

11,

13, 14

2, 24 DV

DV

CMOS/TTL compatible digital clock input. VINis
sampled on the falling edge of CLK input.

Conversion data digital Output pins. D0 is the LSB,
D7 is the MSB. Valid data is output just after the
rising edge of the CLK input. These pins are in a
high impedance mode when the PD pin is low.

Positive digital supply pin. Connect to a clean, quiet
voltage source of +5V. AV

DD

a common source and be separately bypassed with

and DVDDshould have

DD

a 10 µF capacitor and a 0.1 µF ceramic chip
capacitor. See Section 4.0 for more information.

The ground return for the digital supply. AVSSand

should be connected together close to the

SS

DV

SS

ADC1175-50.

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Pin Descriptions and Equivalent Circuits (Continued)

Pin
No.

ADC1175-50

15, 18 AV

20, 21 AV

Symbol Equivalent Circuit Description

Positive analog supply pin. Connect to a clean,
quiet voltage source of +5V. AV

DD

have a common source and be separately bypassed
with a 10 µF capacitor and a 0.1 µF ceramic chip
capacitor. See Section 4.0 for more information.

The ground return for the analog supply. AVSSand

should be connected together close to the

SS

DV

SS

ADC1175-50 package.

and DVDDshould

DD

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ADC1175-50

Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage (AV
Voltage on Any Input or Output Pin −0.3V to +6.5V
Reference Voltage (V
CLK, PD Voltage Range −0.5 to (AVDD+0.5V)
Digital Output Voltage (V
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Power Dissipation at T

,DVDD) 6.5V

DD

)AV

RT,VRB

OH,VOL

)V

DD

DD

±
±

=

25˚C See (Note 4)

A

to V

SS

to V

SS

25 mA
50 mA

ESD Susceptibility (Note 5)

Human Body Model 2000V
Machine Model 250V

Soldering Temperature, Infrared,

(10 sec.) (Note 6) 300˚C
Storage Temperature −65˚C to +150˚C
Short Circuit Duration

(Single High Output to Ground) 1 Second

Operating Ratings (Notes 1, 2)

Operating Temperature Range −20˚C ≤ T
Supply Voltage (AV

−DV

AV

DD

DD

Ground Difference |DV
Upper Reference Voltage (V

,DVDD) +4.75V to +5.25V

DD

–AVSS| 0V to 100 mV

SS

) 1.0V to V

RT

≤ +75˚C

A

Lower Reference Voltage (VRB) 0V to 4.0V

Voltage Range VRBto V

V

IN

Converter Electrical Characteristics

The following specifications apply for AV
50 MHz at 50%duty cycle. Boldface limits apply for T

=

DD

Symbol Parameter Conditions

DC ACCURACY

INL Integral Non Linearity Error V
DNL Differential Non-Linearity

Resolution for No Missing
Codes

E

OT

E

OB

Top Offset Voltage −12 mV
Bottom Offset Voltage +10 mV

VIDEO ACCURACY

DP Differential Phase Error f
DG Differential Gain Error f

ANALOG INPUT AND REFERENCE CHARACTERISTICS

V

IN

C

IN

R

IN

Input Range 2.0

VINInput Capacitance

RINInput Resistance
BW Full Power Bandwidth 120 MHz
R

R
R

I

V

V

RT

REF

RB

REF

RT

RB

Top Reference Resistor 320 Ω

Reference Ladder Resistance VRTto V

Bottom Reference Resistor 80 Ω

Reference Ladder Current

Reference Top Self Bias

Voltage

Reference Bottom Self Bias

Voltage

=

DV

V

+5.0 V

DD

=

0.6V to 2.6V

IN

=

0.6V to 2.6V +0.7 +1.75 LSB (max)

IN

=

A

,PD=0V, V

DC

to T

T

MIN

MAX

=

+2.6V, V

RT

; all other limits T

Typical

(Note 9)

=

0.6V, C

RB

=

25˚C (Notes 7, 8).

A

(Note 9)

±

0.8

=

20 pF, f

L

Limits

±

1.95 LSB (max)

−0.7 −1.0 LSB (min)
8 Bits

= 4.43 MHz Modulated Ramp 0.5 deg

IN

= 4.43 MHz Modulated Ramp 1.0

IN

V

RB

V

RT

V

= 1.5V

IN

+0.7 Vrms

RB

V

RT=VRTS,VRB=VRBS

V

RT=VRTS,VRB

VRTConnected to V
Connected to V

RBS

VRTConnected to V
Connected to V

RBS

(CLK LOW) 4 pF
(CLK HIGH) 7 pF

>

1MΩ

200
350

5.4 mA (min)

10.8 mA (max)

6.1 mA (min)

12.3 mA (max)

0.55

0.70

=AV

RTS,VRB

RTS,VRB

270

7

SS

8

2.6

0.6

CLK

Units

(Limits)

V (min)

V (max)

Ω (min)

Ω (max)

V (min)

V (max)

V (min)

V (max)

=

%

<

0.5V

DD

RT

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Converter Electrical Characteristics (Continued)

The following specifications apply for AV
50 MHz at 50%duty cycle. Boldface limits apply for T

ADC1175-50

Symbol Parameter Conditions

=

DD

ANALOG INPUT AND REFERENCE CHARACTERISTICS

V

RTS–VRBS

V

RT–VRB

Self Bias Voltage Delta

Reference Voltage Differential 2

CONVERTER DYNAMIC CHARACTERISTICS

ENOB Effective Number of Bits

SINAD Signal-to-Noise & Distortion

SNR Signal-to-Noise Ratio

SFDR Spurious Free Dynamic Range

THD Total Harmonic Distortion

POWER SUPPLY CHARACTERISTICS

IA
ID

IA
ID

DD
DD

DD
DD

Analog Supply Current DVDD=AVDD= 5.25V 13 mA
Digital Supply Current DVDD=AVDD= 5.25V 11 mA

+

Total Operating Current

Power Consumption PD pin low 125 190 mW (max)
Power Consumption PD pin high

CLK, PD DIGITAL INPUT CHARACTERISTICS

V

IH

V

IL

I

IH

I

IL

C

IN

Logical High Input Voltage 2.0 V (min)
Logical Low Input Voltage 0.8 V (max)
Logical High Input Current V
Logical Low Input Current V
Digital Input Capacitance 4 pF

DIGITAL OUTPUT CHARACTERISTICS

I

OH

I

OL

Output Current, Logic HIGH DVDD= 4.75V, VOH= 4.0V −1.1 mA (min)
Output Current, Logic LOW DVDD= 4.75V, VOL= 0.4V 1.8 mA (min)

=

DV

V

+5.0 V

DD

A

Connected to V

RT

=

Connected to V
V

Connected to V

RT

Connected to V

=

f

4.4 MHz, f

IN

=

f

19.9 MHz, f

IN

=

f

1.3 MHz, f

IN

=

f

4.4 MHz, f

IN

=

f

24.9 MHz, f

IN

=

f

4.4 MHz, f

IN

=

f

19.9 MHz, f

IN

=

f

1.3 MHz, f

IN

=

f

4.4 MHz, f

IN

=

f

24.9 MHz, f

IN

=

f

4.4 MHz, f

IN

=

f

19.9 MHz, f

IN

=

f

1.3 MHz, f

IN

=

f

4.4 MHz, f

IN

=

f

24.9 MHz, f

IN

=

1.3 MHz 57 dB

f

IN

=

f

4.4 MHz 56 dB

IN

=

f

24.9 MHz 51 dB

IN

=

1.3 MHz −55 dB

f

IN

=

f

4.4 MHz −54 dB

IN

=

f

24.9 MHz −51 dB

IN

=AVDD= 5.25V,

DV

DD

=50MHz

f

CLK

DV

=AVDD= 5.25V,

DD

CLK Inactive (low)

=

IH

=

IL

DV

DD

0V, DV

=

DD

,PD=0V, V

DC

to T

T

MIN

RTS,VRB

RBS

RTS,VRB

RBS

=

RT

; all other limits T

MAX

+2.6V, V

=

0.6V, C

RB

=

25˚C (Notes 7, 8).

A

Typical

(Note 9)

2

=

20 pF, f

L

Limits

(Note 9)

1.89

2.20

2.3 V

1.0

2.8

=

40 MHz 7.2 6.7 Bits (min)

CLK

=

40 MHz 7.0 6.4 Bits (min)

CLK

=

50 MHz 7.3 Bits

CLK

=

50 MHz 7.2 Bits

CLK

=

50 MHz 6.8 6.1 Bits (min)

CLK

=

40 MHz 45 42 dB (min)

CLK

=

40 MHz 44 40 dB (min)

CLK

=

50 MHz 46 dB

CLK

=

50 MHz 45 dB

CLK

=

50 MHz 43 38.4 dB (min)

CLK

=

40 MHz 46 42.5 dB (min)

CLK

=

40 MHz 44 41 dB (min)

CLK

=

50 MHz 48 dB

CLK

=

50 MHz 45 dB

CLK

=

50 MHz 44 40 dB (min)

CLK

25 36 mA (max)

14 mA

<

5mW mW

AV

=

+5.25V

DD

=

AV

=

+5.25V

DD

±

5 µA (max)

±

5 µA (max)

CLK

Units

(Limits)

(V (min)
V (max)

V (min)

V (max)

=

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