NSC ADC08D1000QML Datasheet

May 2007

ADC08D1000QML
High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D
Converter

General Description

The ADC08D1000 is a dual, low power, high performance
CMOS analog-to-digital converter that digitizes signals to 8
bits resolution at sampling rates up to 1.2 GSPS. Consuming
a typical 1.6 Watts at 1 GSPS from a single 1.9 Volt supply,
this device is guaranteed to have no missing codes over the
full operating temperature range. The unique folding and in­terpolating architecture, the fully differential comparator de­sign, the innovative design of the internal sample-and-hold
amplifier and the self-calibration scheme enable a very flat
response of all dynamic parameters beyond Nyquist, produc­ing a high 7.4 Effective Number Of Bits (ENOB) with a 498
MHz input signal and a 1 GHz sample rate while providing a
10

-18

Bit Error Rate ( B.E.R.). Output formatting is offset binary
and the Low Voltage Differential Signaling (LVDS) digital out­puts are compliant with IEEE 1596.3-1996, with the exception
of an adjustable common mode voltage between 0.8V and

1.13V.
Each converter has a 1:2 demultiplexer that feeds two LVDS

buses and reduces the output data rate on each bus to half
the sampling rate. The two converters can be interleaved and
used as a single 2 GSPS ADC.

The converter typically consumes less than 3.5 mW in the
Power Down Mode and is available in a 128-lead, thermally
enhanced multi-layer ceramic quad package and operates
over the Military (-55°C ≤ TA ≤ +125°C) temperature range.

This part will work in a radiation environment, with ex­cellent results, provided the guidelines in applications
section 2.1 are followed.

Features

■

Available with radiation guarantee

■

Internal Sample-and-Hold

■

Single +1.9V ±0.1V Operation

■

Choice of SDR or DDR output clocking

■

Interleave Mode for 2x Sampling Rate

■

Multiple ADC Synchronization Capability

■

Guaranteed No Missing Codes

■

Serial Interface for Extended Control

■

Fine Adjustment of Input Full-Scale Range and Offset

■

Duty Cycle Corrected Sample Clock

Key Specifications

■ Resolution

8 Bits

■ Max Conversion Rate

1 GSPS (min)

■ Bit Error Rate

10

-18

(typ)

■ ENOB @ 498 MHz Input

7.4 Bits (typ)

■ DNL

±0.15 LSB (typ)

■ Power Consumption

  — Operating

1.6 W (typ)

  — Power Down Mode

3.5 mW (typ)

■ Total Ionizing Dose

300 krad(Si)

■ Single Event Latch Up

>120 MeV/mg/cm

2

Applications

■

Communication Satellites/Systems

■

Direct RF Down Conversion

© 2007 National Semiconductor Corporation 201802 www.national.com

ADC08D1000QML High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D Converter

Block Diagram

20180253

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ADC08D1000QML

Ordering Information

NS PART NUMBER SMD PART NUMBER NS PACKAGE NUMBER PACKAGE DISCRIPTION

ADC08D1000WG-Q 5962–0520601QZC EM128A 128L, CERQUAD GULLWING

ADC08D1000WG-QV 5962–0520601VZC EM128A 128L, CERQUAD GULLWING

ADC08D1000WGFQV 5962F0520601VZC

300 krad(Si)

EM128A 128L, CERQUAD GULLWING

Pin Configuration

20180201

* Bottom of package must be soldered to ground plane to ensure rated performance.

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ADC08D1000QML

Pin Descriptions and Equivalent Circuits

Pin Functions

Pin No. Symbol Equivalent Circuit Description

3 OutV / SCLK

Output Voltage Amplitude and Serial Interface Clock. Tie this pin
high for normal differential DCLK and data amplitude. Ground this
pin for a reduced differential output amplitude and reduced power
consumption. See Section 1.1.6. When the extended control mode
is enabled, this pin functions as the SCLK input which clocks in the
serial data.See Section 1.2 for details on the extended control
mode. See Section 1.3 for description of the serial interface.

4

OutEdge / DDR /

SDATA

DCLK Edge Select, Double Data Rate Enable and Serial Data
Input. This input sets the output edge of DCLK+ at which the output
data transitions. (See Section 1.1.5.2). When this pin is floating or
connected to 1/2 the supply voltage, DDR clocking is enabled.
When the extended control mode is enabled, this pin functions as
the SDATA input. See Section 1.2 for details on the extended
control mode. See Section 1.3 for description of the serial
interface.

15 DCLK_RST

DCLK Reset. A positive pulse on this pin is used to reset and
synchronize the DCLK outs of multiple converters. See Section 1.5
for detailed description.

26
29

PD

PDQ

Power Down Pins. A logic high on the PD pin puts the entire device
into the Power Down Mode. A logic high on the PDQ pin puts only
the "Q" ADC into the Power Down mode.

30 CAL

Calibration Cycle Initiate. A minimum 640 input clock cycles logic
low followed by a minimum of 640 input clock cycles high on this
pin initiates the self calibration sequence. See Section 2.5.2 for an
overview of self-calibration and Section 2.5.2.2 for a description of
on-command calibration. See Section 2.1 for use in Radiation

Environments.

14 FSR/ECE

Full Scale Range Select and Extended Control Enable. In non­extended control mode, a logic low on this pin sets the full-scale
differential input range to 650 mV

P-P

. A logic high on this pin sets

the full-scale differential input range to 870 mV

P-P

. See Section

1.1.4. To enable the extended control mode, whereby the serial
interface and control registers are employed, allow this pin to float
or connect it to a voltage equal to VA/2. See Section 1.2 for
information on the extended control mode. See Section 2.1 for

use in Radiation Environments.

127

CalDly / DES /

SCS

Calibration Delay, Dual Edge Sampling and Serial Interface Chip
Select. With a logic high or low on pin 14, this pin functions as
Calibration Delay and sets the number of input clock cycles after
power up before calibration begins (See Section 1.1.1). With pin
14 floating, this pin acts as the enable pin for the serial interface
input and the CalDly value becomes "0" (short delay with no
provision for a long power-up calibration delay). When this pin is
floating or connected to a voltage equal to VA/2, DES (Dual Edge
Sampling) mode is selected where the "I" input is sampled at twice
the input clock rate and the "Q" input is ignored. See Section

1.1.5.1. See Section 2.1 for use in Radiation Environments.

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ADC08D1000QML

Pin Functions

Pin No. Symbol Equivalent Circuit Description

18
19

CLK+

CLK-

LVDS Clock input pins for the ADC. The differential clock signal
must be a.c. coupled to these pins. The input signal is sampled on
the falling edge of CLK+. See Section 1.1.2 for a description of
acquiring the input and Section 2.4 for an overview of the clock
inputs.

11
10

.
22
23

VINI+
VINI−

.
VINQ+
VINQ−

Analog signal inputs to the ADC. The differential full-scale input
range is 650 mV

P-P

when the FSR pin is low, or 870 mV

P-P

when

the FSR pin is high.

7

V

CMO

Common Mode Voltage. The voltage output at this pin is required
to be the common mode input voltage at VIN+ and VIN− when d.c.
coupling is used. This pin should be grounded when a.c. coupling
is used at the analog inputs. This pin is capable of sourcing or
sinking 100μA. See Section 2.3.

31

V

BG

Bandgap output voltage capable of 100 μA source/sink.

126 CalRun

Calibration Running indication. This pin is at a logic high when
calibration is running.

32

R

EXT

External bias resistor connection. Nominal value is 3.3k-Ohms
(±0.1%) to ground. See Section 1.1.1.

34
35

Tdiode_P
Tdiode_N

Temperature Diode Positive (Anode) and Negative (Cathode) for
die temperature measurements. See Section 2.7.2.

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ADC08D1000QML

Pin Functions

Pin No. Symbol Equivalent Circuit Description

83 / 78
84 / 77
85 / 76
86 / 75
89 / 72
90 / 71
91 / 70
92 / 69
93 / 68
94 / 67
95 / 66

96 / 65
100 / 61
101 / 60
102 / 59
103 / 58

DI7− / DQ7−
DI7+ / DQ7+
DI6− / DQ6−
DI6+ / DQ6+
DI5− / DQ5−
DI5+ / DQ5+
DI4− / DQ4−
DI4+ / DQ4+
DI3− / DQ3−
DI3+ / DQ3+
DI2− / DQ2−
DI2+ / DQ2+
DI1− / DQ1−
DI1+ / DQ1+
DI0− / DQ0−
DI0+ / DQ0+

I and Q channel LVDS Data Outputs that are not delayed in the
output demultiplexer. Compared with the DId and DQd outputs,
these outputs represent the later time samples. These outputs
should always be terminated with a 100Ω differential resistor.

104 / 57
105 / 56
106 / 55
107 / 54
111 / 50
112 / 49
113 / 48
114 / 47
115 / 46
116 / 45
117 / 44
118 / 43
122 / 39
123 / 38
124 / 37
125 / 36

DId7− / DQd7−
DId7+ / DQd7+
DId6− / DQd6−
DId6+ / DQd6+
DId5− / DQd5−
DId5+ / DQd5+
DId4− / DQd4−
DId4+ / DQd4+
DId3− / DQd3−
DId3+ / DQd3+
DId2− / DQd2−
DId2+ / DQd2+
DId1− / DQd1−
DId1+ / DQd1+
DId0− / DQd0−
DId0+ / DQd0+

I and Q channel LVDS Data Outputs that are delayed by one CLK
cycle in the output demultiplexer. Compared with the DI/DQ
outputs, these outputs represent the earlier time sample. These
outputs should always be terminated with a 100Ω differential
resistor.

79
80

OR+

OR-

Out Of Range output. A differential high at these pins indicates that
the differential input is out of range (outside the range ±325 mV or
±435 mV as defined by the FSR pin).

82
81

DCLK+

DCLK-

Differential Clock outputs used to latch the output data. Delayed
and non-delayed data outputs are supplied synchronous to this
signal. This signal is at 1/2 the input clock rate in SDR mode and
at 1/4 the input clock rate in the DDR mode. DCLK outputs are not
active during a calibration cycle.

2, 5, 8, 13,
16, 17, 20,
25, 28, 33,

128

V

A

Analog power supply pins. Bypass these pins to ground.

40, 51 ,62,
73, 88, 99,

110, 121

V

DR

Output Driver power supply pins. Bypass these pins to DR GND.

1, 6, 9, 12,
21, 24, 27,

41

GND

Ground return for VA.

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ADC08D1000QML

Pin Functions

Pin No. Symbol Equivalent Circuit Description

42, 53, 64,
74, 87, 97,

108, 119

DR GND

Ground return for VDR.

52, 63, 98,

109, 120

NC No Connection. Make no connection to these pins.

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ADC08D1000QML

Absolute Maximum Ratings

(Notes 1, 2)

Supply Voltage (VA, VDR)

2.2V
Voltage on Any Input Pin −0.15V to (VA +0.15V)

Ground Difference
|GND - DR GND| 0V to 100 mV

Input Current at Any Pin (Note 3) ±25 mA
Package Input Current (Note 3) ±50 mA
ESD Susceptibility (Note 4)

Human Body Model

Class 3A (6000V)

Soldering Temperature, Infrared,
10 seconds 235°C

Storage Temperature −65°C to +175°C

Operating Ratings (Notes 1, 2)

Ambient Temperature Range

−55°C ≤ TA ≤ +125°C

Supply Voltage (VA)

+1.8V to +2.0V

Driver Supply Voltage (VDR) +1.8V to V

A

Analog Input Common Mode Voltage V

CMO

±50mV

VIN+, VIN- Voltage Range
(Maintaining Common Mode)

200mV to V

A

Ground Difference
(|GND - DR GND|) 0V

CLK Pins Voltage Range 0V to V

A

Differential CLK Amplitude 0.4V

P-P

to 2.0V

P-P

Maximum Junction Temperature 150°C

Package Thermal Resistance

Package

θ

JA

θ

JC (Top of

Package)

θ

J-PAD

(Thermal Pad)

128L Cer Quad

Gullwing

11.5°C/W 3.8°C/W 2.0°C/W

Quality Conformance Inspection

MIL-STD-883, Method 5005 - Group A

Subgroup Description Temp (°C)

1 Static tests at +25

2 Static tests at +125

3 Static tests at -55

4 Dynamic tests at +25

5 Dynamic tests at +125

6 Dynamic tests at -55

7 Functional tests at +25

8A Functional tests at +125

8B Functional tests at -55

9 Switching tests at +25

10 Switching tests at +125

11 Switching tests at -55

12 Setting time at +25

13 Setting time at +125

14 Setting time at -55

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ADC08D1000QML

ADC08D1000 Converter Electrical Characteristics

DC Parameters

The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential
870mV

P-P

, CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, f

CLK

= 1 GHz at 0.5V

P-P

with 50% duty cycle, VBG = Floating,

Non-Extended Control Mode, SDR Mode, R

EXT

= 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω Differential. Boldface

limits apply for TA = T

MIN

to T

MAX

(Notes 5, 6)

Symbol Parameter Conditions Notes

Typical

(Note 7)

Min Max Units

Sub-

groups

STATIC CONVERTER CHARACTERISTICS

INL

Integral Non-Linearity
(Best fit)

DC Coupled, 1MHz Sine Wave
Overanged

±0.3 ±0.9 LSB 1, 2, 3

DNL Differential Non-Linearity

DC Coupled, 1MHz Sine Wave
Overanged

±0.15 ±0.6 LSB 1, 2, 3

Resolution with No Missing
Codes

8 Bits 1, 2, 3

V

OFF

Offset Error -0.45 −1.5 0.5 LSB 1, 2, 3

PFSE Positive Full-Scale Error

(Note

8)

−0.6 ±27 mV 1, 2, 3

NFSE Negative Full-Scale Error

(Note

8)

−1.31 ±27 mV 1, 2, 3

Out of Range Output Code
(In addition to OR Output
high)

(VIN+) − (VIN−) > + Full Scale

255 1, 2, 3

(VIN+) − (VIN−) < − Full Scale

0 1, 2, 3

ANALOG INPUT AND REFERENCE CHARACTERISTICS

V

IN

Full Scale Analog
Differential Input Range

FSR pin 14 High 870 790 950

mV

P-P

1, 2, 3

R

IN

Differential Input
Resistance

100 94 106

Ω

1, 2, 3

ANALOG OUTPUT CHARACTERISTICS

V

CMO

Common Mode Output
Voltage

1.26 0.95 1.45 V 1, 2, 3

V

BG

Bandgap Reference
Output Voltage

IBG = ±100 µA

1.26 1.20 1.33 V 1, 2, 3

CLOCK INPUT CHARACTERISTICS

V

ID

Differential Clock Input
Level

Sine Wave Clock 0.6 0.5 2.0

V

P-P

1, 2, 3

Square Wave Clock 0.6 0.5 2.0

V

P-P

1, 2, 3

DIGITAL CONTROL PIN CHARACTERISTICS

V

IH

Logic High Input Voltage

.85xV

A

V 1, 2, 3

V

IL

Logic Low Input Voltage

.15xV

A

V 1, 2, 3

DIGITAL OUTPUT CHARACTERISTICS

V

OD

LVDS Differential Output
Voltage

Measured differentially,
OutV = VA, VBG = Floating

(Note

14)

710 400 920

mV

P-P

1, 2, 3

Measured differentially,
OutV = GND, VBG = Floating

(Note

14)

510 280 720

mV

P-P

1, 2, 3

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ADC08D1000QML

Symbol Parameter Conditions Notes

Typical

(Note 7)

Min Max Units

Sub-

groups

POWER SUPPLY CHARACTERISTICS

I

A

Analog Supply Current

PD = PDQ = Low
PD = Low, PDQ = High
PD = PDQ = High

660

430

1.8

765

508

mA
mA
mA

1, 2, 3
1, 2, 3

I

DR

Output Driver Supply
Current

PD = PDQ = Low
PD = Low, PDQ = High
PD = PDQ = High

200

112

0.012

275

157

mA
mA
mA

1, 2, 3
1, 2, 3

P

D

Power Consumption

PD = PDQ = Low
PD = Low, PDQ = High
PD = PDQ = High

1.6

1.0

3.5

1.97

1.27

W
W

mW

1, 2, 3
1, 2, 3

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ADC08D1000QML

AC Parameters

The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential
870mV

P-P

, CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, f

CLK

= 1 GHz at 0.5V

P-P

with 50% duty cycle, VBG = Floating,

Non-Extended Control Mode, SDR Mode, R

EXT

= 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω Differential. Boldface

limits apply for TA = T

MIN

to T

MAX

(Notes 5, 6)

Symbol Parameters Conditions Notes

Typical

(Note 7)

Min Max Units

Sub -

groups

NORMAL MODE (Non DES) DYNAMIC CONVERTER CHARACTERISTICS

ENOB Effective Number of Bits

fIN = 100 MHz, VIN = FSR − 0.5 dB

7.5 Bits

fIN = 248 MHz, VIN = FSR − 0.5 dB

7.4 7.0 Bits 4, 5, 6

fIN = 498 MHz, VIN = FSR − 0.5 dB

7.4 7.0 Bits 4, 5, 6

SINAD

Signal-to-Noise Plus
Distortion Ratio

fIN = 100 MHz, VIN = FSR − 0.5 dB

47 dB

fIN = 248 MHz, VIN = FSR − 0.5 dB

46.3 43.9 dB 4, 5, 6

fIN = 498 MHz, VIN = FSR − 0.5 dB

46.3 43.9 dB 4, 5, 6

SNR Signal-to-Noise Ratio

fIN = 100 MHz, VIN = FSR − 0.5 dB

48 dB

fIN = 248 MHz, VIN = FSR − 0.5 dB

47.1 44 dB 4, 5, 6

fIN = 498 MHz, VIN = FSR − 0.5 dB

47.1 44 dB 4, 5, 6

THD Total Harmonic Distortion

fIN = 100 MHz, VIN = FSR − 0.5 dB

-55 dB

fIN = 248 MHz, VIN = FSR − 0.5 dB

-55 −47.5 dB 4, 5, 6

fIN = 498 MHz, VIN = FSR − 0.5 dB

-55 −47.5 dB 4, 5, 6

SFDR

Spurious Free Dynamic
Range

fIN = 248 MHz, VIN = FSR − 0.5 dB

57 dB

fIN = 498 MHz, VIN = FSR − 0.5 dB

57 47 dB 4, 5, 6

f

CLK1

Maximum Input Clock
Frequency

Normal Mode (non DES)

1.2 1.0 GHz 4, 5, 6

INTERLEAVE MODE (DES Pin 127=Float) - DYNAMIC CONVERTER CHARACTERISTICS

ENOB Effective Number of Bits

fIN = 248 MHz, VIN = FSR − 0.5 dB

7.3 Bits

fIN = 498 MHz, VIN = FSR − 0.5 dB

7.3 6.8 Bits 4, 5, 6

SINAD

Signal to Noise Plus Distortion
Ratio

fIN = 248 MHz, VIN = FSR − 0.5 dB

46 dB

fIN = 498 MHz, VIN = FSR − 0.5 dB

46 42.5 dB 4, 5, 6

SNR Signal to Noise Ratio

fIN = 248 MHz, VIN = FSR − 0.5 dB

46.4 dB

fIN = 498 MHz, VIN = FSR − 0.5 dB

46.4 43 dB 4, 5, 6

THD Total Harmonic Distortion

fIN = 248 MHz, VIN = FSR − 0.5 dB

-58 dB

fIN = 498 MHz, VIN = FSR − 0.5 dB

-58 −49 dB 4, 5, 6

SFDR

Spurious Free Dynamic
Range

fIN = 248 MHz, VIN = FSR − 0.5 dB

57 dB

fIN = 498 MHz, VIN = FSR − 0.5 dB

57 47 dB 4, 5, 6

AC Timing Parameters

The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential
870mV

P-P

, CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, f

CLK

= 1 GHz at 0.5V

P-P

with 50% duty cycle, VBG = Floating,

Non-Extended Control Mode, SDR Mode, R

EXT

= 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω Differential. Boldface

limits apply for TA = T

MIN

to T

MAX

(Notes 5, 6)

Symbol Parameters Conditions Notes

Typical

(Note 7)

Min Max Units

Sub -

groups

AC TIMING PARAMETERS

t

RPW

Reset Pulse Width

4 Clock

Cycles

9, 10, 11

Serial Clock Low Time 4 ns 9, 10, 11

Serial Clock High Time 4 ns 9, 10, 11

t

CAL_L

CAL Pin Low Time

See Figure 9 640 Clock

Cycles

9, 10, 11

t

CAL_H

CAL Pin High Time

See Figure 9 640 Clock

Cycles

9, 10, 11

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ADC08D1000QML

Typical Electrical Characteristics

DC Parameters

The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential
870mV

P-P

, CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, f

CLK

= 1 GHz at 0.5V

P-P

with 50% duty cycle, VBG = Floating,

Non-Extended Control Mode, SDR Mode, R

EXT

= 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω Differential. (Notes 5,

6)

Symbol Parameters Conditions Notes

Typical

(Note 7)

Units

STATIC CONVERTER CHARACTERISTICS

V

OFF

_ADJ Input Offset Adjustment Range Extended Control Mode ±45 mV

FS_ADJ Full-Scale Adjustment Range Extended Control Mode ±20 % FS

NORMAL MODE (Non DES) DYNAMIC CONVERTER CHARACTERISTICS

FPBW Full Power Bandwidth Normal Mode (non DES) 1.7 GHz

B.E.R. Bit Error Rate

10

−18

Error/Sample

Gain Flatness

d.c. to 498 MHz ±0.5 dBFS

d.c. to 1 GHz ±1.0 dBFS

2nd Harm Second Harmonic Distortion

fIN = 100 MHz, VIN = FSR − 0.5 dB

−60 dB

fIN = 248 MHz, VIN = FSR − 0.5 dB

−60 dB

fIN = 498 MHz, VIN = FSR − 0.5 dB

−60 dB

3rd Harm Third Harmonic Distortion

fIN = 100 MHz, VIN = FSR − 0.5 dB

−65 dB

fIN = 248 MHz, VIN = FSR − 0.5 dB

−65 dB

fIN = 498 MHz, VIN = FSR − 0.5 dB

−65 dB

IMD Intermodulation Distortion

f

IN1

= 321 MHz, VIN = FSR − 7 dB

f

IN2

= 326 MHz, VIN = FSR − 7 dB

−50 dB

INTERLEAVE MODE (DES Pin 127=Float) - Dynamic Converter Characteristics

FPBW
(DES)

Full Power Bandwidth Dual Edge Sampling Mode

900 MHz

2nd Harm Second Harmonic Distortion

fIN = 248 MHz, VIN = FSR − 0.5 dB

-64 dB

fIN = 498 MHz, VIN = FSR − 0.5 dB

-64 dB

3rd Harm Third Harmonic Distortion fIN = 248 MHz, VIN = FSR − 0.5 dB

-69 dB

fIN = 498 MHz, VIN = FSR − 0.5 dB

-69 dB

ANALOG INPUT AND REFERENCE CHARACTERISTICS

V

IN

Full Scale Analog Differential Input
Range

FSR pin 14 Low

650

mVp-p
mVp-p

V

CMI

Analog Input Common Mode Voltage V

CMO

mV
mV

CIN

Analog Input Capacitance, Normal
operation

Differential (Note 9) 0.02 pF

Each input pin to ground (Note 9) 1.6 pF

Analog Input Capacitance, DES Mode

Differential (Note 9) 0.08 pF

Each input pin to ground (Note 9) 2.2 pF

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ADC08D1000QML

Symbol Parameters Conditions Notes

Typical

(Note 7)

Units

ANALOG OUTPUT CHARACTERISTICS

V

CMO_LVL

V

CMO

input threshold to set DC

Coupling mode

VA = 1.8V 0.60 V

VA = 2.0V 0.66 V

TC V

CMO

Common Mode Output Voltage
Temperature Coefficient

TA = −55°C to +125°C

238 ppm/°C

C

LOAD VCMO

Maximum V

CMO

load Capacitance

80 pF (max)

TC V

BG

Bandgap Reference Voltage
Temperature Coefficient

TA = −55°C to +125°C,
IBG = ±100 µA

61 ppm/°C

C

LOAD VBG

Maximum Bandgap Reference Load
Capacitance

80 pF (max)

TEMPERATURE DIODE CHARACTERISTICS

ΔV

BE

Temperature Diode Voltage

192 µA vs. 12 µA,
TJ = 25°C

71.23 mV

192 µA vs. 12 µA,
TJ = 125°C

94.8 mV

CHANNEL-TO-CHANNEL CHARACTERISTICS

Offset Match 1 LSB

Positive Full-Scale Match Zero offset selected in Control Register 1 LSB

Negative Full-Scale Match Zero offset selected in Control Register 1 LSB

Phase Matching (I, Q) FIN = 1.0 GHz <1 Degree

X-TALK Crosstalk from I (Agressor) to Q

(Victim) Channel

Aggressor = 867 MHz F.S.
Victim = 100 MHz F.S.

−71 dB

X-TALK Crosstalk from Q (Agressor) to I

(Victim) Channel

Aggressor = 867 MHz F.S.
Victim = 100 MHz F.S.

−71 dB

CLOCK INPUT CHARACTERISTICS

I

I

Input Current VIN = 0 or VIN = V

A

±1 µA

C

IN

Input Capacitance Differential (Note 9) 0.02 pF

Each input to ground (Note 9) 1.5 pF

DIGITAL CONTROL PIN CHARACTERISTICS

C

IN

Input Capacitance Each input to ground (Note 12) 1.2 pF

DIGITAL OUTPUT CHARACTERISTICS

Δ V

ODIFF

Change in LVDS Output Swing
Between Logic Levels

±1 mV

V

OS

Output Offset Voltage VBG = Floating, See Figure 1 800 mV

V

OS

Output Offset Voltage VBG = VA, See Figure 1 (Note 14) 1130 mV

Δ V

OS

Output Offset Voltage Change
Between Logic Levels

±1 mV

I

OS

Output Short Circuit Current Output+ & Output - connected to 0.8V ±4 mA

Z

O

Differential Output Impedance 100 Ohms

V

OH

CalRun H level output IOH = -400uA (Note 11) 1.65 V

V

OL

CalRun L level output IOH = -400uA (Note 11) 0.15 V

POWER SUPPLY CHARACTERISTICS

PSRR1 D.C. Power Supply Rejection Ratio Change in Full Scale Error with change

in VA from 1.8V to 2.0V

30 dB

PSSR2 A.C. Power Supply Rejection Ratio 248 MHz, 50mV

P-P

riding on V

A

51 dB

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