NSC 54F109FMQB, 54F109DMQB, 54F109DC Datasheet
54F/74F109
Dual JK Positive Edge-Triggered Flip-Flop
General Description
The ’F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation
is independent of rise and fall times of the clock waveform.
The JKdesign allows operation as a D flip-flop (refer to ’F74
data sheet) by connecting the J and K inputs.
Asynchronous Inputs:
LOW input to S
D
sets Q to HIGH level
LOW input to CDsets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and SDmakes both Q and Q
HIGH
Features
n Guaranteed 4000V minimum ESD protection.
Ordering Code: See Section 0
Commercial Military Package Package Description
Number
74F109PC N16E 16-Lead (0.300" Wide) Molded Dual-in-Line
54F109DM (Note 2) J16A 16-Lead Ceramic Dual-in-Line
74F109SC (Note 1) M16A 16-Lead (0.150" Wide) Molded Small Outline,
JEDEC
74F109SJ (Note 1) M16D 16-Lead (0.300" Wide) Molded Small Outline,
EIAJ
54F109FM (Note 2) W16A 16-Lead Cerpack
54F109LM (Note 2) E20A 16-Lead Ceramic Leadless Chip Carrier, Type C
Note 1: Devices also available in 13" reel. Use suffix=SCX and SJX.
Note 2: Military grade device with environmental and burn-in processing. Use suffix=DMQB, FMQB and LMQB.
Logic Symbols
FAST®and TRI-STATE®are registered trademarks of National Semiconductor Corporation.
DS009471-3
DS009471-4
IEEE/IEC
DS009471-6
November 1994
54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop
54F/74F109
© 1997 National Semiconductor Corporation DS009471 www.national.com
1
PrintDate=1997/08/28 PrintTime=11:45:22 10182 ds009471 Rev. No. 1 cmserv
Proof 1
DSXXX
Connection Diagrams
Unit Loading/Fan Out
See Section 0 for U.L. definitions
54F/74F
Pin Names Description U.L. Input I
IH/IIL
HIGH/LOW Output IOH/I
OL
J1,J2,K1,K2Data Inputs 1.0/1.0 20 µA/−0.6 mA
CP
1
,CP
2
Clock Pulse Inputs (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA
C
D1,CD2
Direct Clear Inputs (Active LOW) 1.0/3.0 20 µA/−1.8 mA
S
D1,SD2
Direct Set Inputs (Active LOW) 1.0/3.0 20 µA/−1.8 mA
Q
1,Q2,Q1,Q2
Outputs 50/33.3 −1 mA/20 mA
Truth Table
Inputs Outputs
S
D
C
D
CP J K QQ
LHXXXHL
HLXXXLH
LLXXXHH
HH
N
llLH
HH
N
h l Toggle
HH
N
lhQ0Q
0
HH
N
hhH L
HHLXXQ
0
Q
0
H (h)=HIGH Voltage Level
L (l)=LOW Voltage Level
N
=
LOW-to-HIGH Transition
X=Immaterial
Q
0(Q0
)=Before LOW-to-HIGH Transition of Clock
Lower case letters indicate the state of the referenced output one setup time prior to the LOW-to-HIGH clock transition.
Pin Assignment
for DIP, SOIC and Flatpak
DS009471-1
Pin Assignment
for LCC
DS009471-2
PrintDate=1997/08/28 PrintTime=11:45:23 10182 ds009471 Rev. No. 1 cmserv Proof 2
DSXXX
www.national.com 2
Logic Diagram (One Half Shown)
DS009471-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3 www.national.com
PrintDate=1997/08/28 PrintTime=11:45:24 10182 ds009471 Rev. No. 1 cmserv Proof 3
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