NSC 5962-9219601MLA, 5962-9219601MKA, 5962-9219601M3A, 54ACTQ646W-QMLV, 54ACTQ646SDM Datasheet
54ACTQ646
Quiet Series Octal Transceiver/Register with 3-STATE
Outputs
General Description
The ACTQ646 consist of registered bus transceiver circuits,
with outputs, D-type flip-flops, and control circuitry providing
multiplexed transmission of data directly from the input bus
or from the internal storage registers. Data on theAorBbus
will be loaded into the respective registers on the
LOW-to-HIGH transition of the appropriate clock pin (CPAB
or CPBA). Thefourfundamentalhandlingfunctionsavailable
are illustrated in
Figures 1, 2, 3, 4
.
The ACTQ utilizes FSC Quiet Series technology to guarantee quiet output switching and improved dynamic threshold
performance. FACT Quiet Series
™
features GTO™output
control and undershoot corrector in addition to a split ground
bus for superior performance.
Features
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Independent registers for A and B busses
n Multiplexed real-time and stored data transfers
n 300 mil slim dual-in-line package
n Outputs source/sink 24 mA
n Faster prop delays than the standard AC/ACT646
n 4 kV minimum ESD immunity
n Standard Microcircuit Drawing (SMD) 5962-9219601
Logic Symbols
Pin Descriptions
Pin Names Description
A
0–A7
Data Register A Inputs
Data Register A Outputs
B
0–B7
Data Register B Inputs
Data Register B Outputs
CPAB,
CPBA
Clock Pulse Inputs
SAB, SBA Transmit/Receive Inputs
GTO™is a trademark of National Semiconductor Corporation
FACT
™
and FACT Quiet Series™are trademarks of Fairchild Semiconductor Corporation
DS100326-1
IEEE/IEC
DS100326-2
September 1998
54ACTQ646 Quiet Series Octal Transceiver/Register with 3-STATE Outputs
© 1998 National Semiconductor Corporation DS100326 www.national.com
Logic Symbols (Continued)
Pin Descriptions (Continued)
Pin Names Description
G
Output Enable Input
DIR Direction Control Input
Connection Diagram
Pin Assignment
for DIP and Flatpack
DS100326-3
Pin Assignment
for LCC
DS100326-4
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Function Table
Inputs Data I/O (Note 1) Function
G
DIR CPAB CPBA SAB SBA A0–A7B0–B
7
H X H or L H or L X X Isolation
H X N X X X Input Input Clock A
n
Data into A Register
H X X N X X Clock B
n
Data into B Register
LH X X L X A
n
to Bn—Real Time (Transparent Mode)
L H N X L X Input Output Clock A
n
Data into A Register
L H H or L X H X A Register to B
n
(Stored Mode)
L H N X H X Clock A
n
Data into A Register and Output to B
n
LL X X X L Bnto An—Real Time (Transparent Mode)
L L X N X L Output Input Clock B
n
Data into B Register
L L X H or L X H B Register to A
n
(Stored Mode)
L L X N X H Clock B
n
Data into B Register and Output to A
n
H=HIGH Voltage Level
L=LOW Voltage Level
X=Immaterial
N=LOW-to-HIGH Transition
Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled; i.e., data at the
bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs.
Real Time Transfer
A-Bus to B-Bus
DS100326-5
FIGURE 1.
Real Time Transfer
B-Bus to A-Bus
DS100326-6
FIGURE 2.
Storage from
Bus to Register
DS100326-7
FIGURE 3.
Transfer from
Register to Bus
DS100326-8
FIGURE 4.
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