NSC 54ACTQ544SDMQB, 54ACTQ544LMQB, 54ACTQ544FMQB Datasheet
54ACTQ544
Quiet Series Octal Registered Transceiver with
TRI-STATE
®
Outputs
General Description
The ACTQ544 is an inverting octal transceiver containing
two sets of D-type registers for temporary storage of data
flowing in either direction. Separate Latch Enable and Output Enable inputsare provided for each register to permit independent input and output control in either direction of data
flow. The ’544 inverts data in both directions.
The ACTQ utilizes NSC Quiet Series technology to guarantee quiet output switching and improved dynamic threshold
performance. FACT Quiet Series
™
features GTO™output
control and undershoot corrector in addition to a split ground
bus for superior performance.
Features
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n 8-bit inverting octal latched transceiver
n Separate controls for data flow in each direction
n Back-to-back registers for storage
n Outputs source/sink 24 mA
n 4 kV minimum ESD immunity
Logic Symbols
Pin Names Description
OEAB
A-to-B Output Enable Input (Active LOW)
OEBA
B-to-A Output Enable Input (Active LOW)
CEAB
A-to-B Enable Input (Active LOW)
CEBA
B-to-A Enable Input (Active LOW)
LEAB
A-to-B Latch Enable Input (Active LOW)
LEBA
B-to-A Latch Enable Input (Active LOW)
A
0–A7
A-to-B Data Inputs or
B-to-A TRI-STATE Outputs
B
0–B7
B-to-A Data Inputs or
A-to-B TRI-STATE Outputs
GTO™is a trademark of National Semiconductor Corporation.
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
FACT
®
is a registered trademark of Fairchild Semiconductor Corporation.
FACT Quiet Series
™
is a trademark of Fairchild Semiconductor Corporation.
DS100248-1
IEEE/IEC
DS100248-4
August 1998
54ACTQ544 Quiet Series Octal Registered Transceiver with TRI-STATE Outputs
© 1998 National Semiconductor Corporation DS100248 www.national.com
Connection Diagrams
Functional Description
TheACTQ544 contains two sets of eight D-type latches, with
separate input and output controls for each set. For data flow
from A to B, for example, the A-to-B Enable (CEAB) input
must be LOW in order to enter data from A0–A7or take data
from B0–B7, as indicated in the Data I/O Control Table.With
CEAB LOW, a LOW signal on the A-to-B Latch Enable
(LEAB) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEAB signal puts the A
latches in the storage mode and their outputs no longer
change with the A inputs. With CEAB and OEAB both LOW,
the TRI-STATE B output buffers are active and reflect the
data present at the output of the A latches. Control of data
flow from B to A is similar, but using the CEBA, LEBA and
OEBA inputs.
Data I/O Control Table
Inputs Latch Output
CEAB
LEAB OEAB Status Buffers
H X X Latched High Z
X H X Latched —
L L X Transparent —
X X H — High Z
L X L — Driving
H=HIGH Voltage Level
L=LOW Voltage Level
X=Immaterial
A-to-B data flow shown; B-to-A flow control is the same, except using
CEBA, LEBA and OEBA
Pin Assignment for
DIP and Flatpak
DS100248-2
Pin Assignment
for LCC
DS100248-3
www.national.com 2
Logic Diagram
DS100248-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3 www.national.com
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