NSC 54ACTQ16540FMQB Datasheet
54ACTQ16540
16-Bit Inverting Buffer/Line Driver
with TRI-STATE
®
Outputs
General Description
The ’ACTQ16540 contains sixteen inverting buffers with
TRI-STATE outputs designed to be employed as a memory
and address driver, clock driver, or bus-oriented transmitter/
receiver. The device is byte controlled. Each byte has separate TRI-STATE control inputs which can be shorted together
for full 16-bit operation.
The ’ACTQ16540 utilizes NSC Quiet Series technology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Series
®
features GTO
®
output control for superior performance.
Features
n Utilizes NSC FACT Quiet Series technology
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Separate control logic for each byte
n 16-bit version of the ’ACTQ540
n Outputs source/sink 24 mA
n Additional specs for multiple output switching
Logic Symbol
Pin Description
Pin Description
Names
OE
n
Output Enable Input (Active Low)
I
0–I15
Inputs
O
0–O15
Outputs
Connection Diagram
GTO™is a trademark of National Semiconductor Corporation.
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
FACT
™
and FACT Quiet Series™are trademarks of Fairchild Semiconductor Corporation.
DS010927-1
Pin Assignment
for CERPAK
DS010927-2
September 1998
54ACTQ16540 16-Bit Inverting Buffer/Line Driver with TRI-STATE Outputs
© 1998 National Semiconductor Corporation DS010927 www.national.com
Functional Description
The ’ACTQ16540 contains sixteen inverting buffers with
TRI-STATE standard outputs. The device is byte controlled
with each byte functioning identically,but independent of the
other.The control pins may be shorted together to obtain full
16-bit operation. The TRI-STATE outputs are controlled by
an Output Enable (OE
n
) input for each byte. When OEnis
LOW, the outputs are in 2-state mode. When OEnis HIGH,
the outputs are in the high impedance mode, but this does
not interfere with entering new data into the inputs.
Logic Diagram
Truth Table
Inputs Outputs
OE
1
OE
2
I0–I
7
O0–O
7
LL H L
HX X Z
XH X Z
LL L H
Inputs Outputs
OE
3
OE
4
I8–I
15
O8–O
15
LL H L
HX X Z
XH X Z
LL L H
H
=
High Voltage Level
L=Low Voltage Level
X=Immaterial
Z=High Impedance
DS010927-3
www.national.com 2
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