NSC 5962-9452801QXA, 5962-9452801VXA, 54ACTQ16374MDA Datasheet
54ACTQ16374
16-Bit D Flip-Flop with TRI-STATE
®
Outputs
General Description
The ’ACTQ16374 contains sixteen non-inverting D flip-flops
with TRI-STATEoutputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock
(CP) and Output Enable (OE) are common to each byte and
can be shorted together for full 16-bit operation.
The ’ACTQ16245 utilizes NSC Quiet Series technology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Series
®
features GTO
®
output control for superior performance.
Features
n Utilizes NSC FACT Quiet Series technology
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Buffered Positive edge-triggered clock
n Separate control logic for each byte
n 16-bit version of the ’ACTQ374
n Outputs source/sink 24 mA
n Standard Microcircuit Drawing (SMD) 5962-9452801
Logic Symbol
Pin Description
Pin Description
Names
OE
n
Output Enable Input (Active Low)
CP
n
Clock Pulse Input
I
0–I15
Inputs
O
0–O15
Outputs
Connection Diagram
GTO™is a trademark of National Semiconductor Corporation.
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
FACT
™
and FACT Quiet Series™are trademarks of Fairchild Semiconductor Corporation.
DS010935-1
Pin Assignment for
CERPAK
DS010935-2
September 1998
54ACTQ16374 16-Bit D Flip-Flop with TRI-STATE Outputs
© 1998 National Semiconductor Corporation DS010935 www.national.com
Functional Description
The ’ACTQ16374 consists of sixteen edge-triggered
flip-flops with individual D-type inputs and TRI-STATE true
outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control
pins can be shorted together to obtain full 16-bit operation.
Each byte has a buffered clock and buffered Output Enable
common to all flip-flops within that byte. The description
which follows applies to each byte. Each flip-flop will store
the state of their individual D inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CP
n
)
transition. With the Output Enable (OE
n
) LOW, the contents
of the flip-flops are available at the outputs. When OEnis
HIGH, the outputs go to the high impedance state. Operation
of the OE
n
input does not affect the state of the flip-flops.
Truth Tables
Inputs Outputs
CP
1
OE
1
I0–I
7
O0–O
7
NL H H
NL L L
L L X (Previous)
XH X Z
Inputs Outputs
CP
2
OE
2
I8–I
15
O8–O
15
NL H H
NL L L
L L X (Previous)
XH X Z
H
=
High Voltage Level
L=Low Voltage Level
X=Immaterial
Z=High Impedance
Logic Diagrams
Byte 1 (0:7)
DS010935-3
Byte 2 (8:15)
DS010935-4
www.national.com 2
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