NSC 5962-9562001VXA, 5962-9562001QXA, 54ACTQ16245WRQV, 54ACTQ16245MDA, 54ACTQ16245FMQR Datasheet
54ACTQ16245
16-Bit Transceiver with TRI-STATE
®
Outputs
General Description
The ’ACTQ16245 contains sixteen non-inverting bidirectional buffers with TRI-STATE outputs and is intended for
bus oriented applications. The device is byte controlled.
Each has separate control inputs which can be shorted together for full 16-bit operation. The T/R inputs determine the
direction of data flow through the device. The OE inputs disable both theAand B ports by placing them in a high impedance state.
The ’ACTQ16245 utilizes NSC Quiet Series technology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Series
®
features GTO
®
output control for superior performance.
Features
n Utilizes NSC FACT Quiet Series technology
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Bidirectional non-inverting buffers
n Separate control logic for each byte
n 16-bit version of the ’ACTQ245
n Outputs source/sink 24 mA
n Standard Microcircuit Drawing (SMD) 5962-9562001
Logic Symbol
Pin Description
Pin Names Description
OE
n
Output Enable Input (Active Low)
T/R
Transmit/Receive Input
A
0–A15
Side A Inputs/Outputs
B
0–B15
Side B Outputs/Inputs
Connection Diagram
GTO™is a trademark of National Semiconductor Corporation.
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
FACT
™
and FACT Quiet Series™are trademarks of Fairchild Semiconductor Corporation.
DS010926-1
Pin Assignment for CERPAK
DS010926-2
September 1998
54ACTQ16245 16-Bit Transceiver with TRI-STATE Outputs
© 1998 National Semiconductor Corporation DS010926 www.national.com
Functional Description
The ’ACTQ16245 contains sixteen non-inverting bidirectional buffers with TRI-STATE outputs. The device is byte
controlled witheach byte functioning identically, butindependent of theother. The controlpins can be shorted together to
obtain full 16-bit operation. The following description applies
to each byte. When the T/R input is HIGH, then Bus A data
is transmitted to Bus B. When the T/R input is LOW, Bus B
data is transmitted to Bus A. The TRI-STATE outputs are
controlled by an Output Enable (OE
n
) input for each byte.
When OEnis LOW, the outputs are in 2-state mode. When
OEnis HIGH, the outputs are in the high impedance mode,
but this does not interfere with entering new data into the
inputs.
Truth Tables
Inputs Outputs
OE
1
T/R
1
L L Bus B0–B7Data to Bus A0–A
7
L H Bus A0–A7Data to Bus B0–B
7
H X HIGH-Z State on A0–A7,B0–B
7
Inputs Outputs
OE
2
T/R
2
L L Bus B8–B15Data to Bus A8–A
15
L H Bus A8–A15Data to Bus B8–B
15
H X HIGH-Z State on A8–A15,B8–B
15
H=High Voltage Level
L=Low Voltage Level
X=Immaterial
Z=High Impedance
Logic Diagram
DS010926-3
www.national.com 2
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