NSC 54ACTQ16240FMQB Datasheet
54ACTQ16240
16-Bit Inverting Buffer/Line Driver with TRI-STATE
®
Outputs
General Description
The ’ACTQ16240 contains sixteen inverting buffers with
TRI-STATE outputs designed to be employed as a memory
and address driver, clock driver, or bus-oriented transmitter/
receiver. The device is nibble controlled. Each nibble has
separate TRI-STATE control inputs which can be shorted together for full 16-bit operation.
The ’ACTQ16240 utilizes NSC Quiet Series technology to
guarantee quiet output switching and improve dynamic
threshold performance. FACT Quiet Series
™
features
GTO
™
output control for superior performance.
Features
n Utilizes NSC FACT Quiet Series technology
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Separate control logic for each byte
n 16-bit version of the ’ACTQ240
n Outputs source/sink 24 mA
n Standard Microcircuit Drawing (SMD) 5962-9688001
Logic Symbol
Pin Description
Pin Description
Names
OE
n
Output Enable Inputs (Active Low)
I
0–I15
Inputs
O
0–O15
Outputs
Connection Diagram
FACT®is a trademark of National Semiconductor Corporation.
FACT Quiet Series
®
is a trademark of National Semiconductor Corporation.
GTO
®
is a trademark of National Semiconductor Corporation.
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
DS010924-1
Pin Assignment for CERPAK
DS010924-2
September 1998
54ACTQ16240 16-Bit Inverting Buffer/Line Driver with TRI-STATE Outputs
© 1998 National Semiconductor Corporation DS010924 www.national.com
Functional Description
The ’ACTQ16240 contains sixteen inverting buffers with
TRI-STATE standard outputs. The device is nibble (4 bits)
controlled with each nibble functioning identically, but independent of the other. The control pins may be shorted together to obtain full 16-bit operation. The TRI-STATEoutputs
are controlled by an Output Enable (OE
n
) input for each
nibble. When OEnis LOW, the outputs are in 2-state mode.
When OEnis HIGH, the outputs are in the high impedance
mode, but this does not interfere with entering new data into
the inputs.
Logic Diagram
Truth Tables
Inputs Outputs
OE
1
I0–I
3
O0–O
3
LL H
LH L
HX Z
Inputs Outputs
OE
2
I4–I
7
O4–O
7
LL H
LH L
HX Z
H
=
High Voltage Level
L=Low Voltage Level
X=Immaterial
Z=High Impedance
Inputs Outputs
OE
3
I8–I
11
O8–O
11
LL H
LH L
HX Z
Inputs Outputs
OE
4
I12–I
15
O12–O
15
LL H
LH L
HX Z
DS010924-3
www.national.com 2
Loading...