NSC 5962-9314101M3A, 5962-9314101MXA, 54ACT899FMQB, 54ACT899DM Datasheet
54ACT899
9-Bit Latchable Transceiver with Parity
Generator/Checker
General Description
The ACT899 is a 9-bit to 9-bit parity transceiver with transparent latches. The device can operate as a feed-through
transceiver orit can generate/check parity from the 8-bit data
busses in either direction. TheACT899 features independent
latch enables for the A-to-B direction and the B-to-A direction, a select pin for ODD/EVEN parity, and separate error
signal output pins for checking parity.
Features
n Latchable transceiver with output sink of 24 mA
n Option to select generate parity and check or
“feed-through” data/parity in directions A-to-B or B-to-A
n Independent latch enable for A-to-B and B-to-A
directions
n Select pin for ODD/EVEN parity
n ERRA and ERRB output pins for parity checking
n Ability to simultaneously generate and check parity
n May be used in system applications in place of the ’280
n May be used in system applications in place of the ’657
and ’373 (no need to change T/R to check parity)
n 4 kV minimum ESD immunity
n Standard Microcircuit Drawing (SMD) 5962-9314101
Logic Symbol
Connection Diagram
Pin Names Description
A
0–A7
A Bus Data Inputs/Data Outputs
B
0–B7
B Bus Data Inputs/Data Outputs
APAR, BPAR A and B Bus Parity Inputs
ODD/EVEN
ODD/EVEN Parity Select, Active LOW
for EVEN Parity
GBA, GAB
Output Enables for A or B Bus, Active
LOW
SEL
Select Pin for Feed-Through or
Generate Mode, LOW for Generate
Mode
LEA, LEB Latch Enables for A and B Latches,
HIGH for Transparent Mode
ERRA, ERRB
Error Signals for Checking Generated
Parity with Parity In, LOW if Error
Occurs
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
FACT
®
is a registered trademark of Fairchild Semiconductor Corporation.
DS100245-1
Pin Assignment for LCC
DS100245-2
August 1998
54ACT899 9-Bit Latchable Transceiver with Parity Generator/Checker
© 1998 National Semiconductor Corporation DS100245 www.national.com
Functional Description
The ACT899 has three principal modes of operation which
are outlined below. These modes apply to both the A-to-B
and B-to-A directions.
•
BusA (B) communicates to Bus B (A), parity is generated
and passed on to the B (A) Bus as BPAR (APAR).If LEB
(LEA) is HIGH and the Mode Select (SEL) is LOW, the
parity generated from B[0:7] (A[0:7]) can be checked and
monitored by ERRB (ERRA).
•
Bus A (B) communicates to Bus B (A) in a feed-through
mode if SEL is HIGH. Parity is still generated and
checked as ERRA and ERRB in the feed-through mode
(can be used as an interrupt to signal a data/parity bit error to the CPU).
•
Independent Latch Enables (LEA and LEB) allow other
permutations of generating/checking (see Function Table
below).
Function Table
Inputs Operation
GAB
GBA SEL LEA LEB
H H X X X Busses A and B are TRI-STATE
®
.
H L L L H Generates parity from B[0:7] based on O/E (Note 1). Generated parity
→
APAR. Generated parity checked against BPAR and output as
ERRB.
H L L H H Generates parity from B[0:7] based on O/E. Generated parity
→
APAR. Generated parity checked against BPAR and output as ERRB.
Generated parity also fed back through the A latch for generate/check
as ERRA.
H L L X L Generates parity from B latch data based on O/E. Generated parity
→
APAR. Generated parity checked against latched BPAR and output as
ERRB.
H L H X H BPAR/B[0:7]→APAR/A0:7] Feed-through mode. Generated parity
checked against BPAR and output as ERRB.
H L H H H BPAR/B[0:7]→APAR/A[0:7]
Feed-through mode. Generated parity checked against BPAR and
output as ERRB. Generated parity also fed back through the A latch
for generate/check as ERRA.
L HLHLGenerates parity for A[0:7] based on O/E. Generated parity→BPAR.
Generated parity checked against APAR and output as ERRA.
L H L H H Generates parity from A[0:7] based on O/E. Generated parity
→
BPAR. Generated parity checked against APAR and output as ERRA.
Generated parity also fed back through the B latch for generate/check
as ERRB.
L H L L X Generates parity from A latch data based on O/E. Generated parity
→
BPAR. Generated parity checked against latched APAR and output as
ERRA.
L H H H L APAR/A[0:7]→BPAR/B[0:7]
Feed-through mode. Generated parity checked against APAR and
output as ERRA.
L HHHHAPAR/A[0:7]→BPAR/B[0:7]
Feed-through mode. Generated parity checked against APAR and
output as ERRA. Generated parity also fed back through the B latch
for generate/check as ERRB.
H=HIGH Voltage Level
L=LOW Voltage Level
X=Immaterial
Note 1: O/E=ODD/EVEN
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Functional Block Diagram
AC Path
DS100245-3
DS100245-4
An,APAR→Bn,BPAR
(B
n
,BPAR→An, APAR)
FIGURE 1.
DS100245-5
A
n
→
BPAR
(B
n
→
APAR)
FIGURE 2.
3 www.national.com
AC Path (Continued)
DS100245-6
A
n
→
ERRA
(B
n
→
ERRB)
FIGURE 3.
DS100245-7
O/E→ERRA
O/E→ERRB
FIGURE 4.
DS100245-8
O/E→BPAR
(O/E→APAR)
FIGURE 5.
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