NSC 5962R8766401SA, 5962R8766401RA, 5962R87664012A, 5962-8766401SA, 5962-8766401RA Datasheet
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54ACT573
Octal Latch with TRI-STATE
®
Outputs
General Description
The ’ACT573 is a high-speed octal latch with buffered common LatchEnable (LE) and buffered common Output Enable
(OE) inputs.
The ’ACT573 is functionally identical to the ’ACT373 but has
inputs and outputs on opposite sides.
Features
n ICCand IOZreduced by 50
%
n Inputs and outputs on opposite sides of package
allowing easy interface with microprocessors
n Useful as input or output port for microprocessors
n Functionally identical to ’ACT373
n TRI-STATE outputs for bus interfacing
n Outputs source/sink 24 mA
n ’ACT573 has TTL-compatible inputs
n Standard Military Drawing (SMD)
— ’ACT573: 5962-87664
Logic Symbols
Pin Names Description
D
0–D7
Data Inputs
LE Latch Enable Input
OE
TRI-STATE Output Enable Input
O
0–O7
TRI-STATE Latch Outputs
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
FACT
®
is a registered trademark of Fairchild Semiconductor Corporation.
DS100332-1
IEEE/IEC
DS100332-2
August 1998
54ACT573 Octal Latch with TRI-STATE Outputs
© 1998 National Semiconductor Corporation DS100332 www.national.com
Connection Diagrams
Pin Assignment for DIP
and Flatpak
DS100332-3
Pin Assignment for LCC
DS100332-4
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Functional Description
The ’ACT573 contains eight D-type latches with TRI-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data onthe D
n
inputs entersthe latches. Inthis condition the
latches are transparent, i.e., a latch output will change state
each time its D input changes. When LE is LOW the latches
store the information that was present on the D inputs a
setup timepreceding the HIGH-to-LOW transition of LE. The
TRI-STATE buffers are controlled by the Output Enable (OE)
input. When OE is LOW, the buffers are enabled. When OE
is HIGH the buffers are in the high impedance mode but this
does not interfere with entering new data into the latches.
Truth Table
Inputs Outputs
OE
LE D O
n
LHH H
LHL L
LLX O
0
HXX Z
H
=
HIGH Voltage
L=LOW Voltage
Z=High Impedance
X=Immaterial
O
0
=
Previous O
0
before HIGH-to-LOW transition of Latch Enable
Logic Diagram
DS100332-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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