NSC 5962R9093401QFA, 5962R9093401QEA, 5962R9093401Q2A, 54ACT399LMQB, 54ACT399JRQMLV Datasheet

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54ACT399 Quad 2-Port Register

General Description

The ’AC/ACT399 is the logical equivalent of a quad 2-input multiplexer feedinginto four edge-triggered flip-flops. Acommon Select input determines which of the two 4-bit words is accepted. The selected data enters the flip-flop on the rising edge of the clock.

Features

n ICCreduced by 50

n Select inputs from two data sources n Fully positive edge-triggered operation n Outputs source/sink 24 mA n ACT399 has TTL-compatible inputs

Logic Symbols Connection Diagrams

Pin Names Description

S Common Select Input CP Clock Pulse Input I

0a–I0d

Data Inputs from Source 0

1a–I1d

Data Inputs from Source 1

a–Qd

TRI-STATE®is a registered trademark of National Semiconductor Corporation. FACT

is a registered trademark of Fairchild Semiconductor Corporation.

DS100356-1

IEEE/IEC

DS100356-5

Pin Assignment

for DIP and Flatpak

DS100356-3

Pin Assignment

for LCC

DS100356-2

August 1998

54ACT399 Quad 2-Port Register

Functional Description

The ’AC/ACT399 is a high-speed quad 2-port register. It selects four bits of data from either of two sources (Ports) under control of a common Select input (S). The selected data is transferred to a 4-bit output register synchronous with the LOW-to-HIGH transition of the Clock input (CP). The 4-bit D-type output register is fully edge-triggered. The Data inputs (I

0x,I1x

) and Selectinput (S) must bestable only asetup time prior to and hold time after the LOW-to-HIGH transition of the Clock input for predictable operation.

Function Table

Inputs Outputs

I1CP Q Q

LL X

LH X

HX L

HX H

HIGH Voltage Level L=LOW Voltage Level X=Immaterial

LOW-to-HIGH Clock Transition

Logic Diagram

DS100356-4

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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