NSC 5962-8763101SA, 5962-8763101RA, 5962-87631012A, 54ACT374FM-MLS, 54ACT374DM Datasheet
54AC374•54ACT374
Octal D Flip-Flop with TRI-STATE
®
Outputs
General Description
The ’AC/’ACT374 is a high-speed, low-power octal D-type
flip-flop featuring separate D-type inputs for each flip-flop
and TRI-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all
flip-flops.
Features
n ICCand IOZreduced by 50
%
n Buffered positive edge-triggered clock
n TRI-STATE outputs for bus-oriented applications
n Outputs source/sink 24 mA
n See ’273 for reset version
n See ’377 for clock enable version
n See ’373 for transparent latch version
n See ’574 for broadside pinout version
n See ’564 for broadside pinout version with inverted
outputs
n ’ACT374 has TTL-compatible inputs
n Standard Military Drawing (SMD)
— ’AC374: 5962-87694
— ’ACT374: 5962-87631
Logic Symbols
Pin
Names
Description
D
0–D7
Data Inputs
CP Clock Pulse Input
OE
TRI-STATE Output Enable Input
O
0–O7
TRI-STATE Outputs
TRI-STATE®is a registered trademarkof National Semiconductor Corporation.
FACT
®
is a registered trademark of Fairchild Semiconductor Corporation.
DS100289-1
IEEE/IEC
DS100289-2
August 1998
54AC374
•
54ACT374 Octal D Flip-Flop with TRI-STATE Outputs
© 1998 National Semiconductor Corporation DS100289 www.national.com
Connection Diagrams
Functional Description
The ’AC/’ACT374 consists of eight edge-triggered flip-flops
with individual D-type inputs and TRI-STATE true outputs.
The buffered clock and bufferedOutput Enableare common
to all flip-flops.The eight flip-flops will store the stateof their
individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the
Output Enable (OE) LOW, the contents of the eight flip-flops
are available at the outputs. When the OE is HIGH, the outputs go to the highimpedance state. Operationof theOE input does not affect the state of the flip-flops.
Truth Table
Inputs Outputs
D
n
CP OE O
n
H
N
LH
L
N
LL
XXH Z
H
=
HIGH Voltage Level
L=LOW Voltage Level
X=Immaterial
Z=High Impedance
N
=
LOW-to-HIGH Transition
Logic Diagram
Pin Assignment for DIP
and Flatpak
DS100289-3
Pin Assignment for LCC
DS100289-4
DS100289-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
) −0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
=
−0.5V −20 mA
V
I
=
V
CC
+ 0.5V +20 mA
DC Input Voltage (V
I
) −0.5V to VCC+ 0.5V
DC Output Diode Current (I
OK
)
V
O
=
−0.5V −20 mA
V
O
=
V
CC
+ 0.5V +20 mA
DC Output Voltage (V
O
) −0.5V to VCC+ 0.5V
DC Output Source
or Sink Current (I
O
)
±
50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
±
50 mA
Storage Temperature (T
STG
) −65˚C to +150˚C
Junction Temperature (T
J
)
CDIP 175˚C
Recommended Operating
Conditions
Supply Voltage (VCC)
’AC 2.0V to 6.0V
’ACT 4.5V to 5.5V
Input Voltage (V
I
) 0VtoV
CC
Output Voltage (VO) 0VtoV
CC
Operating Temperature (TA)
54AC/ACT −55˚C to +125˚C
Minimum Input Edge Rate (∆V/∆t)
’AC Devices
V
IN
from 30%to 70%of V
CC
V
CC
@
3.3V, 4.5V, 5.5V 125 mV/ns
Minimum Input Edge Rate (∆V/∆t)
’ACT Devices
V
IN
from 0.8V to 2.0V
V
CC
@
4.5V, 5.5V 125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of FACT
®
circuits outside databook specifications.
DC Characteristics for ’AC Family Devices
54AC
Symbol Parameter V
CC
T
A
=
−55˚C to +125˚C Units Conditions
(V) Guaranteed Limits
V
IH
Minimum High 3.0 2.1 V
OUT
=
0.1V
Level Input 4.5 3.15 V or V
CC
− 0.1V
Voltage 5.5 3.85
V
IL
Maximum Low 3.0 0.9 V
OUT
=
0.1V
Level Input 4.5 1.35 V or V
CC
− 0.1V
Voltage 5.5 1.65
V
OH
Minimum High 3.0 2.9 I
OUT
=
−50 µA
Level Output 4.5 4.4 V
Voltage 5.5 5.4
(Note 2)
V
IN
=
V
IL
or V
IH
3.0 2.4 −12 mA
4.5 3.7 V I
OH
−24 mA
5.5 4.7 −24 mA
V
OL
Maximum Low 3.0 0.1 I
OUT
=
50 µA
Level Output 4.5 0.1 V
Voltage 5.5 0.1
(Note 2)
V
IN
=
V
IL
or V
IH
3.0 0.50 12 mA
4.5 0.50 V I
OL
24 mA
5.5 0.50 24 mA
I
IN
Maximum Input 5.5
±
1.0 µA V
I
=
V
CC
, GND
Leakage Current
I
OZ
Maximum VI(OE)=VIL,V
IH
TRI-STATE 5.5
±
5.0 µA V
I
=
V
CC
, GND
Current V
O
=
V
CC
, GND
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