NSC 5962-8755601SA, 5962-8755601RA, 5962-87556012A, 54ACT373FM-MLS, 54ACT373DM-MLS Datasheet
54AC373•54ACT373
Octal Transparent Latch with TRI-STATE
®
Outputs
General Description
The ’AC/’ACT373 consists of eight latches with TRI-STATE
outputs forbus organized system applications. The flip-flops
appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup time
is latched. Data appears on the bus when the Output Enable
(OE) is LOW. When OE isHIGH, the bus outputis in the high
impedance state.
Features
n ICCand IOZreduced by 50
%
n Eight latches in a single package
n TRI-STATE outputs for bus interfacing
n Outputs source/sink 24 mA
n ’ACT373 has TTL-compatible inputs
n Standard Microcircuit Drawing (SMD)
— ’AC373: 5962-87555
— ’ACT373: 5962-87556
Logic Symbols
Pin Names Description
D
0–D7
Data Inputs
LE Latch Enable Input
OE
Output Enable Input
O
0–O7
TRI-STATE Latch Outputs
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
FACT
®
is a registered trademark of Fairchild Semiconductor Corporation.
DS100329-1
IEEE/IEC
DS100329-2
August 1998
54AC373
•
54ACT373 Octal Transparent Latch with TRI-STATE Outputs
© 1998 National Semiconductor Corporation DS100329 www.national.com
Connection Diagrams
Functional Description
The ’AC/’ACT373 contains eight D-type latches with
TRI-STATE standard outputs. When the Latch Enable (LE)
input is HIGH, data on the D
n
inputs enters the latches. In
this condition the latches are transparent, i.e., a latch output
will change state each time its D input changes. When LE is
LOW, the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATEstandard outputs are controlled
by the Output Enable (OE)input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the
standard outputs are in the high impedance mode but this
does not interfere with entering new data into the latches.
Truth Table
Inputs Outputs
LE OE
D
n
O
n
XHX Z
HLL L
HLH H
LLX O
0
H
=
HIGH Voltage Level
L=LOW Voltage Level
Z=High Impedance
X=Immaterial
O
0
=
Previous O
0
before HIGH to Low transition of Latch Enable
Pin Assignment for DIP
and Flatpak
DS100329-3
Pin Assignment for LCC
DS100329-4
www.national.com 2
Logic Diagram
DS100329-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3 www.national.com
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