NSC 54ACT283LMQB, 54ACT283FMQB, 54ACT283DMQB Datasheet
54ACT283
4-Bit Binary Full Adder with Fast Carry
General Description
The ’ACT283 high-speed 4-bit binary full adder with internal
carry lookahead accepts two 4-bit binary words (A
0–A3
,
B
0–B3
) and a Carry input (C0). It generates the binary Sum
outputs (S
0–S3
) andthe Carry output (C4) from the most significant bit. The ’ACT283 will operate with either active HIGH
or active LOW operands (positive or negative logic).
Features
n Guaranteed 4000V minimum ESD protection
n Outputs source/sink 24 mA
n TTL-compatible inputs
n Available to Mil-Std-883
Logic Symbols
Connection Diagrams
Functional Description
The ’ACT283 adds two 4-bit binary words (A plus B) plus the
incoming Carry (C
0
). The binary sum appears on the Sum
(S
0–S3
) and outgoing carry (C4) outputs. The binary weight
of the various inputs and outputs is indicated by the subscript
numbers, representing powers of two.
2
0
(A0+B0+C0)+21(A1+B1)
+2
2
(A2+B2)+23(A3+B3)
=
S
0
+2S1+4S2+8S3+ 16C
4
Where (+)=plus
Interchanging inputs of equal weight does not affect the operation. Thus C
0,A0,B0
can be arbitrarily assigned to pins 5,
6 and 7 for DIPS, and 7, 8 and 9 for chip carrier packages.
Due to the symmetry of the binary add function, the ’ACT283
can be used either with all inputs and outputs active HIGH
(positive logic) or with all inputs and outputs active LOW
(negative logic). See
Figure 1
. Note that if C0is not used it
must be tied LOW for active HIGH logic or tied HIGH for active LOW logic.
Due to pin limitations, the intermediate carries of the
’ACT283 are not brought out for use as inputs or outputs.
However, other means can be used to effectively insert a
carry into, or bring a carry out from, an intermediate stage.
Figure 2
shows how to make a 3-bit adder. Tying the oper-
and inputs of the fourth adder (A
3,B3
) LOW makes S3dependent only on, and equal to, the carry from the third adder.
Using somewhat the same principle,
Figure 3
shows a way
of dividing the ’ACT283 into a 2-bit and a 1-bit adder. The
third stage adder (A
2,B2,S2
) is used merely as a means of
getting a carry (C
10
) signal into the fourth stage (via A2and
B
2
) and bringing out the carry from the second stage on S2.
DS100977-1
IEEE/IEC
DS100977-4
Pin Assignment
for DIP and Flatpak
DS100977-2
Pin Assignment for LCC
DS100977-3
September 1998
54ACT283 4-Bit Binary Full Adder with Fast Carry
© 1998 National Semiconductor Corporation DS100977 www.national.com
Functional Description (Continued)
Note that as long as A
2
and B2are the same, whether HIGH
or LOW, they do not influence S
2
. Similarly, when A2and B
2
are the same the carry into the third stage does not influence
the carry out of the third stage.
Figure 4
shows a method of
implementing a 5-input encoder, where the inputs are
equally weighted. The outputs S
0,S1
and S2present a bi-
nary number equal to the number of inputs I
1–I5
that are
true.
Figure 5
shows one method of implementing a 5-input
majority gate. When three or more of the inputs I
1–I5
are
true, the output M
5
is true.
C0A0A1A2A3B0B1B2B3S0S1S2S3C
4
Logic Levels L L H L H H L L H H H L L H
Active HIGH 00101100111001
Active LOW 11010011000110
Active HIGH:0+10+9=3 + 16 Active LOW:1+5+6=12+0
FIGURE 1. Active HIGH versus Active LOW Interpretation
DS100977-5
FIGURE 2. 3-Bit Adder
DS100977-6
FIGURE 3. 2-Bit and 1-Bit Adders
DS100977-7
FIGURE 4. 5-Input Encoder
DS100977-8
FIGURE 5. 5-Input Majority Gate
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Logic Diagram
DS100977-9
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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