NSC 5962R8755401SFA, 5962R8755401SEA, 5962R8755401S2A, 5962R8755401BFA, 5962R8755401BEA Datasheet

54AC138•54ACT138
1-of-8 Decoder/Demultiplexer

General Description

The ’AC/’ACT138 is a high-speed 1-of-8 decoder/
demultiplexer.This device is ideally suited for high-speed bi­polar memory chip select address decoding. The multiple in­put enables allow parallel expansion to a 1-of-24 decoder
using just three ’AC/’ACT138 devices or a 1-of-32 decoder
using four ’AC/’ACT138 devices and one inverter.

Features

n ICCreduced by 50

%

n Demultiplexing capability
n Multiple input enable for easy expansion
n Active LOW mutually exclusive outputs
n Outputs source/sink 24 mA
n ’ACT138 has TTL-compatible inputs
n Standard Microcircuit Drawing (SMD)

— ’AC138: 5962-87622
— ’ACT138: 5962-87554

Logic Symbols

Pin Names Description

A

0–A2

Address Inputs

E

1–E2

Enable Inputs

E

3

Enable Input

O

0–O7

Outputs

Connection Diagrams

FACT®is a registered trademark of Fairchild Semiconductor Corporation.

DS100268-1

IEEE/IEC

DS100268-7

Pin Assignment

for DIP and Flatpak

DS100268-2

Pin Assignment

for LCC

DS100268-3

August 1998

54AC138

•

54ACT138 1-of-8 Decoder/Demultiplexer

© 1998 National Semiconductor Corporation DS100268 www.national.com

Functional Description

The ’AC/’ACT138 high-speed 1-of-8 decoder/demultiplexer
accepts three binary weighted inputs (A

0,A1,A2

) and, when
enabled, provides eight mutually exclusive active-LOW out­puts (O

0–O7

). The ’AC/’ACT138 features three Enable in­puts, two active-LOW (E1,E2) and one active-HIGH (E3). All
outputs will be HIGH unless E1and E2are LOW and E3is
HIGH. This multiple enable function allows easy parallel ex-

pansion of the device to a 1-of-32 (5 lines to 32 lines) de­coder with just four ’AC/’ACT138 devices and one inverter
(see

Figure 1

). The ’AC/’ACT138 canbe used as an8-output
demultiplexer by using one of the active LOW Enable inputs
as the data input and the other Enable inputsas strobes. The
Enable inputs which are not used must be permanently tied
to their appropriate active-HIGH or active-LOW state.

Truth Table

Inputs Outputs

E

1E2E3A0A1A2O0O1O2O3O4O5O6O7

HXXXXXHHHHHHHH
XHXXXXHHHHHHHH
XXLXXXHHHHHHHH

LLHLLLLHHHHHHH
LLHHLLHLHHHHHH
LLHLHLHHLHHHHH
LLHHHLHHHLHHHH

LLHLLHHHHHLHHH
LLHHLHHHHHHLHH
LLHLHHHHHHHHLH
LLHHHHHHHHHHHL

H=HIGH Voltage Level
L=LOW Voltage Level
X=Immaterial

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Logic Diagram

DS100268-4

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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