NSC 5962R8853401VFA, 5962R8853401VEA, 5962R8853401V2A, 5962R8853401FA, 5962R8853401EA Datasheet
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54AC109•54ACT109
Dual JK Positive Edge-Triggered Flip-Flop
General Description
The ’AC/’ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock
waveform. The JK design allows operation as a D flip-flop
(refer to ’AC/’ACT74 data sheet) by connecting the J and K
inputs together.
Asynchronous Inputs:
LOW input to S
D
(Set) sets Q to HIGH level
LOW input to CD(Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and SDmakes both Q and Q
HIGH
Features
n ICCreduced by 50
%
n Outputs source/sink 24 mA
n ’ACT109 has TTL-compatible inputs
n Standard Military Drawing (SMD)
—’AC109: 5962-89551
—’ACT109: 5962-88534
Logic Symbol
Pin Names Description
J
1,J2,K1,K2
Data Inputs
CP
1
,CP
2
Clock Pulse Inputs
C
D1,CD2
Direct Clear Inputs
S
D1,SD2
Direct Set Inputs
Q
1,Q2,Q1,Q2
Outputs
FACT®is a registered trademark of Fairchild Semiconductor Corporation.
DS100267-1
DS100267-2
IEEE/IEC
DS100267-7
August 1998
54AC109
•
54ACT109 Dual JK Positive Edge-Triggered Flip-Flop
© 1998 National Semiconductor Corporation DS100267 www.national.com
Connection Diagrams
Truth Table
(each half)
Inputs Outputs
S
D
C
D
CP J K QQ
LHXXXHL
HLXXXLH
LLXXXHH
HH
N
LL L H
HH
N
H L Toggle
HH
N
LHQ0Q
0
HH
N
HH H L
HHLXXQ
0
Q
0
H
=
HIGH Voltage Level
L=LOW Voltage Level
N
=
LOW-to-HIGH Transition
X=Immaterial
Q
0(Q0
)=Previous Q0(Q0) before LOW-to-HIGH Transition of Clock
Logic Diagram (one half shown)
Pin Assignment
for DIP and Flatpak
DS100267-3
Pin Assignment
for LCC
DS100267-4
DS100267-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
) −0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
=
−0.5V −20 mA
V
I
=
V
CC
+ 0.5V +20 mA
DC Input Voltage (V
I
) −0.5V to VCC+ 0.5V
DC Output Diode Current (I
OK
)
V
O
=
−0.5V −20 mA
V
O
=
V
CC
+ 0.5V +20 mA
DC Output Voltage (V
O
) −0.5V to VCC+ 0.5V
DC Output Source
or Sink Current (I
O
)
±
50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
±
50 mA
Storage Temperature (T
STG
) −65˚C to +150˚C
Junction Temperature (T
J
)
CDIP 175˚C
Recommended Operating
Conditions
Supply Voltage (VCC)
’AC 2.0V to 6.0V
’ACT 4.5V to 5.5V
Input Voltage (V
I
) 0VtoV
CC
Output Voltage (VO) 0VtoV
CC
Operating Temperature (TA)
54AC/ACT −55˚C to +125˚C
Minimum Input Edge Rate (∆V/∆t)
’AC Devices
V
IN
from 30%to 70%of V
CC
V
CC
@
3.3V, 4.5V, 5.5V 125 mV/ns
Minimum Input Edge Rate (∆V/∆t)
’ACT Devices
V
IN
from 0.8V to 2.0V
V
CC
@
4.5V, 5.5V 125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of FACT
®
circuits outside databook specifications.
DC Characteristics for ’AC Family Devices
54AC
Symbol Parameter V
CC
T
A
=
−55˚C to +125˚C Units Conditions
(V) Guaranteed Limits
V
IH
Minimum High Level 3.0 2.1 V
OUT
=
0.1V
Input Voltage 4.5 3.15 V or V
CC
− 0.1V
5.5 3.85
V
IL
Maximum Low Level 3.0 0.9 V
OUT
=
0.1V
Input Voltage 4.5 1.35 V or V
CC
− 0.1V
5.5 1.65
V
OH
Minimum High Level 3.0 2.9 I
OUT
=
−50 µA
Output Voltage 4.5 4.4 V
5.5 5.4
(Note 2)
V
IN
=
V
IL
or V
IH
3.0 2.4 I
OH
=
−12 mA
4.5 3.7 V I
OH
=
−24 mA
5.5 4.7 I
OH
=
−24 mA
V
OL
Maximum Low Level 3.0 0.1 I
OUT
=
50 µA
Output Voltage 4.5 0.1 V
5.5 0.1
(Note 2)
V
IN
=
V
IL
or V
IH
3.0 0.5 I
OL
=
12 mA
4.5 0.5 V I
OL
=
24 mA
5.5 0.5 I
OL
=
24 mA
I
IN
Maximum Input 5.5
±
1.0 µA V
I
=
V
CC
, GND
Leakage Current
(Note 3)
Minimum Dynamic
Output Current
I
OLD
5.5 50 mA V
OLD
=
1.65V Max
I
OHD
5.5 −50 mA V
OHD
=
3.85V Min
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