NSC 5962-9217801MRA, 5962-9217801MSA, 5962-9217801M2A, 54ACQ373MDA Datasheet
54ACQ373•54ACTQ373
Quiet Series Octal Transparent Latch with TRI-STATE
®
Outputs
General Description
The ’ACQ/’ACTQ373 consists of eight latches with
TRI-STATE outputs for bus organized system applications.
The latches appear transparent to the data when Latch Enable (LE) is HIGH. When LE is low,thedata satisfying the input timing requirements is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH,
the bus output is in the high impedance state.
The ’ACQ/’ACTQ373 utilizes NSC Quiet Series technology
to guarantee quiet output switching and improve dynamic
threshold performance. FACT Quiet Series
™
features
GTO
™
output control and undershoot corrector in addition to
a split ground bus for superior performance.
Features
n ICCand IOZreduced by 50
%
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Improved latch up immunity
n Eight latches in a single package
n TRI-STATE outputs drive bus lines or buffer memory
address registers
n Outputs source/sink 24 mA
n Faster prop delays than the standard ’AC/’ACT373
n 4 kV minimum ESD immunity (’ACQ)
n Standard Military Drawing (SMD)
—’ACTQ373: 5962-92188
—’ACQ373: 5962-92178
Logic Symbols
Pin Names Description
D
0–D7
Data Inputs
LE Latch Enable Input
OE
Output Enable Input
O
0–O7
TRI-STATE Latch Outputs
GTO™is a trademark of NationalSemiconductor Corporation.
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
FACT
®
is a registered trademark of Fairchild Semiconductor Corporation.
FACT Quiet Series
™
is a trademark of Fairchild Semiconductor Corporation.
DS100238-1
IEEE/IEC
DS100238-2
September 1998
54ACQQ373
•
54ACTQ373 Quiet Series Octal Transparent Latch with TRI-STATE Outputs
© 1998 National Semiconductor Corporation DS100238 www.national.com
Connection Diagrams
Functional Description
The ’ACQ/’ACTQ373 contains eight D-type latches with
TRI-STATE standard outputs. When the Latch Enable (LE)
input is HIGH, data on the D
n
inputs enters the latches. In
this condition the latches are transparent, i.e., a latch output
will change state each time its D input changes. When LE is
LOW, the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE standard outputs are controlled
by the Output Enable (OE) input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the
standard outputs are in the high impedance mode but this
does not interfere with entering new data into the latches.
Truth Table
Inputs Outputs
LE OE
D
n
O
n
XHX Z
HLL L
HLH H
LLX O
0
H
=
HIGH Voltage Level
L=LOW Voltage Level
Z=High Impedance
X=Immaterial
O
0
=
Previous O
0
before HIGH to Low transition of Latch Enable
Logic Diagram
Pin Assignment for
DIP and Flatpak
DS100238-3
Pin Assignment
for LCC
DS100238-4
DS100238-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
) −0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
=
−0.5V −20 mA
V
I
=
V
CC
+ 0.5V +20 mA
DC Input Voltage (V
I
) −0.5V to VCC+ 0.5V
DC Output Diode Current (I
OK
)
V
O
=
−0.5V −20 mA
V
O
=
V
CC
+ 0.5V +20 mA
DC Output Voltage (V
O
) −0.5V to VCC+ 0.5V
DC Output Source
or Sink Current (I
O
)
±
50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
±
50 mA
Storage Temperature (T
STG
) −65˚C to +150˚C
DC Latchup Source
or Sink Current
±
300 mA
Junction Temperature (T
J
)
CDIP 175˚C
Recommended Operating
Conditions
Supply Voltage (VCC)
’ACQ 2.0V to 6.0V
’ACTQ 4.5V to 5.5V
Input Voltage (V
I
) 0VtoV
CC
Output Voltage (VO) 0VtoV
CC
Operating Temperature (TA)
54ACQ/ACTQ −55˚C to +125˚C
Minimum Input Edge Rate ∆V/∆t
’ACQ Devices
V
IN
from 30%to 70%of V
CC
V
CC
@
3.0V, 4.5V, 5.5V 125 mV/ns
Minimum Input Edge Rate ∆V/∆t
’ACTQ Devices
V
IN
from 0.8V to 2.0V
V
CC
@
4.5V, 5.5V 125 mV/ns
Note: All commercial packaging is not recommended for applications requiring greater than 2000 temperature cycles from −40˚C to +125˚C.
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of FACT
®
circuits outside databook specifications.
DC Characteristics for ’ACQ Family Devices
54ACQ
Symbol Parameter V
CC
T
A
=
Units Conditions
(V) −55˚C to +125˚C
Guaranteed Limits
V
IH
Minimum High Level 3.0 2.1 V
OUT
=
0.1V
Input Voltage 4.5 3.15 V or V
CC
− 0.1V
5.5 3.85
V
IL
Maximum Low Level 3.0 0.9 V
OUT
=
0.1V
Input Voltage 4.5 1.35 V or V
CC
− 0.1V
5.5 1.65
V
OH
Minimum High Level 3.0 2.9 I
OUT
=
−50 µA
Output Voltage 4.5 4.4 V
5.5 5.4
(Note 2)
V
IN
=
V
IL
or V
IH
3.0 2.4 I
OH
=
−12 mA
4.5 3.7 V I
OH
=
−24 mA
5.5 4.7 I
OH
=
−24 mA
V
OL
Maximum Low Level 3.0 0.1 I
OUT
=
50 µA
Output Voltage 4.5 0.1 V
5.5 0.1
(Note 2)
V
IN
=
V
IL
or V
IH
3.0 0.50 I
OL
=
12 mA
4.5 0.50 V I
OL
=
24 mA
5.5 0.50 I
OL
=
24 mA
I
IN
Maximum Input 5.5
±
1.0 µA V
I
=
V
CC
, GND
Leakage Current (Note 4)
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